September 30, 2014 [14MVD0089]

Digital IC Design LAB

NAND LAYOUT
Nand lay out 1
September 30, 2014 [14MVD0089]
AIM: To observe the following NAN gate !hara!teristi!s using "!aden!e
virtuoso software
a#To !onstru!t a layout for the designed NAN gate
DEI!N:
C"#s nan$ s%&e"ati%
'e%i(i%ati#ns:
$n%$p%100nm , &n%120nm, &p%1''nm
La)#*t:
Nand lay out 2
September 30, 2014 [14MVD0089]
D+C:
Nand lay out 3
September 30, 2014 [14MVD0089]
La)#*t ,it& +C E-t.a%ti#n:
Nan$ %i.%*it *sing %.eate$ s)"/#l:
D% anal)sis:
Nand lay out 4
September 30, 2014 [14MVD0089]

O/se.0ati#ns:
(m for sour!e 1)a#%*+,-.*mv /pin0 !olor1
(m for sour!e 1)b#%*4'-'1mv /green !olor1
(m for !ommon sour!e%,33-10mv /red !olor]
T.ansient anal)sis
A] s%&e"ati% ,it& se'a.ate in'*ts


Nand lay out '
September 30, 2014 [14MVD0089]
Dela) anal)sis
Dela) %al%*lati#n:
1- 2ropagation rise delay )tpdr#%3-**ps
2ropagation fall delay )tpdf#%*-3.ps
Average propagation delay)tpd#%/)tpdr3tpdf#421%'-02'ps
2- !ontamination rise delay )t!dr#%2-.*ps
!ontamination fall delay )t!df#%1-00*ps
average !ontamination delay )t!d#%/)t!dr3t!df#421%1-.,3ps

1#,e. anal)sis:
Nand lay out *
September 30, 2014 [14MVD0089]
1#,e. %al%*lati#n:
Total power%3-2'*4mv Average power%2-,23uw
2ower of N50%341-4.uw 2ower of N51%.,.-0,uw
2ower of 250%..'-1'uw 2ower of 251%1-32++mw

T.ansient %&a.a%te.isti%s2 (#. $ela) %al%*lati#n3
%&e"ati%:
14
for op falling )10611#
spe!ifi!ations7
a%0 to 1-'v b%1-' to 0( ,tr%tf%1ps, time period)a#%4ns, time period)b#%2ns
Nand lay out +
September 30, 2014 [14MVD0089]
54 for op falling )01611#
Spe!ifi!ations7
a%1-' to 0( b%0 to 1-'( ,tr%tf%1ps, time period)a#%2ns, time period)b#%4ns
3-8or op rising )11600#
Spe!ifi!ations7
a%0 to 1-' ( b%0 to 1-'( ,tr%tf%1ps, time period)a#%4ns, time period)b#%4ns
Nand lay out ,
September 30, 2014 [14MVD0089]
4-8or op rising )11610#
spe!ifi!ations7
a% 1-' to 0 ( b%0 to 1-'( ,tr%tf%1ps, time period)a#%4ns, time period)b#%2ns
Dela) %al%*lati#n:
1-2ropagation rise delay )tpdr#%,-',4ps
2ropagation fall delay )tpdf#%+-3,'ps
Average propagation delay)tpd#%/)tpdr3tpdf#421%+-.,'ps
2-!ontamination rise delay )t!dr#%+-241ps
Nand lay out .
September 30, 2014 [14MVD0089]
!ontamination fall delay )t!df#%*-34*ps
average !ontamination delay )t!d#%/)t!dr3t!df#421%*-+.4ps
5]1#,e. anal)sis
O/se.0ati#n:
Total power7%'-4.'mw
Average power%3-.42uw
In(e.en%e:
delay and power !onsumption is in!reased for !onfigured
inverter as it !ontains 9:-
CONCLUION:
Thus implementation of layout and d! and transient analysis of !onfigured nand gate is
su!!essful-
Nand lay out 10