Eda Playground

EDA Playground Documentation
Release
Victor EDA
August 24, 2014
Contents
1 Table of Contents: 3
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Quick Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3 Settings & Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.4 Yosys Circuit Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.5 Tutorials and Code Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.6 FAQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
i
ii
EDA Playground Documentation, Release
EDA Playground on YouTube - Tutorials for Verilog, SystemVerilog, UVM, and VHDL, interview questions, news
and features, etc.
EDA Playground web application located at http://www.edaplayground.com/
EPWave documentation located at http://epwave.readthedocs.org
Contents 1
2 Contents
CHAPTER 1
Table of Contents:
1.1 Introduction
EDA Playground on YouTube - Tutorials for Verilog, SystemVerilog, UVM, and VHDL, interview questions, news
and features, etc.
1.1.1 Overview
EDA Playground gives engineers immediate hands-on exposure to simulating SystemVerilog, Verilog, VHDL,
C++/SystemC, and other HDLs. All you need is a web browser. The goal is to accelerate learning of design/testbench
development with easier code sharing, and with simpler access to EDA tools and libraries. EDA Playground is specif-
ically designed for small prototypes and examples.
With a simple click, run your code and see console output in real time. Pick another simulator version and run
it again.
View waves for your simulation using EPWave browser-based wave viewer.
Save your code snippets. Share your code and simulation results with a web link. Perfect for web forum
discussions or emails. Great for asking questions or sharing your knowledge.
Quickly try something out
Try out a SystemVerilog feature before using it on your project.
Try out a library that youre thinking of using.
Modify another engineers shared code and re-run it.
Eliminate environment differences. Since the code always executes in the same environment, everyone will see
the same result on a subsequent re-run.
Browse and use a large repository of working code examples and templates.
1.1.2 Example Usecases
Quick prototyping try out syntax or a library/language feature before using it in a large code base.
When asking questions on Stack Overow or other online forums, attach a link to the code and simulation
results.
Use during technical interviews to test candidates SystemVerilog/Verilog coding and debug skills.
3
Run anywhere. When away from your work machine, you can still try a quick prototype on EDA Playground.
Try verifying using different verication frameworks: UVM, SVUnit, plain Verilog, or Python.
Create an HDL and Verication Lab for young engineers, with the code hosted on EDA Playground. Students
can work from home at their own pace, and run the lab samples on EDA Playground.
Quickly check whether your code is synthesizable or emulator-friendly.
1.1.3 Tools & Simulators
For settings and options documentation, see Tools & Simulators Options
Available tools and simulators are below. EDA Playground can support many different tools. Contact us to add your
EDA tool to EDA Playground.
Simulators
Riviera-PRO
Commercial simulator that supports ALL SystemVerilog and VHDL features. Supports PSL.
riviera-pro
ModelSim
ModelSim supports most of SystemVerilog (including UVM/OVM and SVUnit libraries), and VHDL.
modelsim-uvm
SystemVerilog DPI (Direct Programming Interface) Tutorial
Icarus Verilog
Version 0.10.0 (devel) supports several SystemVerilog features.
GPL Cver
VeriWell
Compilers and Interpreters
C++
Perl
Python
Csh (C Shell)
Synthesis Tools
NOTE: The synthesis tools will only process code in the right Design pane. The code in the left Testbench pane will
be ignored.
Yosys
Yosys on GitHub
The Verilog-to-Routing (VTR) Project
4 Chapter 1. Table of Contents:
On private EDA Playground
EDA Playground may be deployed on a private company/university network. For such a private deployment, any
additional simulators/tools may be added. The company/university must have licenses for the commercial tools to be
added.
1.1.4 Libraries & Methodologies
For settings and options documentation, see Languages & Libraries Options
Available libraries and methodologies:
SystemVerilog and Verilog
UVM - Universal Verication Methodology
UVM 1.2 Class Reference
*
Whats New in UVM 1.2 on YouTube
UVM 1.1d Class Reference
OVM - Open Verication Methodology
OVM 2.1.2 Class Reference
OVM 2.1.2 User Guide
SVUnit - unit testing framework for Verilog/SystemVerilog modules, classes, etc.
SVUnit on SourceForge
OVL - Open Verication Library
OVL Library Reference Manual
OVL Quick Reference
ClueLib - A generic class library in SystemVerilog
ClueLib API Documentation
svlib - A Programmers Utility Library for SystemVerilog
svlib User Guide
VHDL
OVL - Open Verication Library
OVL Library Reference Manual
OVL Quick Reference
PSL - Property Specication Language
Natively supported by Riviera-PRO
OSVVM - Open Source VHDL Verication Methodology
1.1. Introduction 5
C++
SystemC - system level design and simulation in C++
SystemC 2.3.1 Class Reference
TLM 2.0 Class Reference
Python
MyHDL - a Python based hardware description language (HDL)
MyHDL Manual
MyHDL on Bitbucket
Migen - a Python toolbox for building complex digital hardware
Migen on GitHub
Migen from M-Labs
cocotb - a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
cocotb on GitHub
1.1.5 What Users are Saying
This is a really useful web-based utility for anyone who is discussing/sharing/debugging a code segment
with a colleague or a support person. Also, a very useful follow-up tool for post-training help among
students or between instructor and students. Simple, easy, useful.
Hemendra Talesara, Verication Technologist at Synapse Design Automation Inc.
I think EDA Playground is awesome! Great resource to learn without the hassle of setting up tools!
Alan Langman, Engineering Consultant
Ive used it a few times now to just check out some issues related to SV syntax and its been a big
timesaver!
Eric White, MTS Design Engineer at AMD
EDA Playground is sooo useful for interviews. I got a lot more feedback from being able to watch
someone compile and debug errors. I would highly recommend others to use it if they are asking SV
related questions.
Ricardo Goto, Verication Engineer
I have recommended to use EDAPlayground.com to my team and am also trying to use it more for my
debug. I nd EDAPlayground.com is much easier than logging into my Unix machines.
Subhash Bhogadi, Verication Consultant
I just wanted to thank you a lot for creating EDA Playground. Ive been using it a lot lately together with
StackOverow and it makes asking and answering questions much easier.
Tudor Timisescu, System Verication Engineer at Inneon Technologies
1.1.6 Support, Feature Requests and Bug Fixes
Support available on EDA Playground forum
Or open a bug here: https://github.com/getvictor/eda-playground/issues (requires GitHub account).
1.1.7 News and Site Updates
New features are frequently being added to EDA Playground. Follow the updates on your favorite social media site:
@EDAPlayground on Twitter
Victor EDA on LinkedIn
EDA Playground on Facebook
EDA Playground on Google+
1.1.8 Credits
EDA Playground was created in May 2013 by Victor Lyuboslavsky.
1.2 Quick Start
This Quick Start is intended for users of http://www.edaplayground.com.
1. In a separate web browser window, log in to EDA Playground at: http://www.edaplayground.com
2. In either the Design or Testbench window pane, type in the following code:
module test;
initial
$display("Hello World!");
endmodule
(Note: The code in the right Design pane is compiled rst, followed by code in the left Testbench pane.)
3. Click
Yes, running a sim is as simple as that!
4. In the bottom pane, you should see real-time results as your code is being compiled and then run. A run typically
takes 1-5 seconds, depending on network trafc and simulator. Near the bottom of result output, you should see:
Hello World!
5. Now, lets save our good work. Type in a descriptive name in the Details area on the left.
and click
6. The browser page will reload and the browser address bar will change. This is a persistent link to your saved
code. You can send the link by email, post it on a web page, post it on Stack Overow forums, etc. Here is what
the link looks like for one users Hello World! playground: http://www.edaplayground.com/s/3/12
7. Now, lets try modifying existing code. Load the following example: RAM
8. On the left editor pane, before the end of initial block, add the following:
1.2. Quick Start 7
write_enable = 1;
data_write = 8h2C;
toggle_clk_write;
toggle_clk_read;
$display("data[%0h]: %0h",
address_read, data_read);
The above code will write new data and read it out again. ( address_read and address_write should be the same).
9. Run the sim. In the results you should see this new message:
data[1b]: 2c
10. Optional. Click Copy to save a personal version of the modied RAM code, including the simulation results.
1.2.1 Loading Waves from EDA Playground
You can run a simulation on EDA Playground and load the resulting waves in EPWave.
Loading Waves for SystemVerilog and Verilog Simulations
Go to your code on EDA Playground. For example: RAM Design and Test
Make sure your code contains appropriate function calls to create a *.vcd le. For example:
initial begin
$dumpfile("dump.vcd");
$dumpvars(1);
end
Select a simulator and check the Open EPWave after run checkbox. (Not all simulators may have this run
option.)
Click Run. After the run completes, the resulting waves will load in a new EPWave window. (Pop-ups must be
enabled.)
Loading Waves for VHDL Simulations
Check the Open EPWave after run checkbox.
Specify the Top entity to simulate.
Click Run. After the run completes, the resulting waves will load in a new EPWave window. (Pop-ups must be
enabled.)
The waves for all signals in the specied Top entity and any of its components will be dumped.
In EPWave window, click Get Signals to select the signals to view.
1.2.2 Verilog Synthesis on EDA Playground
1.3 Settings & Buttons
1.3.1 Adding Files
EDA Playground supports up to 10 les. The les may be HDL source les, or text les to be used as inputs to the
testbench.
To add a le, click the + sign in the testbench or design pane. Then create a new le or upload an existing le. The
lename may not contain special characters.
Simulating code with multiple les
For SystemVerilog, use include statements such as the following to include the added source les in the compile:
include "adpcm_seq_item.svh"
For VHDL, all les with the .vhd and .vhdl extensions are automatically included in the compile.
For Python, use import statements:
from design import
*
To rename a le, double click the tab name. (The initial testbench and design les cannot be renamed.)
1.3.2 Sidebar Options
EDA Playground provides many options that can be congured for running your code.
Languages & Libraries
This section allows selection of coding languages and the available libraries for those languages.
1.3. Settings & Buttons 9
Testbench + Design
The testbench (left editor pane) and design (right editor pane) may be written using one of these languages:
Verilog/SystemVerilog for both
VHDL for both
Python for testbench, and Verilog/SystemVerilog for design
Python for both
UVM / OVM (SystemVerilog)
When language is Verilog/SystemVerilog, a UVM or OVM library can be used for both the design and testbench. The
following libraries are available:
UVM 1.2
UVM 1.1d
OVM 2.1.2
Other Libraries (SystemVerilog/Verilog)
When language is Verilog/SystemVerilog, other Verilog libraries can be used for both the design and testbench. These
libraries may be used along with UVM/OVM. Multiple libraries may be selected at the same time. Ctrl+Click to select
multiple libraries. Available libraries:
OVL 2.8.1
SVUnit 2.11
ClueLib 0.2.0
svlib 0.3
Libraries (VHDL)
When language is VHDL, the following VHDL libraries can be used for both design and testbench.
OVL 2.8.1
OSVVM 2014.01
Top entity (VHDL)
When language is VHDL, the top entity of the design must be specied before running a simulation.
Libraries (C++)
When language is C++/SystemC, the following libraries can be used for both design and testbench.
SystemC 2.3.1
SystemC 2.3.0
Methodology (Python + Verilog or Python only)
When testbench language is Python and design language is Verilog/SystemVerilog, the following verication environ-
ments are available:
cocotb 0.4
cocotb 0.3
cocotb 0.2
When testbench and design language is Python, the following methodologies are available:
MyHDL 0.8
Migen X
Migen Before running synthesis on a Migen design, the Top class corresponding to the top module must be specied.
The Top class is the class instantiation to use when converting the Migen design to Verilog. Some examples:
MyModule()
Divisor(4)
MyMemory(16, 2
**
12, init=list(range(20)))
Tools & Simulators
For running the code, several tools/simulators may be selected. Many simulators have additional options that may be
specied. Any options needed for languages and libraries will automatically be included.
Open EPWave after run
Checking this option will open EPWave wave viewer in a new window after the simulation run completes (pop-ups
must be enabled). It is available for all simulators that have a run step.
Download les after run
Checking this option will download the run directory as a ZIP le after the simulation run (pop-ups must be enabled).
The simulation run does not have to be successful for the download to occur. The ZIP le will include all the code
les as well as any generated les such as wave dumps, log les, etc.
YouTube video: How to download code and results from EDA Playground
Riviera-PRO EDU
Additional command-line compile options and run options may be specied in the bottom textboxes.
The Run Time option can be used to specify the number of timesteps for the simulation to run. By default, the
simulation runs forever until it hits a breakpoint or $nish.
The Use run.do Tcl le option is for using a custom run.do DO le for specifying simulation commands.
Riviera-PRO Compile Options for SystemVerilog/Verilog For SystemVerilog and Verilog simulations, Riviera-
PRO compile options are prepopulated with -timescale 1ns/1ns -sv2k9 and run options are prepopulated with +ac-
cess+r
Riviera-PRO Compile Options for VHDL For VHDL simulations, Riviera-PRO compile options are prepopulated
with -2008
ModelSim
The Run Time option can be used to specify the number of timesteps for the simulation to run. By default, the
simulation runs forever until it hits a breakpoint or $nish.
The Use run.do Tcl le option is for using a custom run.do DO le for specifying simulation commands. YouTube
video: Using ModelSim DO le
ModelSim Compile Options for SystemVerilog/Verilog For SystemVerilog and Verilog simulations, ModelSim
compile options are prepopulated with -timescale 1ns/1ns -mfcu +acc=rmb -sv -suppress 2181 and run options are
prepopulated with -suppress 3829
ModelSim Compile Options for VHDL For VHDL simulations, ModelSim compile options are prepopulated with
-2008
Icarus Verilog
Icarus Verilog 0.9.7 and Icarus Verilog 0.9.6 compile options are pre-populated with -Wall
Icarus Verilog 0.10.0 compile options are prepopulated with -Wall -g2012
An example of custom compile and run options is here: http://www.edaplayground.com/s/4/202
Note: When using Migen co-simulation, the compile/run options are not available.
GPL Cver
Currently, no additional options for this simulator are available.
VeriWell
Currently, no additional options for this simulator are available.
C++
This is a g++ Linux compiler for C++. It is used for C++ and SystemC runs.
Csh
This is a standard Csh (C Shell) interpreter. Currently, no additional options are available for Csh.
Perl
This is a standard Perl compiler. Currently, no additional options are available for Perl.
Python
This is a standard Python compiler. It is only used for MyHDL when both testbench and design are written in Python.
Currently, no additional options are available for Python.
Yosys
Yosis is a synthesis tool for performing logical synthesis and creating a netlist. It supports using ABC to synthesize
for a sample cell library.
Yosys will only process code in the right Design pane. The code in the left Testbench pane will be ignored.
UVM/OVM/Methodology/Libraries selections are also ignored.
The following synthesis options are available:
use ABC with cell library - synthesize for a demo cell library using ABC
memory -nomap - skip memory_map step
fsm -nomap - skip fsm_map step
skip FSM step
Show diagram after run - open the generated circuit diagram after synthesis ow completes (pop-ups must be
enabled).
When using Yosys with Migen, the Top class must be specied, which is used to convert Migen design to Verilog.
When using Yosys with MyHDL, the Testbench pane must contain code to convert MyHDL design to a Verilog le.
The Verilog le must have sufx .v, and can be named anything EXCEPT tb_* or a Verilog reserved keyword. Thus,
when running Yosys on MyHDL code, the Testbench code will be run rst before synthesis.
VTR
Verilog-to-Routing is a complete physical design ow that includes elaboration, logical sysnthesis, FPGA technology
mapping, packing, placement, and routing. The recommended architecture le k6_frac_N10_mem32K_40nm.xml is
used for the ow. In addition, route channel width is set at a high 100 to ensure no routing issues with dense designs.
VTR will only process code in the right Design pane. The code in the left Testbench pane will be ignored.
UVM/OVM/Methodology/Libraries selections are also ignored. Currently, no additional options are available for
VTR.
Currently, VTR cannot be used with MyHDL or Migen.
Details
The options in this section are only used when saving the playground.
Name
A brief name/title of the playground. Visible by others when they open a saved playground.
Description
A longer description of the playground. Visible by others when they open a saved playground.
Public
Whether this playground should be publicly accessible after being saved. When checked, anyone will be able to view
this playground. When unchecked, only the creator will be able to view the playground.
Examples
Links to code examples created on EDA Playground. Some examples may have additional documentation provided in
the (docs) link.
1.3.3 Editor Modes and Shortcuts
The editor supports the following modes:
Default
Vim
Emacs
The user may select the mode in the User Options on the user page:
Note that Vim and Emacs modes are only loose approximations of the actual bindings.
Default Mode
The default mode comes with search/replace functionality. The keybindings are:
Ctrl-F / Cmd-F - Start searching
Ctrl-G / Cmd-G - Find next
Shift-Ctrl-G / Shift-Cmd-G - Find previous
Shift-Ctrl-F / Cmd-Option-F - Replace
Shift-Ctrl-R / Shift-Cmd-Option-F - Replace all
The default mode uses the following shortcuts. Note that the shortcuts are different for PC and MAC users.
// For All
keyMap.basic = {
"Left": "goCharLeft", "Right": "goCharRight", "Up": "goLineUp", "Down": "goLineDown",
"End": "goLineEnd", "Home": "goLineStartSmart", "PageUp": "goPageUp", "PageDown": "goPageDown",
"Delete": "delCharAfter", "Backspace": "delCharBefore", "Tab": "defaultTab", "Shift-Tab": "indentAuto",
"Enter": "newlineAndIndent", "Insert": "toggleOverwrite"
};
// For PC
keyMap.pcDefault = {
"Ctrl-A": "selectAll", "Ctrl-D": "deleteLine", "Ctrl-Z": "undo", "Shift-Ctrl-Z": "redo", "Ctrl-Y": "redo",
"Ctrl-Home": "goDocStart", "Alt-Up": "goDocStart", "Ctrl-End": "goDocEnd", "Ctrl-Down": "goDocEnd",
"Ctrl-Left": "goGroupLeft", "Ctrl-Right": "goGroupRight", "Alt-Left": "goLineStart", "Alt-Right": "goLineEnd",
"Ctrl-Backspace": "delGroupBefore", "Ctrl-Delete": "delGroupAfter", "Ctrl-F": "find",
"Ctrl-G": "findNext", "Shift-Ctrl-G": "findPrev",
"Ctrl-[": "indentLess", "Ctrl-]": "indentMore",
fallthrough: "basic"
};
// For MAC
keyMap.macDefault = {
"Cmd-A": "selectAll", "Cmd-D": "deleteLine", "Cmd-Z": "undo", "Shift-Cmd-Z": "redo", "Cmd-Y": "redo",
"Cmd-Up": "goDocStart", "Cmd-End": "goDocEnd", "Cmd-Down": "goDocEnd", "Alt-Left": "goGroupLeft",
"Alt-Right": "goGroupRight", "Cmd-Left": "goLineStart", "Cmd-Right": "goLineEnd", "Alt-Backspace": "delGroupBefore",
"Ctrl-Alt-Backspace": "delGroupAfter", "Alt-Delete": "delGroupAfter", "Cmd-F": "find",
"Cmd-G": "findNext", "Shift-Cmd-G": "findPrev",
"Cmd-[": "indentLess", "Cmd-]": "indentMore",
fallthrough: ["basic", "emacsy"]
};
keyMap.emacsy = {
"Ctrl-F": "goCharRight", "Ctrl-B": "goCharLeft", "Ctrl-P": "goLineUp", "Ctrl-N": "goLineDown",
"Alt-F": "goWordRight", "Alt-B": "goWordLeft", "Ctrl-A": "goLineStart", "Ctrl-E": "goLineEnd",
"Ctrl-V": "goPageDown", "Shift-Ctrl-V": "goPageUp", "Ctrl-D": "delCharAfter", "Ctrl-H": "delCharBefore",
"Alt-D": "delWordAfter", "Alt-Backspace": "delWordBefore", "Ctrl-K": "killLine", "Ctrl-T": "transposeChars"
};
1.3.4 Buttons
Log In
The user must be logged in to save or run playground code. Playground code and results may be viewed without
logging in.
Run
Shortcut: Ctrl+Enter
Run the current code using the selected tool/simulator and options. The code runs on the EDA Playground server and
the results are printed in the bottom Results pane.
Save
Shortcut: Ctrl+S
Save the current playground, including code, bottom 200 lines of results, and options. Once the playground is saved,
the page reloads. The location specied in the address bar is a static link to this playground this link can be shared
with others.
If the playground has been saved previously, clicking on Save updates the currently saved playground. The static link
does not change.
If you modied a code example but did not save, youll see an asterisk in the Save button.
Copy
This button shows up for everyone when viewing a saved playground. Clicking on it creates a new copy of the current
playground. The copy will be complitely separate from the original, and it will have its own link that can be shared
with others.
If you modied a code example but did not save, youll see an asterisk in the Copy button.
Share
This button only shows up for saved playgrounds. It displays a modal pop-up with a static link to the current play-
ground. Also, it displays buttons for sharing on Twitter, Facebook, or LinkedIn.
Collaborate
Allows real-time collaborations where multiple users can edit code simultaneously.
Real-Time Collaboration Intro on YouTube.
About
Links to EDA Playground documentation (these pages).
Apps
Shows links to other apps available on EDA Playground, such as EPWave.
1.4 Yosys Circuit Diagrams
NOTE: Multiple top-level design modules are not supported by Yosys Cicruit Diagrams.
The Yosys synthesis ow can create circuit diagrams.
Square boxes are cells. Outputs on the right, inputs and unrecognized ports on the left. The rst line of text in
the box in the cell name, or _<number>_ for internal cells. The 2nd line is the cell type. Internal cell types start
with a dollar sign. (There is a chapter in the manual about the internal cell library used in yosys.)
Diamond-shaped nodes are wires that are not ports. Octagon-shaped nodes are ports.
Elliptical nodes are constant drivers. The label has the format <width><bits> or simply <number> for 32 bit
integers.
Boxes with round corners with lines such as 0:0 - 42:42 are used to break out and re-combine nets from busses.
So for example
wire [3:0] a, b;
wire [7:0] y = {a,b};
will create the following box:
The numbers tell you which bits on which side are connected. for example 3:0 - 7:4 means that the bits 3:0
from the left net are connected to bits 7:4 from the right net. Usually the box has a single connection on one
side and individual connections on the other side. When such boxes are connected to each other or to a cell port,
the connections have little diamonds on the ends instead of arrows. Thats because its not an actual connection
in the sense of the internal RTLIL netlist format.
For a detailed explanation, see Yosys Application Note 011: Interactive Design Investigation
1.4. Yosys Circuit Diagrams 19
1.5 Tutorials and Code Examples
1.5.1 Verilog Tutorials and Examples
D Flip-Flop (DFF)
Code located at: Verilog D Flip-Flop
This example demonstrates the design and verication of a simple D ip-op (Wikipedia link).
Design
The DFF module has the following pins:
Name Type Description
clk input the clock; rising edge of the clock captures the value
reset input asynchronous reset; when reset is high, the DFF output q is 0
d input the main input
q output the d value captured at the last rising clock edge
qb output inverted version of q
Testbench
The testbench is a simple directed test which toggles the DFF inputs and displays the outputs to the console.
The reg signals are used to drive inputs, and wire signals are used to observe outputs:
reg clk;
reg reset;
reg d;
wire q;
wire qb;
The DFF design is instantiated:
dff DFF(.clk(clk), .reset(reset),
.d(d), .q(q), .qb(qb));
The initial block contains the actual test. First, reset is driven to 1 to reset the op, while d is driven with an X:
clk = 0;
reset = 1;
d = 1bx;
From the console display, we see that the op has been properly reset with q == 0
Reset flop.
d:x, q:0, qb:1
Next, reset is released, while input d is driven to 1:
d = 1;
reset = 0;
The output q remains at 0 because the design did not see a rising edge of clk and did not capture the d input:
Release reset.
d:1, q:0, qb:1
Finally, we drive clk to 1 to create a rising edge:
clk = 1;
Now we see q output change to match the d input:
Toggle clk.
d:1, q:1, qb:0
Note: Before calling the $display task, we always tell simulation to proceed for 1 time unit #1 to allow the output
signals to propagate.
Ripple Carry Counter
Code located at: Verilog Ripple Carry Counter
$display System Task
Code located at: Verilog $display System Task
dene Text Macros
Code located at: Verilog dene Text Macros
Port Declaration & Connection
Code located at: Verilog Module Ports for Ripple Carry Counter
Ripple Carry Full Adder
Code located at: Verilog Ripple Carry Full Adder
Blocking and Nonblocking Assignments
Code located at: Verilog Blocking and Nonblocking Assignments
always @ event wait
Code located at: Verilog always @ event wait
if-else conditional and case statements
Code located at: Verilog if-else and case statements
1.5. Tutorials and Code Examples 21
Parameters
Code located at: Verilog Parameter
Generate Blocks
The StackOverowquestion mentioned in this Verilog tutorial: http://stackoverow.com/questions/18153405/parameterized-
number-of-cycle-delays-in-verilog
The generate example from the StackOverow question: Delay with Verilog generate
The generate conditional example from this Verilog tutorial: Verilog generate conditional
Verilog Tutorials on YouTube
1.5.2 SystemVerilog Tutorials and Examples
SystemVerilog Interview Questions on YouTube
1.5.3 UVM (Universal Verication Methodology) Tutorials and Examples
UVM Hello World Tutorial on YouTube
Whats New in UVM 1.2 on YouTube
1.5.4 SystemVerilog Unit Testing (SVUnit) Tutorials and Examples
Hands-on SVUnit Tutorial
Time to learn the basics of unit testing with SVUnit!
Edit the code and run it here: Hands-on SVUnit Tutorial on EDA Playground
Heres a simple set of unit tests for an interface called svunitOnSwitch. The purpose of the design is to offer a
few utility functions as well as to operate an on/off output.
The API of the svunitOnSwitch is as follows:
output logic on;
function logic true();
function logic false();
function int return43();
turn_on();
turn_off();
The svunitOnSwitch is dened as:
interface svunitOnSwitch (
output logic on
);
initial on = hx;
function logic true();
// no implementation yet
endfunction
function logic false();
endfunction
function int return43();
endfunction
function void turn_on();
endfunction
function void turn_off();
endfunction
endinterface
The SVTESTs below are the acceptance unit tests that verify the functionality of the svunitOnSwitch. If you
run the tests on EDA Playground youll see all the tests fail because none of the svunitOnSwitch functionality is
implemented. Your job is to build a complete svunitOnSwitch, one requirement at a time, by:
examining the requirement dened in the unit test
(HINT: a unit test is marked by the SVTEST macro)
implementng the corresponding code in the svunitOnSwitch
(HINT: watch for the no implementation yet comment)
running the test suite to make sure your implementation satises the unit test
When youve gone through all the tests and your entire test suite passes, youre done! Youve veried the
svunitOnSwitch and learned the basics of SVUnit!
Ready... set... go!
Edit the code and run it here: Hands-on SVUnit Tutorial on EDA Playground
include "svunit_defines.svh"
import svunit_pkg::
*
;
module svunitDemo_unit_test;
SVUNIT_TESTS_BEGIN
//------------------------------
// test: true_test
// the true() function should
// return 1
//------------------------------
SVTEST(true_returns_1)
FAIL_UNLESS(uut.true() === 1);
SVTEST_END
//------------------------------
// test: false_test
// the false() function should
// return 0
//------------------------------
SVTEST(false_returns_0)
FAIL_UNLESS(uut.false() === 0);
SVTEST_END
//-----------------------------------
// test: return43
// The function return43() returns
// a value. this test should fail
// if that doesnt happen.
//-----------------------------------
SVTEST(return43)
FAIL_UNLESS(uut.return43() === 43);
SVTEST_END
//---------------------------------
// test: turn_on
// our uut has an output pin
// called on that we can
// assert via turn_on()
//---------------------------------
SVTEST(turn_on)
uut.turn_on();
FAIL_UNLESS(uut.on === 1);
SVTEST_END
//---------------------------------
// test: turn_off
// we can turn on off using
// turn_off() method
//---------------------------------
SVTEST(turn_off)
uut.turn_off();
FAIL_UNLESS(uut.on === 0);
SVTEST_END
/
*
----------------------------------------
----------------------------------------
For more SVUnit, Remember to visit:
www.AgileSoC.com/svunit
And try the other SVUnit examples at:
www.edaplayground.com
----------------------------------------
----------------------------------------
*
/
SVUNIT_TESTS_END
string name = "svunitDemo_ut";
svunit_testcase svunit_ut;
//===================================
// This is the UUT that were
// running the Unit Tests on
//===================================
svunitOnSwitch uut();
//===================================
// Build. Runs once
//===================================
function void build();
svunit_ut = new(name);
endfunction
//===================================
// Setup for running the Unit Tests
// Runs before every SVTEST.
//===================================
task setup();
svunit_ut.setup();
/
*
Place Setup Code Here
*
/
endtask
//===================================
// Here we deconstruct anything we
// need after running the Unit Tests
// Runs after every SVTEST.
//===================================
task teardown();
svunit_ut.teardown();
/
*
Place Teardown Code Here
*
/
endtask
endmodule
You can do a lot more than test a simple svunitOnSwith with SVUnit. When youre ready to test your own design
and testbench IP visit: http://www.AgileSoC.com/svunit
SVUnit Examples on YouTube
1.5.5 VHDL Tutorials and Examples
VHDL Basic Tutorials on YouTube
1.5.6 cocotb Tutorials and Examples
Endian Swapper Design and Testbench Tutorial
1.6 FAQ
1.6.1 How do I start a blank playground design?
When working on code at http://www.edaplayground.com, you can start a blank design by clicking the EDA Play-
ground logo in the top left. (Before doing that, please ensure that your existing code edits are saved.)
1.6.2 How do I modify one of the examples? How do I modify someone elses play-
ground?
After making code edits, you can save your own version by clicking Copy.
1.6.3 What is EPWave?
EPWave (EDA Playground Wave) is the rst web browser-based wave viewer. It is part of EDA Playground.
1.6.4 Can I view the waves from my EDA Playground sim using EPWaves?
Yes, waves are supported for all languages, frameworks, and libraries. See Loading Waves from EDA Playground
1.6.5 How do I get updates about new EDA Playground features?
New features are frequently being added to EDA Playground. Follow the updates on your favorite social media site:
@EDAPlayground on Twitter
Victor EDA on LinkedIn
EDA Playground on Facebook
EDA Playground on Google+
1.6.6 What are the resource limits for running my code?
Each run is limited to 60 seconds runtime and 100MB of memory.
These limits can be increased for those who would like to be power users use EDA Playground on a regular basis
and provide feedback. Contact Victor EDA to request.
1.6.7 Which web browsers are supported?
Firefox
Chrome
Internet Explorer 9 or higher
1.6.8 How do I log in if I dont have a Google or Facebook account?
We are working on providing additional ways to sign into EDA Playground. Meanwhile, please create a new Google
account at https://accounts.google.com/SignUp and use that to sign in.
Note: If youre using EDA Playground on a private network, log in with the authentication credentials for your
network.
1.6.9 Why cant I run a sim with SystemVerilog assertions, coverage, or random-
ize() methods?
Currently, most of SystemVerilog language is supported on EDA Playground, which is sufcient for examples and
tutorials.
We are working with simulator vendors to offer limited public access to commercial SystemVerilog features.
Also see modelsim-uvm
1.6.10 Is VHDL supported?
Yes, VHDL is supported. VHDL example: http://www.edaplayground.com/s/example/615
1.6.11 How do I get a private deployment of EDA Playground at my com-
pany/university?
Please contact Victor EDA
Private deployments are available FREE for academic and non-commercial research purposes.
1.6.12 I have more questions. How do I get support?
EDA Playground is actively being improved. If you need help or have suggestions, support is available on EDA
Playground forum
If you see a bug, however minor, please post on the forum or le a new issue at https://github.com/getvictor/eda-
playground/issues (requires GitHub account)
For simulator support, please contact the appropriate simulator vendor.
1.6. FAQ 27

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