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Code No: R05420402 R05 Set No. 2
IV B.Tech II Semester Examinations,AUGUST 2011
DIGITAL DESIGN THROUGH VERILOG
Common to Bio-Medical Engineering, Electronics And Computer
Engineering, Electronics And Communication Engineering
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks

1. Write HDL Module of CPU cycles process. [16]
2. (a) Write about a byte comparator?
(b) Write a verilog module of an 8 bit comparator and its test bench? [8+8]
3. (a) Design Up counter coding procedural assignment.
(b) Write Up counter test bench, simulation results. [8+8]
4. (a) Explain control network using a counter for the state register in Dice.
(b) SM chart with serial state assignment and added X-state. [8+8]
5. (a) Explain asymmetric sequence generator with example.
(b) Explain automatic (re-entrant) tasks with example. [8+8]
6. (a) Explain about Microcontrollers.
(b) Explain about dice roll controllers. [8+8]
7. (a) Explain module with an example using verilog code?
(b) Explain port Declaration with an example using verilog code? [8+8]
8. (a) Explain about operator priority with examples.
(b) Explain bit widths of expressions. [8+8]

1
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Code No: R05420402 R05 Set No. 4
IV B.Tech II Semester Examinations,AUGUST 2011
DIGITAL DESIGN THROUGH VERILOG
Common to Bio-Medical Engineering, Electronics And Computer
Engineering, Electronics And Communication Engineering
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks

1. (a) Explain about Microcontrollers.
(b) Explain about dice roll controllers. [8+8]
2. (a) Explain about operator priority with examples.
(b) Explain bit widths of expressions. [8+8]
3. (a) Write about a byte comparator?
(b) Write a verilog module of an 8 bit comparator and its test bench? [8+8]
4. Write HDL Module of CPU cycles process. [16]
5. (a) Design Up counter coding procedural assignment.
(b) Write Up counter test bench, simulation results. [8+8]
6. (a) Explain asymmetric sequence generator with example.
(b) Explain automatic (re-entrant) tasks with example. [8+8]
7. (a) Explain control network using a counter for the state register in Dice.
(b) SM chart with serial state assignment and added X-state. [8+8]
8. (a) Explain module with an example using verilog code?
(b) Explain port Declaration with an example using verilog code? [8+8]

2
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Code No: R05420402 R05 Set No. 1
IV B.Tech II Semester Examinations,AUGUST 2011
DIGITAL DESIGN THROUGH VERILOG
Common to Bio-Medical Engineering, Electronics And Computer
Engineering, Electronics And Communication Engineering
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks

1. (a) Explain asymmetric sequence generator with example.
(b) Explain automatic (re-entrant) tasks with example. [8+8]
2. (a) Explain control network using a counter for the state register in Dice.
(b) SM chart with serial state assignment and added X-state. [8+8]
3. (a) Write about a byte comparator?
(b) Write a verilog module of an 8 bit comparator and its test bench? [8+8]
4. (a) Explain about operator priority with examples.
(b) Explain bit widths of expressions. [8+8]
5. (a) Explain about Microcontrollers.
(b) Explain about dice roll controllers. [8+8]
6. (a) Design Up counter coding procedural assignment.
(b) Write Up counter test bench, simulation results. [8+8]
7. Write HDL Module of CPU cycles process. [16]
8. (a) Explain module with an example using verilog code?
(b) Explain port Declaration with an example using verilog code? [8+8]

3
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www.jntuworld.com
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Code No: R05420402 R05 Set No. 3
IV B.Tech II Semester Examinations,AUGUST 2011
DIGITAL DESIGN THROUGH VERILOG
Common to Bio-Medical Engineering, Electronics And Computer
Engineering, Electronics And Communication Engineering
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks

1. Write HDL Module of CPU cycles process. [16]
2. (a) Design Up counter coding procedural assignment.
(b) Write Up counter test bench, simulation results. [8+8]
3. (a) Explain asymmetric sequence generator with example.
(b) Explain automatic (re-entrant) tasks with example. [8+8]
4. (a) Write about a byte comparator?
(b) Write a verilog module of an 8 bit comparator and its test bench? [8+8]
5. (a) Explain control network using a counter for the state register in Dice.
(b) SM chart with serial state assignment and added X-state. [8+8]
6. (a) Explain module with an example using verilog code?
(b) Explain port Declaration with an example using verilog code? [8+8]
7. (a) Explain about Microcontrollers.
(b) Explain about dice roll controllers. [8+8]
8. (a) Explain about operator priority with examples.
(b) Explain bit widths of expressions. [8+8]

4
www.jntuworld.com
www.jntuworld.com