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Objectives:
The purpose of this lab is to solidify our understanding of sequential circuits and behavioral
Verilog by introducing the binary counter. This will be built via the usage of previously
configured circuits and calling their functions. This will demonstrate the usage of binary counters
on the Xilinx board and use them to perform clock frequency division and I/O debouncing.
Clock frequency division is the process by which we can generate a slower clock from a faster
clock and thereby allow for two circuits running at different speeds to be run by the same clock.
Signal debouncing refers to being able to have a circuit that runs in non-ideal conditions. Mainly
these non-ideal conditions refer to electrical chatter caused when buttons are pushed producing
electric pulses or a bouncing signal so debouncing refers to alleviating the circuit outputs of
this problem.
Design:
Below are the source codes for all of the circuits we simulated as well as the .ucf code we had to
write ourselves.
//clock divider
`timescale 1ns / 1ps
`default_nettype none
module clock_divider(ClkOut, ClkIn);
//this program takes the clock signal and divides it
output wire [3:0] ClkOut;
//divided signal
input wire ClkIn;
//initial clock
parameter n = 5;
reg [n-1:0] Count;
//Counter
always@(posedge ClkIn)
Count <= Count + 1;
//up counter
`timescale 1ns / 1ps
`default_nettype none
module up_counter(Count, Carry3, En, Clk, Rst);
output reg [3:0] Count;
output wire Carry3;
input wire En, Clk, Rst;
wire [3:0] Carry, Sum;
//output counter
//final carry output
//Enable, Clock, Reset
//Four carry and sum within the circuit
//Do this when the clock or reset goes from low to high
//If it is the reset then set count to zero
endmodule
//top level
`timescale 1 ns/ 1 ps
`default_nettype none
module top_level (LEDs, SWs, North, South, FastClk);
output wire [4:0] LEDs;
//the LEDs show the outputs
input wire [1:0] SWs;
//Switches
input wire North, South, FastClk;
//North button, south button, faster clock (original clock)
reg SlowClk;
//slow clock (derived from fast clock)
wire [3:0] Clocks;
//each clock
always@(*)
case(SWs)
2'b00: SlowClk =Clocks[0];
2'b01: SlowClk =Clocks[1];
2'b10: SlowClk =Clocks[2];
2'b11: SlowClk =Clocks[3];
endcase
#Push buttons
NET "North" LOC = "V4" |IOSTANDARD = LVTTL | PULLDOWN; //assigns the north and south commands to buttons
NET "South" LOC = "K17" |IOSTANDARD = LVTTL | PULLDOWN;
#LEDs
NET "LEDs[0]" LOC = "F12" | IOSTANDARD = LVTTL;
NET "LEDs[1]" LOC = "E12" | IOSTANDARD = LVTTL;
NET "LEDs[2]" LOC = "E11" | IOSTANDARD = LVTTL;
NET "LEDs[3]" LOC = "F11" | IOSTANDARD = LVTTL;
NET "LEDs[4]" LOC = "C11" | IOSTANDARD = LVTTL;
NET "FastClk" LOC ="C9" | IOSTANDARD = LVTTL;
//assigns clock in
//switch bounce
`timescale 1ns / 1ps
//Written to demonstrate bounce in a switch
module switch_bounce(
input wire Center,
output wire J1_0
);
assign J1_0 = Center;
endmodule
//switch bounce ucf
#UCF for observing switch bounce
NET "J1_0" LOC = "B4" | IOSTANDARD = LVTTL | SLEW = FAST; #J1_0
NET "Center" LOC = "V16" | IOSTANDARD = LVTTL | PULLDOWN | SLEW = FAST; #ROT_CENTER
//nodebounce
`timescale 1ns / 1ps
`default_nettype none
/*This module describes a counter that is triggered off of*
*the rising-edge of an signal that has not been debounced*
*in order to demonstrate the effects of switch bounce */
#Clock constraints
NET "Clk" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
# Define clock period for 50 MHz oscillator
NET "Clk" PERIOD = 20.0ns HIGH 40%;
//withDebounce
`timescale 1ns / 1ps
`default_nettype none
module withDebounce(LEDs, Center, Clk);
output reg [7:0] LEDs;
input wire Center, Clk;
/*-this is a keyword we have not seen yet!*
*-as the name implies, it is a parameter *
* that can be changed at compile time... */
parameter n = 18;
wire notMsb, Rst, En, Debounced;
reg Synchronizer0, Synchronized;
reg [n-1:0] Count;
reg edge_detect0;
wire rising_edge;
/********************************************/
/* Debounce circuitry!!!
*/
/********************************************/
always@(posedge Clk)
begin
Synchronizer0 <= Center;
Synchronized <= Synchronizer0;
end
always@(posedge Clk)
if(Rst)
Count <= 0;
else if(En)
Count <= Count + 1;
assign notMsb = ~Count[n-1];
assign En = notMsb & Synchronized;
assign Rst = ~Synchronized;
assign Debounced = Count[n-1];
/********************************************/
/* End of Debounce circuitry!!!
*/
/********************************************/
always@(posedge Clk)
edge_detect0 <= Debounced;
assign rising_edge = ~edge_detect0 & Debounced;
always@(posedge Clk)
if(rising_edge)
#Clock constraints
NET "Clk" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
# Define clock period for 50 MHz oscillator
NET "Clk" PERIOD = 20.0ns HIGH 40%;
Results:
Below are the waveforms of the various experiments throughout the lab and they are labeled
accordingly.
Figure 1: Waveforms of Experiment 1
Conclusion:
The code ran according to plan and I learned a bit more about the inner workings of the circuit
and this was the first time we experienced the real world time delay and bounce in the circuit.
When studying circuits it seems like a few nanoseconds of delay here and there wouldnt matter,
but it really starts to accumulate in a circuit. This means that I need to be more careful in
calculating these delays when I am designing circuits to make sure that all of the information
gets to the right place at the right time. This was also the first lab that we used the oscilloscope
with Verilog and it was really neat to see how the clocks make wave patterns and being able to
physically visualize the delays and the clock dividers.
Questions:
1.
2.
3.
4.
b.
c.
d.
e.
f.
g.
Student Feedback:
1. I liked that we used the oscilloscope. I didnt like the partner work. I feel like I
understand much better when I am coding and doing the measurements myself, but it
would have been far too much work to finish on my own in one class period.
2. Nothing about the lab manual was unclear.
3. Minimizing partner work (if possible) would be nice. Not that I dont like Thomas, but I
would have learned more if I was doing it myself. Teamwork is great, but in coding I
think hands on is much better.