A Systematic Frequency Planning Method in

Direct Digital Synthesizer (DDS) Design

Chao Huang

Li-xiang Ren

Beijing Institute of Technology

Beijing, China 100081

Beijing Institute of Technology

Beijing, China 100081
Email: Lixiangr@bit.edu.cn

AbstractDirect Digital Synthesizer (DDS) based frequency synthesizer is important to the performance of
radar. Effective DDS frequency planning is a problem
still untouched in DDS design. Traditional software based
method in DDS design can only get one frequency point
spur performance at each run. A new DDS frequency
planning method is proposed in the paper, this method
can indicate DDSs output clean frequency band with a
graphic method. This simple and useful method can tell
the designer the usable DDSs output frequency band in
the early stage of the overall frequency synthesizer design.
As a result, it is of great significance in realizing a high
performance synthesizer. Finally, a real S band frequency
synthesizer was developed for a stepped frequency radar,
the frequency synthesizer works well and its test results
prove the effectiveness of the frequency planning method.
Index TermsDDS, Frequency planning, frequency synthesizer.

Er-ke Mao
and Pei-kun He
Beijing Institute of Technology

This paper presents a graphic DDS frequency planning

method which gives a final solution to the spur issue. The
graphic method provides the designer an overall picture
of the DDSs output performance, as a result, the spur
performance of the DDS is cleanly shown and spur issue
can be solved in design stage.
In this paper, first, traditional DDS frequency planning
method is introduced in section II. The DAC harmonics
analysis is given in section III. In section IV, the graphic
frequency planning method is proposed in details. The
experimental results based on a real S band frequency
synthesizer are presented in section V and a conclusion
is given in section VI.
II. TRADITIONAL DDS FREQUENCY PLANNING
METHOD

I. I NTRODUCTION
Direct Digital Synthesizer (DDS) has already become
the first choice of most frequency synthesizer designers.
Actually, this is due to DDSs advantages such as fast
frequency hopping speed, high frequency resolution,
output phase continuity and so on. However, if DDS is
chosen as the frequency synthesizer core, every designer
has to face a spur issue. It is the spurs of DDS that prevents it from replacing traditional frequency synthesizer
completely.
Generally speaking, frequency planning is the only
way that works in eliminating the spurs of DDS in
real circumstances. Unfortunately, there isnt an effective
frequency planning method at present. Traditional software based method can only get one frequency point
performance at each run. Certainly, this is far from
enough. A bad DDS design without proper frequency
planning may lead to a DDS main output accompanied
by lots of nearby spurs. This nearby spurs can become
disaster after frequency multiplying. For example, if
we multiply the output of DDS by N , the power of
the nearby spurs will increase by a factor of 20 lg(N ).
Consequently, Only when a full view of DDS output
spurs is obtained can we make a clean DDS output.

A DDS chip is usually made of a DDS core plus a

DAC. In applications, a spur filter is usually connected
behind to suppress DAC spurs(as depicted in Figure 1).
This is a quite classic structure. DDS core is used to
generate digital output amplitude. The DAC bridges the
digital amplitude to analog waveform. The spur filter
is used to attenuate unwanted spurs of DAC output. As
the analog spur filters attenuation ability (including Pass
Bandwidth, Stop Bandwidth, order and etc.) is limited,
it is necessary to do DDS frequency planning in design
stage.
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Fig. 1.

DDS chip structure.

At present, DDS frequency planning is often done

with the aid of some simulation softwares. For example,
the ADI company has provided with a simulation tool

978-1-4244-5668-0/09/$25.00 2009 IEEE

named ADIsimDDS on its website. Software simulation method is fast. Furthermore; both the DAC harmonics and phase truncation spurs are indicated. However,
after all, software simulation method is a try method.
The designer can only get a frequency point performance
at each run; the overall output band performance is still
unknown even though lots of frequency points have been
tried.
For example, Figure 2 shows a software simulation
output. This is a DDS driven by a clock of 1GHz, and
the DDS output is 336M Hz. The software shows that
there are two spurs exist in the circumstance, one is a
nearby spur and another is a far away spur. Because there
is an obvious nearby spur near 336M Hz, this output
is considered as a bad output. However, what if DDS
outputs a frequency of 337M Hz, 340M Hz, ...? what
if that there is a mandatory requirement that the spurs
should be 50M Hz away from main output? Too many
problems cant be resolved with the try method.

IV. A NOVEL GRAPHIC FREQUENCY

PLANNING METHOD
In this part, a graphic frequency planning method is
derived step by step. Furthermore, a sum-up is made
to guide the whole DDS based frequency synthesizer
design. Based on the analysis in section III, m in
Equation 1 is confined to be less than or equal to 3.
Furthermore, because of the DAC at the output of the
DDS chip, there is a Nyquist constraint on fi and fo .
Therefore the following constraints should apply:

0 < fi < fs /2
0 < fo < fs /2
(2)

m = 1, 2, 3
Where m is the order of HDs. When fo is considered
only within the range of [0, fs /2], the possible numbers
that n could be taken are greatly reduced. Based on
Equation 1 and Equation 2, the following results on
HD1(m = 1), HD2(m = 2) and HD3(m = 3) are
deduced:
fo1 = fi for 0 < fi < fs /2

fo2 =

Fig. 2.

DDS software simulation output.

fo3 =
III. ANALYSIS OF DAC HARMONICS
The DAC outputs different orders of harmonic distortions(HDs), including HD1(the wanted main output)
and higher order HDs. This is due to DAC cores integral
non-linearity characteristics [9]. The HD1 is main output
harmonic distortion. The HDn (n 2) are spurs that
need to be filtered out.
The higher order DAC HDs are troublesome, because
they contaminate DAC output. Fortunately, their positions are predicable. Equation 1 shows their theoretical
position: [5].
fo = mfi + nfs

(3)

2fi for 0 < fi < fs /4

fs 2fi for fs /4 < fi < fs /2

(4)

3fi for 0 < fi < fs /6

fs 3fi for fs /6 < fi < fs /3

3fi 2fs for fs /3 < fi < fs /2

(5)

From Equation 3, 4, 5, the behavior of HD1, HD2 and

HD3 can be drawn in Figure 3:
fo

(1)

Where fs is the frequency of DDS chip driven clock,

fi is intended output and fo is actual output. It becomes
easy to understand when it is taken as a mixing process
of frequency fs and fi . Equation 1 gives the positions of
HDs, while the amplitude information can be estimated
when compared to mixing process, that is, the higher
order, the lower amplitude. In practical applications, we
only consider the influence of HD2 and HD3, higher
orders are too weak and are often neglected.

fi

Fig. 3.

HD1, HD2 and HD3 behavior.

The next step is to set a threshold that determines

the clean area and dirty area. Usually, the threshold
is decided by the performance of spur filter (the pass
bandwidth, the stop bandwidth, the attenuation and etc).

Suppose a spur filter with a stop bandwidth of 100M Hz,

it is reasonable that we want any spurs be at least
50M Hz away from main output, as depicted in Figure 4,
if we want any spurs be afs away from HD1, the spurs
should be out of the shaded area, and the corresponding
threshold formulas are as follows:
T hreshold1 = afs + fi
T hreshold2 = afs + fi

(6)


(1)
(2)
(3)
(4)
(5)

Threshold 1

fo

af s  f i

Threshold 2 af s  fi

Sectors
Sector 1
Sector 2
Sector 3

Clean and Dirty area.

Comparing Figure 3 and Figure 4, we can draw

Figure 5 in which spurs and thresholds are showed
simultaneously.

fo

fi

Fig. 4.

The six x-coordinates x1,x2,x3,x4,x5,x6 define the

boundaries of three clean intervals as:
Sector 1: [x1, x2]
Sector 2: [x3, x4]
Sector 3: [x5, x6]
The three intervals are clean sectors with all the
spurs at least afs away from them. The final results are
summed up as follows:

DIV

IV

(6)

IV

DIV

fo = fi + afs
fi = x1 = afs
fo = 2fi
fo = fi + afs
fi = x2 = 1a
4 fs
fo = 3fi + fs
fo = fi afs
fi = x3 = 1+a
4 fs
fo = 3fi + fs
fo = fi + afs
fi = x4 = 1a
3 fs
fo = 2fi + fs
fo = fi afs
fi = x5 = 1+a
3 fs
fo = 2fi + fs
fo = fi afs
fi = x6 = 1a
2 fs
fo = 3fi fs

Threshold1

Threshold 2

boundary
[afs , 1a
4 fs ]
[ 1+a
f
, 1a
s
4
3 fs ]
1+a
[ 3 fs , 1a
2 fs ]

Bandwidth
15a
2 fs
17a
12 fs
15a
6 fs

Center frequency
1+3a
8 fs
7a
24 fs
5a
12 fs

Furthermore, as the width of sectors must be positive,

there are three conclusions:
(1): when 0 < a < 17 , all of three sectors are available.
(2): when 17 < a < 15 , Sector 1 and Sector 3 are
available.
(3): when 15 < a, no sector is available.
The above three conclusions indicate that we should
be cautious in filter design. Loose limit on filter design
incurs a penalty of a large a, which leads to fewer clean
sectors and may increase design difficulty.
V. E XPERIMENTAL RESULTS

fi

Fig. 5.

HD1, HD2 and HD3 with threshold indicated.

The six intersections of the spur curves and the

shaded area in Figure 5 determine the final boundaries of
clean and dirty areas. The x-coordinates of the six
intersections can be obtained by solving the following
six equations.

A real S band frequency synthesizer was developed

for a stepped frequency radar. As depicted in Figure 6,
The frequency synthesizer is composed of a DDS and a
PLL. Furthermore; the driving clock of DDS is 1GHz.
The frequency synthesizer is required to output a frequency of 2728M Hz and according to spur filter parameters(in the DDS+PLL structure, spur filter parameters
actually are determined by loop filter in PLL), there is
a requirement that any spurs should be 100M Hz away
from 2728M Hz.
In design stage, two schemes have been considered.
Scheme 1 is to let DDS output 341M Hz and the PLL
is set as X8 mode, thus a final output of 341 8 =
2728M Hz is obtained. Scheme 2 is a 170.5M Hz output

Scheme1spectrum

Fig. 6.

Photograph of a S band frequency synthesizer.

DDS plus a X16 PLL, the same output of 170.5 16 =

2728M Hz can also be obtained.
The frequency planning method presented above was
used to tell which scheme is better. As discussed above,
fs = 1GHz, as any spurs should be 100M Hz away,
a can be calculated as a = 100/1000 = 0.1, which
satisfies 0 < a < 1/7. Using the conclusions given
in section IV, we can quickly get three clean output
sectors:
Sector 1: [100, 225]M Hz
Sector 2: [275, 300]M Hz
Sector 3: [367, 450]M Hz
It is obvious that in Scheme 1, DDS output 341M Hz
is out of the clean sector; while in Scheme 2, DDS
output 170.5M Hz is within the clean Sector 1, consequentially, Scheme 2 is a better choice.
The test conditions and comparisons are listed in the
following table:
Compared contents
DDS output sectors
DDS output
PLL configuration
DDS+PLL output
Spectrum results

Scheme 1
dirty
341M Hz
X8
2728M Hz
top of Fig 7

Scheme 2
clean
170.5M Hz
X16
2728M Hz
bottom of Fig 7

The spectrum output of the S band frequency synthesizer shows the experimental results of the two schemes
in Figure 7. Obviously, after frequency planning, Scheme
2 gives a better result that most of the spurs have
been suppressed which greatly improve the synthesizers
Spurious Free Dynamic Range.
VI. C ONCLUSION
In the paper, a DDS frequency planning method is presented. This graphic method can give an overall performance depiction of the available DDS output frequency
band in the design stage, thus, the influence of spurs is
greatly eliminated. Furthermore, a real S band frequency
synthesizer was developed for a stepped frequency radar,
the frequency synthesizer works well and its test results

Scheme2spectrum

Fig. 7.

Scheme 1 vs Scheme 2 at 2728M Hz output.

prove the effectiveness of the frequency planning method

in the paper.
ACKNOWLEDGMENT
The author is grateful for Li-xiang Ren, Er-ke Mao,
Pei-kun He and Lei Li, for consulting them on writing
this paper, for their good ideas and valuable comments
as well as useful references.
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[5] Analog Devices. 1 gsps direct digital synthesizer. page 19, 2003.
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