Intro to FinFET:

Challenges for 14nm and Beyond

Mothi Rohini Ande

Independent

ABSTRACT

Due to limitation of CMOS planar process industry has moved to a new process FinFET. In this
paper we will be highlighting on advantages and limitations of FinFET to CMOS planar with
respect to process, design and characteristics. Although we have seen some success story with
FinFET, but what about technology nodes beyond 14nm.We have discussed on the challenges we
will be facing when we move to 10nm and 5nm focusing whether FinFET will be good for all the
future technology nodes or we will be switching to a new process.

Table of Contents
1. Introduction ....................................................................................................................... 3
2. FinFET .............................................................................................................................. 3
3. FinFET Challenges and Limitations .................................................................................... 6
4. Beyond 14nm .................................................................................................................... 8
5. Conclusions ......................................................................................................................11
6. References........................................................................................................................11

Table of Figures
Figure 1 - Planar CMOS and FinFET ....................................................................................... 3
Figure 2 - FinFET.................................................................................................................... 4
Figure 3 - SOI and Bulk FinFET .............................................................................................. 5
Figure 4 - Carbon Nanotube Structure .....................................................................................10
Figure 5 - 5nm FET with carbon nanotube between S/D ..........................................................10
Figure 6 - Parasitic Capacitances in FinFET ............................................................................10

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Intro to FinFET: Challenges for 14nm and Beyond

1. Introduction
As technology is shrinking the short channel effects such as Drain Induced Barrier Lowering
(DIBL) is playing a major role in the performance of a transistor by reducing gate control over
the channel and causing a huge leakage. In DIBL effect it is hard to turn off the transistor as it is
harder for the voltage on a gate electrode to deplete the channel underneath and stop the flow of
carriers through the channel. This increased leakage is because as we are moving to lower
technology nodes we are having decreased oxide thickness, higher substrate doping, decreased
channel length and targeting for a better performance at lower threshold voltage. The continued
shrinking of source and drain reduces the control of gate over the channel causing DIBL. To
reduce this leakage in planar process we used strained silicon challis, ultra thin single gate fets,
metallic gates, double gate (DG) and multi gate devices.
Another approach to reduce DIBL is by raising the channel above the surface of the wafer
instead of creating the channel just below the surface, the gate is wrapped around its three sides,
providing much greater electrostatic control over the carriers within. This is where a finFET
comes in.

2. FinFET
FinFET is the Field Effect Transistor in which the transistor gate is wrapped around the channel
or the fin, there is more control on channel current as compared to the planar CMOS. A planar
CMOS and FinFET is shown in Figure 1. A finFET consists of a narrow vertical fin that sticks
up from the wafer surface, Source and Drain are built at opposite ends of the fin. The fin is used
to form the raised channel. The channel is then deposited such that it wraps around the fin to
form the trigate structure. As the channel is extremely thin the gate has much greater control over
the carriers within it. The current flow in the channel is parallel to the plane of the wafer. The fin
height is uniform for all the fins on chip.

Figure 1 Planar CMOS and FinFET

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Intro to FinFET: Challenges for 14nm and Beyond

The cross section of a finFET is shown in Figure 2. The main parameters are height (h_fin) and
width (t_fin) of fin, which are defined by the fabrication process. A tri-gate is described as the
gate covering both sides and top of the fin, it has a thin dielectric on three sides and a thick
dielectric at the top that allows the gate electrostatic control on fin silicon to just the sidewalls.
The conducting channel are formed on two vertical sidewalls of fin which are in 110 orientation,
this channel crystal orientation is different from planar CMOS which is 100. But as the channel
is extremely thin so when the device is switched on the shape limits the current through it to a
low level. So multiple fins are used in parallel to provide higher drive strengths.

Figure 2 FinFET cross-section

The width of a single fin is 2h_fin+t_fin
The aspect ratio used in finFET is 2:1= h_fin/t_fin
The use of multiple parallel fin introduces fin spacing or fin pitch, the fabrication process is such
that the fin spacing or fin pitch exceeds the device width.
The fin pitch < (2h_fin+t_fin)
Fin engineering (balancing height, fin thickness, oxide thickness and channel length) is essential
in minimizing the leakage current.
Usually finFET was developed for use on SOI wafer, but can be fabricated on SOI or bulk Si
substrate. The steep doping profile used to control the leakage in the bulk substrate has a
beneficial impact on the DIBL. By reducing Source/Drain to body junction depth with respect to
the bottom of the gate, the finFET sub threshold characteristics can be improved to become equal
or better than the SOI finFET while keeping the good-on state performance. Figure 3 shows a
SOI and bulk FinFET.
Bulk FinFET
In a Bulk finFET the narrow fins were fabricated on bulk Si (100) substrate by special etching,
followed by isolation region formation and Punch through Stop (PTS) formation. After that the
gate stack is formed by SiON gate dielectrics and poly-Si. The narrow fins widths were formed
by the combination of High precision RIE (Reactive-ion-etch) and the fin trimming process. The
gate length is scaled down with Etch Back (EB) lithography and mask trimming. The fin width
in the channel length direction is very uniform in the multi fin structure. The bulk silicon
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Intro to FinFET: Challenges for 14nm and Beyond

substrate from which the fin is fabricated is undoped (very low impurity concentration per
cm**3) the switching input threshold device is set by the work function potential difference
between the gate, dielectric and undoped silicon materials. To block the punch through current
between Source/Drain nodes from carriers not controlled electro statically by gate input,
impurities are added below the fin to provide a punch through stop (PTS) without disturbing the
undoped concentration in the fin volume. The dielectric between the pedestals that remain after
the etch back serves as the field oxide, the gate material traversing between parallel fins is well
separated from the substrate, minimizing the Cg parasitic capacitance.

Figure 3 - SOI and Bulk finFET

The finFET on bulk substrate has more advantage than the SOI, such as lower wafer cost,
improved thermal conductivity, 2x times holes mobility, better immunity to heat transfer
problems, negative bias temperature stress and ease of combination with conventional CMOS
planar devices. By reducing the junction depth, relaxes the demand of fin width scaling at a
given technology node for suppression of short channel effect. For all channel doping cases, bulk
fin has lower DIBL than SOI. Bulk finFET with shallower junctions has good sub threshold
performance even with high body doping density. To avoid negative Vt due to lightly doped
body, gate stacking is used.
But there are few limitations too for the Bulk finFET. Bulk finFET has more sensitivity to body
doping than the SOI finFET. Bulk finFET Vt is larger than SOI in both saturation and linear
region because of body tied structure. A high channel doping may cause Vt variation due
to discrete impurity fluctuation problem in extremely scaled fins. A highly doped body causes
slightly higher Vt and thus lower on state current. In order to have the bulk fin characteristics
same as SOI, the bulk fin should be lightly doped (undoped) body while the Vt should be carried
out by the metal gate with proper work function.
Planar CMOS has several leakage mechanism, sub threshold leakage, gate leakage, reverse
biased junction, band-to-band tunneling, DIBL. In finFET we have two leakage mechanism, the
sub threshold leakage and the gate leakage. Bulk Fin has large junction leakage current and the
large junction capacitance Cj due to high impurity region in channel region. The steep doping
profile used to control the leakage in the bulk substrate has a beneficial impact on the DIBL, but
increased doping has a negative impact on the variability. It is difficult to build the finFET
reliably, as the finFET was designed to be built on SOI wafers, the oxide layer provides a stop
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Intro to FinFET: Challenges for 14nm and Beyond

for the etch process used to define the channel fins. On bulk Si the control of the fin depth is
more difficult, although the manufacturing issues appear to be manageable.

3. FinFET Challenges and Limitations

FinFET provides advantage in packing density, carrier transport and device scalability. In terms
of power optimization designers can trade leakage for switching speed. The increased voltage
helps keep flicker noise under control, as well as improved matching, higher current drive and
higher gain. The low impurity concentration in the fin results in less scattering when the device
is active improving the carrier mobility and device current. In planar for multiple threshold
device the Channel Random Dopant fluctuation from dopants is high whereas in finFET it is
little. A planar CMOS has several leakage mechanism, sub threshold leakage, gate leakage,
reverse biased junction, band-to-band tunneling, DIBL. In finFET we have two leakage
mechanism, the sub threshold leakage and the gate leakage.
The finFET has more on current, resulting in faster switching times. The Ion and Ioff increase as
the fin thickness increase (t_fin). The increase in Ion is due to a reduction in fin and parasitic
Source/Drain resistances, while decreased gate control over the channel causes an increase in the
Ioff. The carrier mobility is less at the surface channel due to increased scattering. Carriers that
terminate the gate electric field in the body of the fin away from the surface will have greater
mobility when a drain-source potential is applied. The thickness of the carrier inversion layer in
the fin is also a critical parameter to device current.
The variation in fin dimensions results in small variation in the on current. FinFET could be
fabricated with either high-k metal gate gate first or gate-last process. In gate last sequence,
a dummy polysilicon gate is initially patterned and used for Source/Drain formation, then the
gate is removed and the replacement metal gate composition is patterned. FinFET also requires a
unique process after gate patterning and Source/Drain node formation to suitably fill the three
dimensional grid of parallel fins and series gates with a robust (low k) dielectric material.
Contacts to the Source/Drain and gate will leverage the local interconnect metallization layer.
Even though there are many advantages of finFET but it does have challenges and limitations to
overcome.
The freedom to choose device width is reduced in finFET, especially for devices that are
close to the minimum size as drive strength can only be improved during layout by
adding more fins. The effective width of the device becomes quantized and the
quantization effect is worse for smaller transistors for which the next step up from the
minimum size device is the one that is twice as wide. The quantization of device width in
the SRAM arrays and the analog circuits are the most impacted by the quantized width of
finFETs especially SRAM bit cells, where a high layout density and robust
readability/writability criteria both need to be satisfied. The problem of using minimum
sized devices throughout the SRAM can create problems for static noise margins
reducing the ability of the system to reliably read a memory cell.
The minimum number of fins may be two in practical manufacturing process. This is due to
the self aligned spacer process that are used to create fins at tighter pitches, each
sacrificial spacer element that is deposited creating a pair of fins.
Due to 3D topology, the parasitic RC is increased, that must be extracted and modeled. The
designers can not just model the transistor length and width, now they have to consider
the Rs and Cs inside the transistor, local interconnect, fins and gates that are critical to
predict the transistor behavior.
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Intro to FinFET: Challenges for 14nm and Beyond

 The layer used beneath Metal1 is highly resistive and the resistance is non-uniform and
depends on where the bias are placed, therefore there will be 100x difference in
resistivity between top metal and lower metal layer.
The smaller geometries, double patterning which is needed to print correctly with current
lithography equipment. It requires extra mask along with a colorized decomposition
process that determines how layout features will be implemented by different masks.
Layout dependent effects occur because the layout feature placed near to a cell or device
will impact its timing and power. Electro migration is more of a concern as geometries
shrink.
In finFET technologies, different device thresholds would be provided by alternative gate
metallurgy with different work function potential.
The fin edge roughness will result in variation in device Vt and drive current. Chemical etch
steps that are selective to the specific silicon crystal surface orientation of the fin sidewall
are used to help reduce roughness known as Annealing process. The fabrication of the
gate traversing the topology cover and between fins will increase the Gate Edge
Roughness of finFET.
The undoped fin results in high series resistance outside the transistor channel, which
would otherwise negate the drive current benefits of finFET.
To reduce the resistance of source and drain a spacer oxide is deposited on finFET gate
sidewalls. To increase the volume of Source/Drain, a silicon epitaxial growth step is used.
The exposed Source/Drain regions of the original fin serve as the seed for the epitaxial
growth, separated from the finFET gate by the sidewall spacer. The incorporation of
impurities of appropriate type during epitaxial growth reduces the Source/Drain
resistivity to a more tolerable level. The resistivity is further reduced by silicidation of the
top of the Source/Drain region. In case of p-fet the additional small percentage of Ge
during this epitaxy step transfers silicon crystal stress to the channel, increasing hole
carrier mobility significantly.
Raised Source/Drain epitaxy reduces the Rs/Rd for planar fet as well. The topography of
the top surface for subsequent metallization coverage is very uneven. The current
distribution in the Source/Drain nodes outside the channel and thus the effective Rs and
Rd is quite complex.
While finFET provides excellent electrostatic characteristics they suffer from significant
self heating. The small and confined dimensions of the fin reduces the thermal
conductivity (which increases the thermal resistance) of the device due to reduced
phonon mean free path. Heat transport out of the device is hindered and the device
temperature rises. For finFET it is the temperature of the source that impacts the current
generation.
Device density variation can lead to dishing, the fins at the edges of a cluster suffer higher
variability than those in the middle and these effects lead to greater need for the use of
dummy fill shapes to reduce the variation due to density.
As the channel is extremely thin the gate has much greater control over the carriers within it
but when the device is switched on the shape limits the current through it to a low level.
So multiple fins are used in parallel to provide higher drive strengths. A larger height
complicates processing and causes defects.
In finFET there is almost no channel doping and back biasing the gate is very area
inefficient even where possible, the main technique for adjusting threshold is to
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Intro to FinFET: Challenges for 14nm and Beyond

manipulate the work function of the gate. An alternative that will push up the variability
and may have a knock on effect on the fin pitch and therefore cell density is to dope the
channel.
The effect of finFET on the cell library, the performance of n-channel is less dependent on
lattice orientation than with todays planar devices, the mobility curve for n-fet on 100
and 110 crystal surface follows the same profile, but in p-fet the 110 has better
performance, but this change in orientation dependency makes it possible to optimize the
layout for p-channel performance by aligning transistors to the 110 direction and then
using fewer dopants in the p-fet to reduce the level of carries scattering. Another thing is
to introduce Ge into the fin of p-channel to improve the carrier mobility.
Designers doesnt have the ability to control the channel as easily and the higher
Source/Drain resistance cuts transconductance. Designers have little choice over voltages
for I/O and have to develop more complex methods to achieve ESD immunity.
The contours of the fin where the curvature is largest will have the dense electric field, and
thus the highest carrier density, in both the on (Vgs> Vt) and sub threshold leakage
(Vgs<=Vt) condition. The short channel performance of finFET could be improved by
reducing fin width, but this will introduce a large parasitic Source/Drain resistance,
degrading the device drive current. With a wide fin (hence less parasitic), finFET with
longer channel show good DC performance.

4. Beyond 14nm
Although finFETs benefit from a fully depleted channel, they can provide a significant delay
improvement at a lower Vdd or much lower Vdd at the same delay. The existing finFET
struggles from performance and variability perspective. Also the fin profile shape is also a
concern, as we like to have a slanted profile that makes it easy to fill the dielectric between the
fins, but this creates a design that drags down the performance and introduces variability. Too
few fins can also cause variability. Another problem is non-uniform fin doping. Some
other challenges are that as the finFET characteristics depends on fin width and height
uniformity. Parasitic resistance crosses over strained Silicon channel resistance due to the narrow
Source/Drain width. While planar transistors support an unconstrained selection of device width,
all fin width and heights are identical, thus to change the drive strength, only a quantized channel
width is available in finFET, adding fins in discrete increments. 3D device modeling is needed to
capture fin profile data and geometry shapes. Complex middle-of-line parasitic modeling is
needed.
As we are running out of ways to scale planar transistor technology, so we are moving into 3D
devices FinFET and chip stacking and beyond that is atomic dimensions era that will bring a new
material like carbon nanotubes. As the EUV will not be ready till 7nm node so have come up
with immersion technologies including double and triple patterning, sidewall image transfer and
directed self assembly. While double patterning (the use of two masks to print alternating
features) will make immersion lithography practical at 20nm, but a new approach will be needed
at 10nm. This will be sidewall image transfer (SIT) also called self aligned double patterning and
that is more complex than todays Litho-etch-litho-etch( LELE) methodology that uses two
masks to print alternating features .
Sidewall image transfer involves depositing a film, etching it to create a sidewall and then using
a cut mask to generate the structure we want. The step that defines the fin thickness uses
Sidewall image transfer (SIT) . A low pressure chemical vapor (isotropic) deposition provides a
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Intro to FinFET: Challenges for 14nm and Beyond

unique dielectric profile on the sidewall of the sacrificial pattered line. A subsequent anisotropic
etch of the dielectric retains the sidewall material.
As we move to 10nm FinFET the p-FinFET shows high transconductance. The parasitic Rsd in
the narrow fin influences the device performance. While fabricating, the poly-Si gates were
doped by ion implantations and subsequently activated with RTA(Rapid Thermal Anneal). A
193nm and 248nm wavelength optical lithography were used to pattern the Si fin and the gate
respectively. A pattern reduction technique was used to produce both fin width and gate length of
10nm. A nitride oxide with 17A physical thickness was used as the gate insulator. Other process
features include low temperature Source/Drain annealing, NiSi and Cu metalization. The
conducting channels were formed on the two vertical sidewalls of the silicon fin, which are in the
110 crystal orientation. A thin sacrificial oxide was formed and later stripped completely to
remove the Si surface damage caused during the plasma etching of the fin stack. A thin
insulating cap layer is retained on top of the Si fin.
A good short channel performance is observed because of the dual gate control and significant
grading of the Source/Drain junction. A largely graded Source/Drain junction reduces the
electrical coupling from the drain biasing, relaxing the strict requirement on fin width scaling.
The fin aspect ratio is determined by circuit design and fabrication considerations. Maximum fin
height with 5:1 aspect ratio. Minimum fin height for area efficiency. Moderate fin height with
min device Wg=5Lg. The short channel performance of the finFET can be improved by reducing
the fin width. This introduces a large parasitic Source/Drain resistance, degrading the device
drive current.With a wide fin (hence less parasitics), finFETs with longer channel show good DC
performances.
The peak transconductance of the p-finFET is very high because of the large hole mobility. The
electron mobility in a (110)FinFET channel is decreased with that in a (100) planar channel
while the hole mobility is improved and is 100% higher than the planar FET due to reduced
vertical electric field in the inversion layer and the different channel crystal orientation. Both
conditions of sacrificial oxidation resulted in comparable mobility, suggesting that a clean oxide
interface can be obtained with a sacrificial oxidation of 50A. The direct tuneling leakage through
thin gate oxide(formed on sidewalls of the etched Silicon) in the FinFET is comparable to the
planar FET.
At 7nm we might need triple and quadruple patterning that might be highly expensive, an
alternative and less cost solution will be to use block co-polymers. If we create an anchor pattern
and apply the proper constrains, the co-polymers will align themselves in alternating parallel
patterns, we then cut away what we do not want. This is called directed self assembly.
As we will move towards 5nm, the next device innovation will be carbon nanotubes, which will
replace the fins on the device that still looks much like a finFET. Figure 4 and 5 shows a 5nm
FET with carbon nanotube between Source and Drain and a carbon nanotube structure. Because
of the great transport properties of carbon, we can get a 10X improvement in power or
performance. But there are two challenges, as 30% of the carbon nanotubes that are created are
metallic and must be sorted out. Another is placing the nanotubes where we want them on the
wafer. The carbon nanotube research is now well underway.

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Intro to FinFET: Challenges for 14nm and Beyond

Figure 4 - Carbon Nanotube Structure

Figure 5 - 5nm FET with carbon nanotube between S/D

All the above mentioned issues will impact the custom/analog designer. But digital designer may
also notice complex design rules, double patterning colorization requirement , more restriction
on access to cells and pin location. Finally some SOC designers will be asked to design and
verify a chip that has hundreds of millions of gates. Designers have to work on higher level of
abstraction and heavily reuse silicon IP.
The extraction tools, TCAD tools, Mask synthesis tools, physical verification tools need to be
enhanced to handle the Rs and Cs to predict the transistor performance for 14nm and 10nm
finFET and while moving to 5nm we need to enhance tools for the new material carbon
nanotube. This R and C and the stress variation effects are to be considered in the design at early
stage if needed to change the methodology in which the circuit designers and the layout
designers work closely. Figure 6 shows the parasitic capacitances in a 14nm FinFET.

Figure 6 - Parasitic Capacitances in FinFET

The physical design tool must be able to handle the new design rules for 14nm and carbon
nanotube. This includes placement, routing, optimization, extraction and physical verification.
The cell library must be co-optimized with these tools which includes both custom/analog

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Intro to FinFET: Challenges for 14nm and Beyond

/digital design. Feedback from EDA and IP developers can influence process development,
which will set new requirement for tools and IP.

5. Conclusions
This paper provides an introductory explanation of finFETs over planar process, the advantage
and limitation of SOI and Bulk substrate finFET and the limitation and challenges of finFET.
Although finFET would be a strong competitor or successor to planar CMOS, while a few non
show stopper issues (gate material engineering, parasitic reduction) need to be addressed, the
finFET is promising for the extremely scaled CMOS in which the packing density, scalability,
performance and power dissipation would be among the vital challenges. But moving further
towards 5nm and further we might need to switch to atomic dimension era of carbon nanotubes.

6. References
[1] Mirko Polijak, Vladimir Jovanovic and Tomislav Suligoj. "SOI vs. Bulk FinFET: Body doping and
Corner Effects Influence on Device Characteristics".
[2] Brian Swahn and Soha Hassoun. "Gate Sizing:FinFETs vs 32nm Bulk MOSFETs".
[3] K.Okano, T.Izumida, H.Kawasaki, A.Kaneko, A.Yagishita, T.Kanemura, M.Kondo, S.Ito, N.Aoki,
K.Miyano, T.Ono, K.Yahashi, K.Iwade, T.Kubota, T.Matsushita, I.Mizushima, S.Inaba, K.Ishimaru,
K.Suguro, K.Eguchi, Y.Tsunashima and H.Ishiuchi. "Process Integration Technology and Device
Characteristics of CMOS FinFET on Bulk Silicon Substrate with sub 10nm Fin Width and 20nm Gate
Length".
[4] Bin Yu, Leland Chang, Shibly Ahmed, Haihong Wang, Scott Bell, Chih-Yuh Yang, Cyrus Tabery,
Chau Ho, Qi Xiang, Tsu-Jae King, Jeffrey Bokor, Chenming Hu, Ming-Ren Lin and David Kyser.
"FinFET Scaling to 10nm Gate Length".
[5] Chi-Ping Hsu."16nm/14nm FinFETs:Enabling The New Electronics Frontier". Jan18, 2013.
[6] FinFET Wiki. SemiWiki Forum.
[7] Richard Goering. "Common Platform Forum Keynotes: 14nm FinFETs and Beyond". Feb 6, 2013.
[8] Dylan McGrath. "Globalfoundries looks to leapfrog fab rivals ". EETimes. Sep 20, 2012.
[9] Tsu-Jae King Liu. "FinFET History,Fundamentals and Future". 2012 Symposium on VLSI Technology Short Course. June 11, 2012.
[10] David Kanter, "Intels 22nm tri-gate transistors ". Real World Technologies. May 5, 2011.

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Intro to FinFET: Challenges for 14nm and Beyond