Name

Address:
Phone number: / Email:
OBJECTIVE
To secure a challenging position in Hi-Tech environment with dedicated and committed people where I can effectively contribute
my skills as electronics and computer professional, possessing competent Technical Skills.

SKILLS
EDA Tools:

Cadence Verilog XL, Synopsys (VCS Compiler, SimVision, Prime Time, Design Vision,
Design Compiler), Veri ProLogger, Cadence Virtuoso, ModelSim, Questasim.
Debugging Tool:
Spring Soft Verdi, Debussy, Synopsys DVE.
Operating Systems:
DOS, Windows, Red Hat Enterprise Linux, Centos, Windows CE .
Software Proficiency:
Microsoft Assembler (TASM), Visual Basic, Xilinx ISE, Matlab, Simulink, Platform Builder.
Hardware Level Languages: Verilog, VHDL, System Verilog.
High Level languages:
C, C++.
Assembly Level Languages: 8085, 8086, 8051, ARM assembly.
Scripting Languages:
Perl, TCL, UNIX.
Lab Equipments:
Oscilloscopes, Function Generators, Logic Analyzer, Logic Probes, and Multimeters.
Communication Skills:
Bilingual: English/Hindi, Excellent verbal and oral communication skills
Excellent leadership, team work and time management qualities enhanced by group projects
and extra curriculum activities

PROFESSIONAL EXPERIENCE

XXX Corporation, City, State

Pre-Silicon Verification Engineer

Jun. 2010 Present

Worked on one of the feature of DFx verification of next generation SOC using System Verilog OVM.
To meet the low power verification goal of SOC, I am doing low power verification using MVSIM Synopsis.

XXX Ltd, City, State

ASIC Verification Engineer

Mar 2007 - Nov 2007

Development of I2C SV (System Verilog) Verification Environment(VE).

There are various blocks of SVVM (System Verilog Verification Environment) such as BFM, Monitor, Driver, and
Checker that were implemented.
WISHBONE interface was used to connect ports between test environment and DUV. Test cases were written to check the
special scenarios and corner cases for DUT.
The Preliminary functionality of I2C was verified by running it against itself.
Development of Micro UART SV (System Verilog) Verification Environment(VE).
Implemented all blocks of SVVM, and also complete Functional Coverage measurement including stimulus condition and
device response.
The Preliminary functionality of DUT was verified by writing corner and special cases in Test Bench.
Development of Ethernet Protocol Verification Environment using C++.
Generator, BFM, Monitor, Utility and checker were implemented for VE.
Test cases were written to verify generated actual packets data by DUT with expected data output in checkers.

XXX Ltd, City, State

Jun 2005 June 2006

Designed microcontroller using Verilog HDL on Xilinx Platform:

Studied various microcontroller architecture and its instruction set. By taking reference of them, simple 8-bit Microcontroller
was designed using top-down methodology by Verilog-HDL, and synthesized using Synopsys VCS tool. Synthesized
preliminary design and optimized it according to architectural specification.

EDUCATION
MS, Electrical & Electronics Engineering,
XXXXX University, Los Angeles

PATENTS/AWARDS

Month-Year

Reference Available upon request