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VL7301 Testing of VLSI Circuits
VL7301 Testing of VLSI Circuits
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UNIT-3DESIGN FOR TESTABILITYPART-A
1. What are the advantages of using DFT approach for testing?2. Define Predictability?It is an ability to obtain
known output values in response to given input
stimuli.3. List out the characteristics that influences various cost associative with testing?Status of a device to be
determined and the isolation of faults within the device to be performed quickly toreduce both test time and
cost. The cost effective development of the tests to be determine this status.4. What are the classifications of
test points?Test points are classified into two typesControl points (CP) - CPs are primary inputs to enhance
controllability.Observation points (OP) - Ops are primary outputs to enhance observability.5. Define Initialization?It
is a process of bringing a sequential circuit into a known state at some known time, such as when it is powered on or
after an initialization sequence is applied.6. List out the types of generic scan based design?Full serial integrated
scanIsolated serial scan Non serial scan7. State the LSSD design rules?All internal storage elements must consist of
polarity hold latches. Latches can be controlled by two or morenon overlapping clocks. Clock primary inputs cannot
feed the data inputs to latches, either directly or throughcombinational logic. They may only feed clock inputs
ti latches or primary outputs.8. List out the uses of scan design?Flipflops and latches are more complex. Hence scan
designs are expensive in terms of board or silicon area.Some designs are not easily realizable as scan designs. Test generation
costs can be significantly reduced. This canalso lead to higher fault coverage.PART-B1. Discuss briefly about generic
scan based design techniques?
2. How Ad-hoc designs are used to improve testability digital circuits? Explain with examples.3. Discuss on system
level DFT techniques?4. Explain any four ad-hoc design methods used for improving the testability of digital
circuits.5. Discuss on system level DFT techniques.6. Explain about the following i) Classical scan based design and
ii) LSSD design rules.
UNIT-4SELF TEST AND TEST ALGORITHMS
2. List out the categories of test pattern generation approaches for BIST?Exhaustive/Pseudo
exhaustive testingPseudo random testingDeterministic testing3. Draw the BIST structure4. What are the methods to
derive n input and m output combinational circuit?

Syndrome driver counter

Constant weight counter

Linear feedback shift register/ shift register(LFSR/SR)

Linear feedback shift register/ EX-OR gates(LFSR/EX-OR)5. List out the BIST architectures?

BILBO

STUMPS

LOCST6. Mention the test algorithms for RAMs?

GALPAT

WALKING 0s AND 1s

March Test

Checkboard test7. List the types of coupling faults exist in memories?Inversion coupling faultIdem-potent fault OR
State coupling fault8. Mention the advantages of transition counting?It is not necessary to store either the correct response
sequence or the actualresponse sequence at any test point; only the transition counts are needed.9. What are the advantages of
circular BIST?

It provides high fault coverage.Low hardware overhead.10. List out the methods of pseudo exhaustive pattern
generation?Syndrome driver counterConstant weight counterLFSR/SR
PART-B
1. Discuss the test pattern generators used in BIST.2. Discuss the fault models used in memories and explain how tes
t generation is done for embedded RAM3. Draw the circular BIST architecture and explain how testing is done usin
g this architecture.4. Explain any two test algorithms used for testing memories.5. Explain about test generation and
Built in self-test for embedded RAM.
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