MIDDLE EAST TECHNICAL UNIVERSITY NORTHERN CYPRUS CAMPUS

ELECTRICAL AND ELECTRONICS ENGINEERING PROGRAM

EEE-413 (3-0)3

INTRODUCTION TO VLSI DESIGN

Fall-2015

Instructors Name

Office

Phone

e-mail

AL MUHTAROLU

S-141

661 2969

amuhtar@metu.edu.tr

Course Schedule: M. 15:4016:30; W. 11:4013:30 (TZ-13)

Office Hours: T. 14:4016:30 or by appointment (S-141) Lab Recitation: TBD as needed (RZ-11)
Text:
Auxiliary
Texts:

Weste & Harris, Integrated Circuit Design, 4/e, Pearson, 2011.

Pucknell & Eshraghian, Basic VLSI Design, 3/e, Prentice Hall, 1995.
Rabaey, Chandrakasan, Nikolic, Digital Integrated Circuits, 2/e, Prentice Hall, 2003.
Mano & Kime, Logic and Computer Design Fundamentals, 4/e, Prentice Hall, 2008.
Books in the library on Linux OS

Software:

Cadence Mixed Signal IC Design Suite (IC 6.1.4), which will used for designing, drawing, and
simulating small to moderately sized integrated circuits in 180 nm technology. This tool suite
works in x86 Linux OS environment.

Catalog Description: Design techniques for rapid implementations of very large-scale integrated (VLSI)
circuits, MOS technology and logic. Structured design. Design rules, layout procedures. Design aids: layout,
design rule checking, logic, and circuit simulation. Timing. Testability. Projects to develop and lay out circuits.
Prerequisite: EEE 248 and EEE 312 or consent of the department.
Course Objectives: With the relentless drive to reduce cost, size, and power consumption while
simultaneously achieving performance goals, chip design issues (a.k.a. Very Large Scale Integrated Circuit
Design concerns) are at the center of electronics industry. CMOS digital circuit design, simulation, and layout
flow will be introduced in this course, and applied in assignments using state-of-the-art CAD tools commonly
used in the VLSI design industry. Students will use design metrics such as size, speed, power dissipation,
energy, and reliability to optimize IC design. Special subsystems (memory, packaging, I/Os, power and clock
distributions), testability issues, and common analog IC building blocks will finally be discussed as time allows.
Course Outline (Tentative):
Week
#

Week
Starts

5-Oct

12-Oct

3
4

19-Oct
26-Oct

Introduction, Design Metrics; Introduction to CMOS

Fabrication & Layout
Design & Fabrication Flow, Long-L MOSFET model
(review), Deviations from Long-Channel Model
CMOS Inverter Review & Delay Model
Logical Effort, Designing for Speed

5
6
7
8
9
10

2-Nov
9-Nov
16-Nov
23-Nov
30-Nov
7-Dec

Designing for Speed

Designing for Power
Wires, Combinational Circuits & Dynamic Gates
Other CMOS Logic Families
Sequential CMOS Circuits
Sequential CMOS Circuits; Midterm

11
14-Dec
12
21-Dec*
13
28-Dec
14
4-Jan
15-16 11,18-Jan

HW
Out

LECTURE

Datapath Subsystems, Arithmetic Circuits

Memory Design
Design Methodology, Design-for-Test
Package; Power; I/O; Scaling
Finals

CAD
CAD
HW
Assign. Assign.
Due
Out
Due

1
1

Prj

2
3

3
Prj

* No lecture on December 23rd (religious holiday) make-up lecture on December 19th.

Grading:

Midterm
Final
H.W. + Participation
CAD Assignments
Project

: 25%
: 35%
: 10%
: 10%
: 20%

Tentatively on Dec 9th in class (Wednesday)

Date/Time/Place To Be Determined
[Late HWs and CAD assignments are penalized
20% / week day]

Attendance is highly recommended to do well in this course. Those who miss > 20% of the lectures and
recitations, or the Midterm, will not be allowed to take the Final Exam, and will receive an NA grade
Will use ODTUClass (lms.metu.edu.tr) to post HWs, CAD assignments, lecture notes, announcements, etc.
If we hold recitations to go over homeworks, the corresponding solutions may NOT be posted.

Academic Integrity
Copying, communicating, or using disallowed materials during an exam is cheating. Students
caught cheating on a midterm or final exam will be reported to the campus disciplinary
committee. Students may not leave the classroom during exams; any student leaving the
classroom is leaving the exam.
Academic integrity is a more complicated issue for assignments and CAD exercises, but one
we take very seriously. The following rules will be in force for all HWs and CAD assignments:
Students are allowed to work together in brainstorming solutions, in interpreting error
messages from tools, and in discussing strategies for finding tool bugs, but NOT in
designing or implementing solutions.
Students may not share logic diagrams, schematics, equations, screen shots, or layout,
may not copy these, and may not discuss their solutions in detail at any time, i.e. while
it is being generated or afterwards.
Similarly, students may not receive detailed help on their solutions from individuals
outside the course. This restriction includes tutors, students from prior terms, internet
resources, etc.
Students may not show their solutions to other students as a means of helping them.
Sometimes good students who feel sorry for struggling students are tempted to provide
them with "just a peek" at their solution. Such "peeks" often turn into extensive copying,
despite prior claims of good intentions. No such claim will be accepted as an excuse for
ethical violations.
Students may not leave their solutions (either electronic versions or printed copies) in
publicly accessible areas. Students may not share computers in any way when there is
an assignment pending.
All students caught cheating on an assignment (both the copier and the provider) will receive
an automatic 0 for that assignment, and may be forwarded to METU NCC Disciplinary
Committee. No excuses, no discussions, no exceptions! If cheating persists, disciplinary action
will be taken for sure at university level. Remember, it is unethical to copy regardless of if you
get caught or not.
If citation is needed, proper and accurate citation for the used information sources must be
given. Any sort of plagiarism will not be tolerated.
For more details about plagiarism, please see
http://www.plagiarism.org/plagiarism-101/what-is-plagiarism