MC LC

MC LC.......................................................................................................................................1
DANH SCH HNH V................................................................................................................2
DANH SCH BNG......................................................................................................................3
DANH SCH T VIT TT........................................................................................................4
MC TIU.....................................................................................................................................5
CHNG 1 : TNG QUAN KIN TRC KHI TIN KHUCH AI...................................6
1.1.

V tr v thut ton...........................................................................................................6

1.2.

Giao din v cc kin trc chi tit bn trong..................................................................7

1.3.

Quy trnh thit k chip ASIC v v tr bc tng hp xung mc cng........................8

CHNG 2: TNG HP XUNG LP CNG.........................................................................9

2.1.

Mi trng tng hp.......................................................................................................9

2.2.

Chi tit cc rng buc....................................................................................................11

2.3.

Th vin tng hp..........................................................................................................11

CHNG 3: KT QU AT C.........................................................................................13
3.1.

Kt qu v phn tch v din tch..................................................................................13

3.2.

Kt qu phn tch v thi gian......................................................................................14

3.3.

Kt qu phn tch v cng sut.....................................................................................15

3.4.

Cc kt qu khc............................................................................................................17

3.5.

Phn tch tng quan gia thi gian v din tch.......................................................17

KT LUN V KIN NGH.......................................................................................................19

TI LIU THAM KHO.............................................................................................................20

DANH SCH HNH V

Hnh 1.1 M hnh l thuyt khi pre-emphasis.............................................................................6
Hnh 1.2 Giao din khi Trch c Trng vi h s cua Pre-emphasis co th thay i c...7
Hnh 1.3 Kin trc phn cng khi Pre-emphasis.......................................................................7
Hnh 1.4 Quy trnh thit k ASIC..................................................................................................8
Hnh 2.1 Cc bc tng hp........................................................................................................12
Hnh 3.1 Netlist cua khi pre_emphasis......................................................................................17
Hnh 3.2 Biu tng quan thi gian v din tch..................................................................18

DANH SCH BNG

Bng 2.1 M hnh thng tin mi trng tng hp.....................................................................10
Bng 2.2 Cc rng buc thit k..................................................................................................11
Bng 2.3 Th vin dng cho tng hp........................................................................................11
Bng 3.1 Tng quan thi gian v din tch..............................................................................18

I.DANH

SCH T VIT TT

ASIC

Application specific integrated circuit

STA

Static timing analysis

DFT

Design for test

P&R

Place and Route

MC TIU
Tng hp, phn tch sai khc gia thit k phn cng khi Tin
Khuych i mc thanh ghi (RTL) vi mc cng vt l v ti u,
nh gi hiu nng
Thit k m hnh kin trc chi tit phn cng khi Tin Khuch
ai bao gm khi lung d liu v khi iu khin
Quy trnh tng hp xung lp Cng
Nghin cu v xy dng mi trng v th vi n tng hp cho
khi Tin Khuch ai.
anh gia cac kt qua v di n tich, thi gian, cng sut v cac kt
qua khac

CHNG 1 : TNG QUAN KIN TRC KHI

TIN KHUCH AI
1.1. V tr v thut ton
Khi Pre-emphasis l mt trong nhng kin trc thnh phn ca khi MFCC c
m ta chi tit hnh v

Hnh 1.1 M hnh l thuyt khi pre-emphasis

Quan sat hnh v 1.1 cho thy ng vo ca khi Pre-emphasis l sau khi qua tin x
li vi cac b ct m thanh. Gia tr sau khi i qua khi Pre-emphasis s c lu tr trn
cac b nh ni trung gian v s l d liu ng vo cho khi Winodow k tip
Sau khi phn tich thut toan v m phng trn phn mm (Matlab- Window) v
phn cng (VCS Synopsys - Linux), thit k c hin thc trn nn tang FPGA nhm
chng t mt ln na kha nng hin thc cao trong quy trnh thit k chip ASIC. Thut
toan cui cng c s dng qua cng thc 1.1
(1.1)

iu cn quan tm l tinh linh ng ca khi Pre-emphasis s c kim chng

hiu qua khi tng hp xung lp cng phn tip theo sau y. Da trn kt qua tng
hp v phn tich s cho thy s chn la cui cng hp l nht khi kt ni vi h thng.

1.2. Giao din v cc kin trc chi tit bn trong

Giao din ca thit k khi Pre-emphasis c nhc lai hnh v sau

Hnh 1.2 Giao din khi Trch c Trng vi h s cua Pre-emphasis co th thay i c

Chi tit phn cng ca khi cng c th hin bi cac hnh v sau :

Hnh 1.3 Kin trc phn cng khi Pre-emphasis

1.3. Quy trnh thit k chip ASIC v v tr bc tng hp xung mc cng

Hnh v 1.4 m ta y quy trnh thit k chip ASIC

Hnh 1.4 Quy trnh thit k ASIC

Vai tr chuyn nhm tng hp thit k RTL c kim chng nhm anh gia
s b hiu nng ca thit k ring l cng nh ton b h thng. c lng ban u
trc khi tin hnh bc t v i dy cho php tinh toan gn nh chinh xac hiu nng
ca thit k .

CHNG 2: TNG HP XUNG LP CNG

2.1. Mi trng tng hp
Mi trng tng hp xung mc cng ca khi Tin Khuch ai c thc hin
trn h iu hnh Linux c th bc th mc nh sau:
chuyen_de
|-- 05_Code MFCC
|
|-- 01-Preemp
|
|-- 02-windowing
|
|-- 03-FFT
|
|-- 04-magnitude
|
|-- 05-Filter bank
|
|-- 06-Logarithm
|
|-- 07-Cepstral
|
|-- 08-Energy
|
`-- 09-Delta
|-- design_compiler
|
|-- command.log
|
|-- dc_command.src
|
`-- run
|-- formality
|
|-- fm_shell_command.log
|
|-- fm.tcl
|
|-- formality.log
|
|-- formality_svf
|
|-- log.formality
|
|-- RESULT
|
|-- run_fm
|
`-- preem.fmv_unmatched_points.rpt
|-- library
|
`-- TSMC_130nm
|-- rtl
|
|-- preemp.v
`-- vcs

Cng c v nn tang tng hp c tm tt chi tit qua bang biu sau:

Bng 2.1 M hnh thng tin mi trng tng hp

H iu hnh

Linux

Ngn ng tao mi
trng

Bash Shell

Ngn ng thit k

Verilog

Th vin s dng

TSMC 130nm

Cng c

Design compiler

Thit k

Preem.v

Tn file chinh

preemp.v

Cac rng buc

+ Tr hon ng vo
+ Tr hon ng ra
+ Tn s xung clock
+ S dng b nh ni
+ Reset bt ng b
+ Tr hon clock

10

2.2. Chi tit cc rng buc

Chi tit cac rng buc trong bang 2.2 c th hin chi tit qua file rng buc tng
ng vi cac thit k khac nhau sau y:
Bng 2.2 Cc rng buc thit k

create_clocknameclkperiod2{clk}
set_input_delaymax1.0clockclk{get_inputin}
set_input_delaymax1.0clockclk{get_inputen}
set_input_delaymax1.0clockclk{get_inputnewspeech}
set_input_delaymin0.0clockclk{get_inputin}
set_input_delaymin0.0clockclk{get_inputen}
set_input_delaymin0.0clockclk{get_inputnewspeech}
set_input_delaymin0.0clockclk{get_outputout}
set_input_delaymax1.0clockclk{get_outputout}

2.3. Th vin tng hp

Th vin chn cho thit k l th vin TSMC 130nm. Cu trc c ban ca th vin
TSMC 130nm c th hin nh trong bang sau:
Bng 2.3 Th vin dng cho tng hp
[root@localhost 01_preemp]# tree -L 4
library/
library/
`-- TSMC_130nm
`-- sc-x
|-- cell_list
|-- symbols
| |-- cadence
| |-- edif
| `-- synopsys
|-- synopsys

| |-- README
| |-scx2_tsmc_cl013g_ff_1p32v_0c.lib
| |-scx2_tsmc_cl013g_ff_1p32v_m40c.db
| |-scx2_tsmc_cl013g_ff_1p32v_m40c.lib
| |-scx2_tsmc_cl013g_ss_1p08v_125c.db
| |-scx2_tsmc_cl013g_ss_1p08v_125c.lib
| |-scx2_tsmc_cl013g_tt_1p2v_25c.db
11

| `-scx2_tsmc_cl013g_tt_1p2v_25c.lib
`-- verilog
|-- README
|-- tsmc13.v
`-- tsmc13_neg.v

2.4. Cc bc c bn tng hp
Cac bc c ban tng hp c soan thao chay theo tp nhiu lnh c th hin
cac hnh v sau

Hnh 2.5 Cc bc tng hp

12

CHNG 3: KT QU AT C
3.1.

Kt qua v phn tich v din tich

Cac file tng thut cho php thy c kt qua din tich c lng nh sau:
Report : area
Design : preemp
Version: C-2009.06
Date : Fri Mar 28 11:31:24 2014
****************************************
Library(s) Used:
scx2_tsmc_cl013g_tt_1p2v_25c
(File:/root/TamNguyen/Work/01_chuyen_de/01_preemp/library/TSMC_130nm/scx/synopsys/scx2_tsmc_cl013g_tt_1p2v_25c.db)
Number of ports:

54

Number of nets:

232

Number of cells:

179

Number of references:
Combinational area:

24
957.333596
13

Noncombinational area:

1682.123344

Net Interconnect area:

undefined (No wire load specified)

Total cell area:

2639.456941

Total area:

undefined

3.2.

Kt qu phn tch v thi gian

Kt qua tng thut cho thy cac yu cu v mt thi gian c ap ng. Ch s

SLACK cho thy kha nng tng thm tn s s c tng thut chi tit phn tip
theo.
report_timing
Warning: Design 'preemp' has '1' unresolved references. For more detailed
information, use the "link" command. (UID-341)
****************************************
Report : timing
-path full
-delay max
-max_paths 1
Design : preemp
Version: C-2009.06
Date : Fr Mar 28 11:31:24 2014
****************************************
Operating Conditions: tt_1p2v_25c Library: scx2_tsmc_cl013g_tt_1p2v_25c
Wire Load Model Mode: top
Startpoint: in[1] (input port clocked by clk)
Endpoint: b_reg[10] (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Point

Incr

Path

----------------------------------------------------------14

clock clk (rise edge)

0.00

clock network delay (ideal)

input external delay
in[1] (in)
U71/Y (OR2X1)

0.00

0.00

0.00

1.00
0.00

1.00 f
1.00 f

0.16

1.16 f

U70/Y (NOR4X1)

0.10

1.25 r

U69/Y (NOR4X1)

0.07

1.32 f

U68/Y (NAND4X1)

0.10

1.42 r

U124/Y (OAI22X1)

0.07

1.50 f

U129/Y (NOR2BX4)

0.11

1.60 f

U125/Y (NOR3X2)

0.20

1.80 r

U32/Y (OAI211X1)

0.07

1.87 f

b_reg[10]/D (DFFRX1)

0.00

data arrival time

clock clk (rise edge)

1.87
2.00

clock network delay (ideal)

2.00

0.00

b_reg[10]/CK (DFFRX1)
library setup time

1.87 f

2.00

0.00
-0.13

data required time

2.00 r

1.87
1.87

----------------------------------------------------------data required time

data arrival time

1.87
-1.87

----------------------------------------------------------slack (MET)

0.00

3.3. Kt qu phn tch v cng sut

File tng trnh sau cho bit cng sut tiu th ca khi kin trc Pre-emphasis c
chi tit ha
report_power

15

Loading
db
'/root/TamNguyen/Work/01_chuyen_de/01_preemp/library/TSMC_130nm/scx/synopsys/scx2_tsmc_cl013g_tt_1p2v_25c.db'

file

Information:Propagating switching activity (low effort zero delay simulation).(PWR-6)

Warning: Design has unannotated primary inputs. (PWR-414)
Warning: Design has unannotated sequential cell outputs. (PWR-415)
Warning: Design has unannotated black-box outputs. (PWR-428)
****************************************
Report : power
-analysis_effort low
Design : preemp
Version: C-2009.06
Date : Fri Mar 28 11:31:26 2014
****************************************
Library(s) Used:
scx2_tsmc_cl013g_tt_1p2v_25c
/root/TamNguyen/Work/01_chuyen_de/01_preemp/library/TSMC_130nm/scx/synopsys/scx2_tsmc_cl013g_tt_1p2v_25c.db)
Operating Conditions: tt_1p2v_25c Library: scx2_tsmc_cl013g_tt_1p2v_25c
Wire Load Model Mode: top
Global Operating Voltage = 1.2
Power-specific unit information :
Voltage Units = 1V
Capacitance Units = 1.000000pf
Time Units = 1ns
Dynamic Power Units = 1mW (derived from V,C,T units)
Leakage Power Units = 1pW
Cell Internal Power = 803.7273 uW (95%)
Net Switching Power = 40.3947 uW (5%)
--------Total Dynamic Power

= 844.1219 uW (100%)
16

(File:

Cell Leakage Power

= 529.5368 nW

3.4. Cc kt qu khc
File tng trnh sau y cho bit chi tit cng v DFF no c tng hp v chn la
trong th vin sau khi thc hin bc thit k ny

Hnh 3.1 Nestlist cua khi Pre-emphasis

3.5. Phn tch tng quan gia thi gian v din tch
Phn tich s tng quan gia thi gian v din tich cho thy vic tng tn s s lm
din tich tng ln cho thy tc v din tich t l nghch ng vi quy lut thit k
Bang s liu so sanh khi khao sat vic tng tn s cho thy r hn nhm a ra chn
la ng n tn s ph hp cho thit k b pre_emphasis cng nh ton b vi mach

17

Bng 3.4 Tng quan thi gian v din tch

No.

Tn s

Din tich

2 Ghz

2891.90348

1 Ghz

2809.87465

500 MHz

2639.456941

400 MHz

2244.837653

200 MHz

1892.938282

100 MHz

1424.78349

50 MHz

1015.88093

25 MHz

7983.89247

20 Mhz

5987.87378

10

10 Mhz

3353.98378

18

Hnh 3.6 Biu tng quan thi gian v din tch

19

KT LUN V KIN NGH

Kt Lu n :
Bao cao gii thi u s lc v thu t toan khi Pre-emphasis cng nh quy trnh
tng hp m t thit k xung lp cng.
Bao cao trnh by c quy trnh tng hp khi Pre-emphasis xung cng m t
cach chi tit v: Mi trng tng hp, chi tit rng bu c trong qua trnh tng hp,
th vi n tng hp.
Bao cao cng a ra c m t s kt qua chi tit ca qua trnh tng hp v: Thi
gian, di n tich, cng sut, v m t s kt qua khac.
Kin Ngh :
Tng hp khi pre-emphasis vi nhiu h s a khac nhau.
Thay i th vi n tng hp c nhiu kt qua tng hp hn.

Ch nhim ti
(k tn)

i din c quan ch tr ti
(k tn v ng du)

TS.HONG TRANG

20

TI LIU

II.

THAM KHO
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Ngn Ng Ting Vit, ti cp Nh Nc KC01-03, nm 2001-2004.
[2] Lng Chi Mai , Nghin cu, phat trin mt s san phm tiu biu v thit yu v x l
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khin, B mn C in t - Khoa C khi ai hc Bach Khoa TPHCM
[4] Wei HAN, Cheong-Fat CHAN, Chiu-Sing CHOY and Kong-Pang PUN, An Efficient
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[5] Wei HAN, Cheong-Fat CHAN, Chiu-Sing CHOY and Kong-Pang PUN, A Speech
Recognizer with Selectable Model Parameters, Circuits and Systems, 2005. ISCAS 2005.
IEEE International Symposium, May 2005, pages: 5842-5845
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Technology, Master thesis, University of McGill, 2007.
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23