II.

MONOLITHIC HETEROGENEOUS INTEGRATION OF INP

High Performance Hybrid System consisting of InP

HBT, GaN, Si CMOS and FRAM memory
Madhuri Suthar, Ph.D. student, Jalali Lab, UCLA
Abstract In this work an approach for direct monolithic
heterogeneous integration of InP HBT, GaN and Si CMOS on a
Silicon Substrate is illustrated and recommended for high
performance hybrid systems. InP HBTs and GaN performance
comparable to fabrication on their native substrates is achieved
with this method. This is followed by incorporating an FRAM
memory wafer (200 mm diameter) onto the CMOS logic wafer
(200 mm diameter) by WOW stacking method. The ultrathinning technology in WOW stacking is used to reduce wafer
thickness to sub 10 micrometer levels.

I.

INTRODUCTION

HE continuous downscaling in bulk silicon (Si)

complementary
metal-oxide
semiconductor
(CMOS) technology is the main driving force for
the industries to maintain high performance of devices, lower
the power consumption and reduce cost per transistor [1,2].
However, this down scaling of devices has now reached a
fundamental bottleneck. Further shrinkage of the CMOS
device makes the CMOS devices unreliable [3] owing to short
channel effects and also more expensive [4] owing to the
enhanced lithography. To address this problem, 3D integration
which is a solution for monolithic integration of different
Heterogeneous Integration (HGI) device technology is
proposed.
The recent work done for HGI device technology include
approaches like wafer-scale assembly approach [5] at
Northrup Grumman to integrate completed IIIV chiplets on
top of a completed CMOS wafer based on the use of microbumps to interconnect two or more different devices and/or
components with Si CMOS. This approach preserves device
performance by fabricating different devices on their native
substrates. However, in an another approach by HRL
Laboratories, LLC [6], IIIV epitaxy layer is transferred to the
top of a completed CMOS wafer. The IIIV devices are then
fabricated in situ on top of the CMOS wafer to provide
precision placement of the IIIV device relative to the Si
transistors. [6].
In our approach presented here three-dimensional integration
followed by stacking of Si CMOS wafers is presented. The
benefit of using this approach is the monolithic integration of
InP and GaN on a single wafer that reduces interconnect
length without affecting device characteristics in comparison
to native substrate. FRAM wafer is used for Wafer on Wafer
(WOW) stacking with CMOS wafer by ultra-thinning
technology producing high density devices and shorter TSVs.

AND

GAN ON SI CMOS

A. For High Voltage III-N active device: GaN

The choice of GaN as a candidate for high voltage III- N
active device is based on the ability of GaN transistors to
operate at higher temperatures and work at higher voltages
than gallium arsenide (GaAs) transistors. They have wide
applications
in optoelectronics, high-power
and
highfrequency devices. The first step in our heterogeneous
integration of all the HGI device technologies is to grow GaN
HEMT epitaxial layer on silicon wafer in windows on
commercially available SOI wafers, where the Si <100>
handle wafer of traditional SOI is replaced by a highresistivity Si <111> substrate. This approach has already been
demonstrated with standard SOI wafers of 200mm (or greater)
diameter wafers that integrated advanced Si CMOS (120nm
or smaller) [7]. For the growth of GaN, Molecular Beam
Epitaxy (MBE) is preferred owing to the lower growth
temperature when compared with more standard metal organic
chemical vapour deposition (MOCVD). The MOCVD growth
temperature (approx. 1000C) leads to degradation of Si
CMOS device characteristics and hence should be avoided.
Figure 1 shows the schematic cross section that indicates that
the thickness of the GaN HEMT epi is chosen such that the top
of the GaN transistor is coplanar with the CMOS transistors.

Fig. 1. Schematic cross section of - GaNSi CMOS integration process. GaN

HEMTs are fabricated in windows on Si SOI wafer. [7]

This facilitate interconnect formation, however our

approach would involve at this step only the growth of 40 nm
GaN on silicon wafer as depicted in Figure 2 because we will
use this same wafer for the growth of InP. Hence, GaN is only
grown at this step by using selective window growth over a
specific area of substrate as per our requirements.
The main motivation to use this approach to fabricate GaN
was based on the results in [8] that depicted successful
implementation of 40 nm GaN amplifier heterogeneously
integrated with pMOS gate bias control circuitry reported in
[8] with GaN performing on an open channel current (Imax) of
1.1Amm1, a trans-conductance (gm) of 270mSmm1 and
good pinch-off characteristics. The RF power measurements
done also revealed that GaN HEMT in windows performed
similarly as GaN on SiC substrates and hence is very efficient

approach. This approach is also best suited for further

allowing HGI of InP on this same substrate as it allows a high
alignment accuracy and involves shared lithography steps,
thus minimizing the overall cost of batch processing.

Fig. 2. Step 1: Growth of GaN by selective window growth.

B. For High Speed III-V transistor: InP HBT

The choice of InP HBT as a candidate for high speed III-V
transistor is based on its wide range of applications in highspeed electronics such as Analog-to-Digital (A/D), Digital-toAnalog (D/A), fiber optic amplifiers and Voltage-Controlled
Oscillators (VCOs). The method, very much similar to a SiGe
BiCMOS to integrate InP HBT, involves integrating InP into
the Si CMOS process between the Si CMOS FEOL process
and BEOL interconnect process (Figure 3). However, as
device-quality (low defect/dislocation density) IIIV epilayers cannot easily be grown directly on Si substrates, the
direct integration approach is based on engineered silicon
substrates, which are a variant of standard silicon-on-insulator
(SOI) wafers. The starting substrate, known as silicon on
lattice-engineered substrate (SOLES), contains a buried IIIV
template layer which aids in the direct growth of high-quality
IIIV epitaxial material in windows grown directly on the
silicon substrate. As presented in [9], fabrication includes Ge
as the buried IIIV template layer, however we can use GaAs
or InP template layers as well for the substrate fabrication. The
importance of Ge as the template layer owes to (i) already
availability in Si foundries and hence a non-standard substrate
is not required in a Si foundry, and (ii) high-quality GaAs
buffer layers can easily be grown on Ge (almost a near-perfect
lattice match).

bipolar transistors (HBTs) and GaN high-electron-mobility

transistors (HEMTs)) with Si CMOS on a common siliconbased wafer using an integration/fabrication process similar to
a SiGe BiCMOS process (BiCMOS integrates BJT and CMOS
transistors).
This approach has resulted in a very high device-quality
InP HBT on a SOLES wafer of 200mm containing Si CMOS
exhibit gain (), ft and fmax of 40, more than 200GHz and more
than 200GHz, respectively used to implement f ully functional
high-speed InPSi CMOS differential amplifier and DAC
[10].
Based on the claim by recent patents US 8823146 and US
20140231870 [11, 12], the CMOS logic, InP and GaN device
characteristics are negligibly affected following the above
integration process for a wafer of 200 mm diameter.
Moreover, this approach with daisy chain test structure is
capable of supporting interconnect lengths and pitches of the
order of 1-2 micrometers with accordance of ITRS
specifications with the maximum flexibility and intimacy
(shortest interconnect length) [13]. We can optimize thickness
of the IIIV epitaxial layers and depth of the windows such
that the IIIV devices and CMOS transistors are coplanar.
Thus, to summarize our steps:
1.

A starting wafer comprising of a handle silicon substrate

with a <111> orientation to be used.
2. Selective growth of GaN over the substrate using the
process defined in 2.A monitored using selective window
growth over a specific area.
3. A silicon dioxide insulating layer over a selective portion
of the <111> substrate is deposited followed by silicon
<100> layer disposed over the insulating layer selectively
using windows monitoring growth over the wafer
escaping out the area where GaN is grown.
4. Si CMOS device fabrication over selective area of silicon
dioxide grown leaving area for InP growth.
5. Growth of template layer specific to the arear where InP
is to be grown followed by growth of InP.
Note that, the interconnection would be grown after WOW
method with FRAM memory wafer. This method has an
alignement accuracy of 1 micron and has high achievable
integration proximity of 5-6 micron [11,12].

Fig. 3. Schematic cross section of - InP HBTs are integrated with Si CMOS
using a IIIV BiCMOS process[9].

Therefore, in order to have a direct monolithic heterogeneous

integration of 250 nm InP, 40 nm GaN and Si-CMOS (120
nm), the Si wafer with GaN grown selectively over specific
part of the wafer (obtained from process defined in 2.a) can be
used in the above process of IIIV BiCMOS process to cofabricate CMOS and InP. This results in the successful
integration of IIIV electronic devices (InP heterojunction

Fig. 4. Step 2: Schematic cross section of showing growth of GaN followed

by CMOS and then InP HBTs using Ge template layer.

III. WOW TECHNOLOGY FOR CMOS LOGIC AND FRAM

MEMORY
The choice FRAM an acronym for ferroelectric

random access memory, is dictated by its ability

that combines the fast read and write access of
dynamic RAM (DRAM) with being non-volatile (the
ability to retain data when power is turned off)
and ultra-low power consumption when compared
to EEPROM and Flash. The FRAM based on a
capacitor stack of PZT can be grown with a CMOS
compatible process detailed in [14].
The wafer (200 mm dia) with CMOS logic, InP and GaN is
stacked on a FRAM wafer (200 mm dia with 64 or more level
stacking 16 bit devices provides terabyte of memory) using
wafer-on-wafer (WOW) stacking. The choice of WOW is
based on the rationale that it can be carried out with existing
facilities and results in high production and high device
densities with lower cost by simple multiplication of stacked
layers. It is known that wafer thickness affects ThroughSilicon-Via (TSV) aspect ratio and a thinner wafers resulting
in relaxed stress concentration in the TSVs allowing for better
high frequency operation [15]. Therefore, a solution is to use
ultra-thinning technology for wafers but it should be done
such that device characteristics should not undergo
degradation. In our approach to stack FRAM wafer on CMOS
wafer an optimization technique could be followed. Results in
[15] have shown that logic devices can be scaled down to 10
microns width without affecting device characteristics with
aspect ratio less than 4.
The process is done as shown in the Figure 5 where the second
wafer (FRAM wafer) in the stack is temporarily bonded onto
support glass, and the backside is ground and subsequently
treated to achieve a final thickness of 10 m or less.

Fig. 5. WOW Method for FRAM wafer and CMOS logic wafer [15].

Wafers are thinned-down from the backside using the Back

Grind process because removal rate can be adjusted relative to
the wafer thickness. Following the thinning using back
grinding (BG) process, wafers need to be polished using
surface treatment like Ultra-Poligrind processing, chemical
mechanical planarization or dry polishing. Finally, the WOWmethod results in the following hybrid system as shown in
Figure6.

Fig. 6. WOW Method for FRAM wafer and CMOS logic wafer

IV. MAJOR TECHNICAL CHALLENGES AND RISK

MITIGATION STRATEGIES

There are a few challenges in the above proposed HGI

technology. First of all, for the growth of high quality InP epi
layer in windows on Ge Template layer optimization of
nucleation and buffer layer to simultaneously minimize stress
is achieved by thicker strain relief buffer layers.
Also, the bulk of the non-crystalline layer in WOW
method may cause chip fracturing, may harbour
contaminants, and can affect device electrical
characteristics. Therefore, Ultra-Poligrind processing,
chemical mechanical planarization or dry polishing should be
done efficiently.
The InP MHEMT is not nearly co-planar with the other device
surfaces which complicates device processing. The thermal
resistance path for heat generated in the InP MHEMT to the
substrate is increased by the presence of the silicon layer and
SiO2 layer. The growth of III-V material such as the InP
MHEMT on a Si <100> surface is improved by tilting the
Si<100> surface several degrees. The CMOS process,
however, is developed on <100> silicon layers that are not
misoriented. [9] Tilting the silicon layer can alter the CMOS
process by changing the depths of implanted species.
The growth of III-V material such as MHEMT on a tilted
<100> silicon surface is improved by performing a high
temperature (900 C) anneal to form bilayer steps in the
surface. If bilayer steps are not formed, growth of a binary IIIV material on <100> elemental silicon results in antiphase
boundary defects.
A high temperature anneal could degrade the CMOS and
possibly the GaN HEMT present on the wafer. [16] Also as
there exits different metal layers, due to compatible
metallization issue, the problem of see-beck effect may arise
which should be take care of [17]. The thermal
conduction path (through thermal via) to
efficiently transport heat away from the highcurrent density InP HBTs can be further optimized
to fully exploit the performance of the InP
technology.
V. ADVANTAGES AND IMPACTS TO FUTURE HYBRID
SYSTEMS

The recommended HGI device technology has very

promising areas of applications ranging from intelligent
circuits (microsystems- and sensors-on-a-chip) to of microand nano-electronics. The key advantages are
High flexibility in functionality which would enable
this system to perform multiple applications;
Elimination of performance variations caused by
temperature drift and aging;
Enables tremendous savings of size, weight, power,
cost, and fabrication cycle time.
VI. CONCLUSION
The recommended heterogeneous integration of different
device technologies indicate that it promises to enable novel

advanced microsystems through the use of the best devices

and materials for each function in an integrated system and is
of significant value to high performance. Further due to
integration of all the devices on a single wafer the cost
decreases and hence, is cost effective.
REFERENCES
1. S. Deleonibus, " Physical and technological limitations of Nano CMOS
devices to the end of the roadmap and beyond", Eur. Phys. J. Appl. Phys. vol.
36, no. 3, pp. 197-214, Jan. 2007.
2. International Technology Roadmap for Semiconductor [www.itrs.net].
3. H. S. P. Wong, D. J. Frank, P. M. Solomon, C. H. J. Wann, J. J. Welser,
"Nanoscale CMOS", Proc. IEEE, vol. 87, no. 4, pp. 537-570, Apr. 1999.
4. L. R. Harriott, "Limits of Lithography", Proc. IEEE, vol. 89, no. 3, pp. 366374, Mar. 2001. [5] C. Cao and K. O. Kenneth, A 90-GHz voltage-controlled
oscillator with a 2.2-GHz tuning range in a 130-nm CMOS technology, in
Proc. Symp. VLSI Circuits Dig. Tech. Papers, 2005, pp. 242 243.
5.Gutierrez-Aitken A, et al. 2009 Advanced heterogeneous integration of InP
HBT and CMOS Si technologies for high performance mixed signal
applications. In IEEE MTT-S Int. Microwave Symposium Digest (MTT'09),
Boston, MA, 712 June, pp. 11091112. Piscataway, NJ: IEEE.
6. Li JC, et al. Heterogeneous wafer-scale integration of 250 nm, 300 GHz
InP DHBTs with a 130 nm RF-CMOS technology In IEEE Int. Electron
Devices Meeting (IEDM 2008), San Francisco, CA, 1517 December 2008,
pp. 944948. Piscataway, NJ: IEEE. 2008
7. Chen CL, et al. 2009 Wafer-scale 3D integration of InGaAs image sensors
with Si readout circuits. In IEEE Int. Conf. on 3D System Integration (3DIC
2009), San Francisco, CA, 2830 September, 4 pp. Piscataway, NJ: IEEE
8. Hoke, W. E. and Chelakara, et al.Monolithic integration of silicon CMOS
and GaN transistors in a current mirror circuit T., Journal of Vacuum Science
& Technology B, 30, 02B101 (2012),
9. Kazior, T.E.; Laroche, J.R.; Lubyshev, D.; Fastenau, J.M.; Liu, W.K.;
Urteaga, M.; Ha, W.; Bergman, J.; Choe, M.J.; Bulsara, M.T.; Fitzgerald,
E.A.; Smith, D.; Clark, D.; Thompson, R.; Drazek, C.; Daval, N.; Benaissa,
L.; Augendre, E., "A high performance differential amplifier through the direct
monolithic integration of InP HBTs and Si CMOS on silicon substrates," in
Microwave Symposium Digest, 2009. MTT '09. IEEE MTT-S International ,
vol., no., pp.1113-1116, 7-12 June 2009
10. Oyama, B.; Ching, D.; Khanh Thai; Gutierrez-Aitken, A.; Patel, V.J., "InP
HBT/Si CMOS-Based 13-b 1.33-Gsps Digital-to-Analog Converter With >
70-dB SFDR," in Solid-State Circuits, IEEE Journal of , vol.48, no.10,
pp.2265-2272, Oct. 2013
11. Hoke, W.E., "Generic Semiconductor structure having silicon devices,
column III-nitride devices, and column III-non-nitride or column II-VI
devices
http://www.google.com/patents/US8823146 ,2014 Google Patents
12. Hoke, W.E., "Generic Semiconductor structure having silicon devices,
column iii-nitride devices, and column iii-non-nitride or column ii-vi devices
http://www.google.com/patents/US20140231870 2014, Google Patents
13. Hussain, T.; Wheeler, D.C.; Sharifi, H.; Shinohara, K.; Zhiwei Xu; Li,
J.C.; Patterson, P.R.; Elliott, K.R.; Wonill Ha; Royter, Y.; Brewer, P.D.,
"Recent advances in monolithic integration of diverse technologies with Si

CMOS," in Silicon Monolithic Integrated Circuits in Rf Systems (SiRF), 2014

IEEE 14th Topical Meeting on , vol., no., pp.1-3, 19-23 Jan. 2014
14. Yamazaki, T.; Inoue, K.-i.; Miyazawa, H.; Nakamura, M.; Sashida, N.;
Satomi, R.; Kerry, A.; Katoh, Y.; Noshiro, H.; Takai, K.; Shinohara, R.; Ohno,
C.; Nakajima, T.; Furumura, Y.; Kawamura, S., "Advanced 0.5 /spl mu/m
FRAM device technology with full compatibility of half-micron CMOS logic
device," in Electron Devices Meeting, 1997. IEDM '97. Technical Digest.,
International , vol., no., pp.613-616, 10-10 Dec. 1997
15. Maeda, N.; Kim, Y.S.; Hikosaka, Y.; Eshita, T.; Kitada, H.; Fujimoto, K.;
Mizushima, Y.; Suzuki, K.; Nakamura, T.; Kawai, A.; Arai, K.; Ohba, T.,
"Development of ultra-thinning technology for logic and memory
heterogeneous stack applications," in 3D Systems Integration Conference
(3DIC), 2011 IEEE International , vol., no., pp.1-4, Jan. 31 2012-Feb. 2 2012
16. Schmid, H. te al. Template-assisted selective epitaxy of IIIV nanoscale
devices for co-planar heterogeneous integration with Si
Applied Physics Letters, 106, 233101 (2015).
17. Edwards, H.; Debord, J.; Tran, T.; Freeman, D.; Maggio, K., "Performance
metrics for thermoelectric energy harvesting studied using a novel planar 65
nm silicon CMOS-based thermopile," in SENSORS, 2013 IEEE , vol., no.,
pp.1-4, 3-6 Nov. 2013.

ACKNOWLEDGMENT
The author would like to thank UCLA for providing access
to publications in esteemed journals and conferences. The
author would also like to thank Prof. Chi On Chui, EE Dept.,
UCLA for giving an opportunity to have insightful learning
through this term paper and for the guidance in understanding
important aspects of 3D integration technology as part of the
classwork.

Madhuri Suthar (F91) is a PhD student at Electrical Engineering

Department, UCLA. She is currently working under Prof. Jalali at UCLA. She
has graduated in Electronics and Communication Engineering from Indian
School of Mines, Dhanbad in May, 2014 with an Institute Rank 1 in a batch of
950. Previously, she was working as a Project Research Assistant at Indian
Institute of Technology (IIT) Bombay on developing low power terabit/sec
interconnects for broadband communication links. She spent summer of 2013
at University of British Columbia working on continuous wave channel
sounder for high speed trains propagation environment. The test results were
presented in NSERC Diva Connected Vehicle Workshop at UBC. Her work
featured in an article in a Canadian newspaper. Her research interests are
Silicon Photonics, Optical Communication, optoelectronic devices and
microwave. She was recipient of prestigious O.P. Jindal Scholarship and
Directors Merit Award at Indian School of Mines Dhanbad for her excellent
academic results.