ANALOG

LAYOUT DESIGN
We work in collaboration with major
VLSI Companies for placement
 ABOUT
TAKSHILA VLSI
Takshila VLSI is among the top VLSI training
institutes in India. At Takshila, we understand
the changing demands in the field of VLSI. Our
courses are designed to offer students
hands-on experience in industry trends. We
focus on the overall growth and development
of the student. At Takshila, our courses are job
oriented and our trainers have over 15+ year’s
industry experience.

Since our inception, we have strived to remain among the best VLSI training insti-
tute. We do this through intensive training, affiliation with top-tier semiconductor
companies and effective placement programs. Our primary aim at Takshila is to
connect the student’s skill set with industry requirements. We have a very conducive
learning environment with modern facilities and tools. Our student’s excellent perfor-
mance in the field has continually ranked us the best VLSI institute in India.

TAKSHILA VLSI
UNIQUE FEATURES

Expert Trainers and Curriculum 100% Placement Support

We collaborate with trainers who have over 15+ years
in the industry. All our courses are professionally
designed and are job-oriented to satisfy the demands
of the VLSI industry. Our courses are designed and
delivered by Professionals in The Industry.
At Takshila VLSI technologies we provide placement
support for our students till they get placed. We
collaborate with over 200+ top-level semiconductor
companies that provide us with placement opportu
nities for our students.

Online/Offline Courses & Affordable Fee Powerful EDA Tools

Our online/offline VLSI courses are designed to ensure that
our students gain access to training materials and
classrooms at their convenience. We offer state-of-the-art
courses at very affordable prices. Our prices are very
affordable and competitive with monthly EMI facility.
We utilize industrial standard EDA tools for hands
-on training of our students. During your period
as a trainee in our VLSI institute, EDA tools are
accessible 24×7 through our vpn service.
ANALOG LAYOUT DESIGN
COURSE DESCRIPTION
Takshila VLSI’s Analog Layout Design course is designed to give
handson experience in designing the layout of a complex Analog
mixed signal chip’s block level to chip level layout. Course
focuses on giving intuitive understanding of Latch-up, Antenna
effect, EM&IR and different types of matching techniques. Course
curriculum is designed to enforce the student to continuous
practice of layout design of critical blocks such as Opamp, BGR,
LDO, VCO to make them suitable for jobs in semiconduc
tor industry.

LEARNING OUTCOME
Get handson experience in Analog layout design of Opamp,
BGR, LDO and VCO by executing industry standard live projects.

Gain deep knowledge in layout design concepts such as

Common centroid and inter-digitization matching techniques.
KEY COURSE FEATURES
Strong understanding of Latchup, Anatenna effect, EM&IR, LOD, 100% placement and tool support till placement is done.
STI and other device level effects.
24×7 tool access through vpn.
Learn to verify chip layout design using all physical verification
concepts and tools. Affordable fee and EMI facility.

Placements ready with improved soft skills and strong Analog Industry live projects under the supervision of 15+ experienced
fundamentals. trainer.

Course material, hand-outs, quizzes, assignments to assist in

TRAINER DETAILS learning.

Trainer has 12+ years of expertise in leading, mentoring Analog and 200+ LIST OF PLACEMENT
RFIC Layout teams in reputed multinational companies. He
worked on complex designs for Mobile and WLAN CHIP
COMPANIES
solutions. He has working experience in High Speed SerDes,
100% Assured Placement Assistance Till get placed.
PLL, TX, RX modules. He worked on Tech Nodes 5nm, 7nm,
65nm, 90nm, 120nm in TSMC and GF process. He is specialised Typical placement companies: Capgemini, L&T, HCL,
in AMS and RF Layout Design, Chip Tape outs and Full Chip Wipro, Cyient, Samsung, AMD, Synopsys, Tessolve, Micron,

Integration. Building, Mentoring and training new engineers.
COURSE LINK:
https://www.takshila-vlsi.com/course/analog-layout-design/
Synapse, Cerium, Einfochips, Wafer Space, UST Global,
KarMic, Mirafra, Eximius, Sankalp, Insemi, Si2chip, PerfectVIPs,
SeviTech, Open Silicon, Atria, Appex, Krisemi, Incise and many
more
For more info see: https://www.takshila-vlsi.com/placements/

ELIGIBILITY
DURATION: 4 Months
B.E/B.Tech/Diploma in EEE, ECE & EIE pursuing or completed.

M.E/M.Tech/M.S in VLSI/Embedded/Any other specialization

CONTACT INFO TOOLS & VPN

Cadence Virtuoso with 24x7 VPN access to tools
info@takshila-vlsi.com
MODE OF STUDY
+91- 97429 72744
Offline, Online – Daily and Weekends
COURSE CURRICULUM
S.No Module Name Sub-Modules
Module 1 Analog, Digital Electronics & MOSFET Analog Electronics
Theory Introduction to MOSFET theory and second order effects
Digital Electronics
Module 2 Introduction to CMOS Process and CMOS Fabrication Process
Circuits CMOS Circuits and Stick Diagrams
Module 3 Basics of Unix/Linux Introduction to Unix/Linux Commands
VI Editor Commands
Module 4 EDA Tool Introduction Introduction to Cadence Tool
DRC, LVS, ERC fixing using tool
Physical Verification
Module 5 Design for Manufacturability Checks Latch-up
Antenna Effect
Electro-migration (EM)
IR Drop & Self-Heat (SH)
Module 6 Deep sub-micron process challenges Shallow trench Isolation (STI)
Length of Diffusion (LOD)
Well proximity Effect (WPE)
Metal Density effects
ESD
Module 7 STD cell Layout design Techniques Critical signals shielding techniques
Basic STD cells understanding
NAND, NOR, AND, OR, INV1X & IV4X layout design
Module 8 Analog Layout Design Techniques Mismatch and Need for Matching
Matching Techniques Common centroid & Interdigitation
Guard / Seal Ring Techniques
Analog Design Layout considerations
Constraint & Module based Fullchip level floor planning techniques
Module 9 Industry standard Projects execution Layout Design & Physical Verification of Casdode Opamp
till tape-out Layout Design & Physical Verification of Flash ADC blocks
Layout Design & Physical Verification of Bandgap Reference
Layout Design & Physical Verification of LDO
Module 10 Memory Layout Design Concepts 6T Bit cell circuit theory and MEMORY architecture
ROW/COLUMN Decoder
Sense Amplifier & Precharge circuits theory
DRAM Basics
Module 11 FinFET Concepts Introduction and Process methods of FinFET
Process and reliability challenges
Module 12 Mock Interviews & Personality
Development