CSLA IMPLEMENTATION TECHNIQUE TO MINIMISE THE

AREA, POWER AND DELAY

A Project report submitted in partial fulfillment of the requirements for the
award of the degree of
MASTER OF TECHNOLOGY
IN
VLSI AND EMBEDDED SYSTEMS
BY
G. BHAGYA SRI (13MK1D6805)
Under the esteemed guidance of
Prof. P.BALA MURALI KRISHNA

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

SRI MITTAPALLI INSTITUTE OF TECHNOLOGY FOR WOMEN
(Approved by AICTE, New Delhi & Affiliated to JNTU, Kakinada)
NH-5, TUMMALAPALEM, GUNTUR-522233, A.P.
2013-2015

SRI MITTAPALLI INSTITUTE OF TECHNOLOGY FOR WOMENNH5,

THUMMALAPALEM, GUNTUR-522233, A.P(Approved by AICTE, New Delhi &
Affiliated to JNTU, Kakinada)

Department of
Electronics and Communication Engineering

CERTIFICATE
This is to certify that a project report entitled Implementation of efficient Multiplexer and
Multiplier Using MZI Technique being submitted by GUTTIKONDA BHAGYA SRI
bearing the roll number 13MK1D6805, in partial fulfilment of the requirements for the
award of the degree of Master of Technology in VLSI AND EMBEDDED SYSTEMS to
Jawaharlal Nehru Technological University, Kakinada, during the year 2014-2015 of SRI
MITTAPALLI INSTITUTE OF TECHNOLOGY FOR WOMEN, GUNTUR.

Prof. P. Bala Murali Krishna

G. Suseelamma

Project Guide

Head, Dept. of ECE

EXTERNAL EXAMINER

ACKNOWLEDGEMENTS

express

my

sincere

thanks

to

Sri

M.V.Koteswara

Rao,

Chairman,

and

Sri

M.B.V.Satyanarayana, Secretary and Correspondent of Sri Mittapalli Institute of Technology

for Women, Guntur for providing dexterities to carry out this project.
It gives us an honor to express my deep sense of gratitude and to our principal and project guide
Prof P. Bala Murali Krishna, Department of ECE, Sri Mittapalli Institute of Technology for
Women, Guntur for his valuable guidance, constant encouragement, and for every scientific and
personal concern throughout the course of investigation and successful completion of this work.
I wish to extend my sincere thanks to G. Suseelamma, Head of the Department of ECE, Sri
Mittapalli Institute of Technology for Women, Guntur for her constant support, encouragement
and enabling us to do a work of this magnitude.
Our sincere thanks to teaching and non teaching staff members of ECE, Sri Mittapalli Institute of
Technology for Women, Guntur.
Lastly I bow to my affectionate Parents for their love and blessings, which has sustained me a lot
in completing this project work successfully.

BY
G.BHAGYA SRI
(13MK1D6805)

CONTENTS
Page No:
ABSTRACT

LIST OF FIGURES

II

LIST OF TABLES

III

CHAPTER 1: INTRODUCTION
1.1 Introduction to VLSI

1.2 Objective

1.3 Existing system

1.3.1 Existing System Disadvantages

1.4 Proposed system

1.5 Project Outline

CHAPTER 2: LITERATURE REVIEW

10

CHAPTER 3: PROPOSED CONCEPT

3.1 Logic Formulation

30

3.1.1 Logic Expressions of the SCG Unit of the Conventional CSLA

31

3.1.2 Logic Expression of the SCG Unit of the BEC-Based CSLA

31

3.2 Proposed Adder Design

33

3.3 Analysis of Adders

37

3.4 Extension Concept of Multistage CSLA (SQRT-CSLA)

38

CHAPTER 4: SIMULATION AND SYNTHESIS RESULT ANALYSIS

4 .1 Simulation Result

40

4.1.1 32-bit Ripple Carry Adder

40

4.1.2 16 bit of proposed concept

40

4.1.3 Results of 32 bit proposed adders

41

4.1.4 Performance Comparison

41

4.2 Synthesis Report

43

4.3 Applications

44

4.4 Advantages

44

CHAPTER 5: CONCLUSION AND FUTURE SCOPE

45

5.1 CONCLUSION

45

5.2 Future Scope

45

REFERENCES

46

ABSTRACT
With the advancements in semiconductor technology, there has been an increased
emphasis in low-power design techniques over the last few decades. Reversible computing has
been proposed by several researchers as a possible alternative to address the energy dissipation
problem. This paper describes the design of Mach Zehnder Interferometer and reviews its
applications in emerging optical communication networks. Mach Zehnder Interferometer is
basically used to measure relative phase shift between two collimated beams from a coherent
light source. Using this basic principle a number of devices can be designed, few of these such as
optical sensors, all-optical switches, optical add-drop multiplexer and implementation of sum
function are discussed in this paper.

LIST OF FIGURES
NAME OF THE FIGURE

PAGENO

Fig.1 Delay and Area evolution of regular SQRT CSLA

11

Fig.2.2 Block Diagram of regular CSLA

18

Fig.2.3 Block diagram of modified CSLA

19

Fig.2.4 The 5-bit Binary to Excess-1 code converter

20

(a) BEC (Without carry)

(b) BECWC (With Carry)
Fig.3.1 (a) Conventional CSLA; n is the input operand bit-width

30

(b) The logic operations of the RCA

Fig.3.2. Structure of the BEC-based CSLA; n is the input operand bit-width

32

Fig. 3.3 (a) Proposed CS adder design

33

(b) Gate-level design of HSG

(c) Gate-level optimized design of (CG0) for input-carry= 0
(d) Gate-level optimized design of (CG1) for input-carry= 1
(e) Gate-level design of the CS unit
(f) Gate-level design of the final sum generation (FSG) unit
Fig.3.4 A 4-bit Ripple Carry Adder

35

Fig.3.5: A Carry Select Adder with 1 level using n/2- bit RCA

36

Fig.3.6: .3 4-BIT CLA Logic equations

36

Fig. 3.7: Proposed SQRT-CSLA for n = 16

39

Fig.4.1: 32-bit ripple carry adder

40

Fig.4.2: 16 bit of proposed concept

40

Fig.4.3: Results of 32 bit proposed adders

41
II

LIST OF TABLES
NAME OF THE TABLE

PAGENO

Table 2.1: Delay and area count of regular SQRT CSLA

12

Table 2.2: Delay and area count of Modified SQRT CSLA

12

Table 2.3: Truth table for binary to excess-1 converter

20

Table 2.4: Functional table of the 4-bit BEC

23

Table 2.5: Categorization of adders w.r.t delay time and capacity

25

Table 3.1: Theoretical Comparison of Area Occupied (Ax)

37

Table 3.2: Theoretical Comparison of Time Required (T)

38

Table 3.3: Theoretical Area Delay Product (AxT)

38

Table 3.4: Comparison of Time Required (Simulated Value)

38

Table 4.1: Path delays comparison

42

Table 4.2: Comparison of the Regular and Modified SQRT CSLA

42

Table 4.3: Theoretical Estimation

43

Table 4.4: Design Summary

43

Table 4.5: Comparison of post layout- synthesis result

44

III