www.ti.

com

TLV5619
www.ti.com

SLAS172F DECEMBER 1997 REVISED FEBRUARY 2004

These devices have

REFIN

D0

12

+
_

19
20

D1
1
D2
2
D3
3
D4
4
D5
5
D6
6
D7
7
D8
8
D9
9
D10
10
D11

18
CS
WE

17

Resistor
String DAC
12
12-Bit
DAC
Latch

12-Bit
Input
Register

Power-On
Reset

Select
and
Control
Logic
15
PD

12

16
LDAC

x2

13

OUT

TLV5619
www.ti.com

SLAS172F DECEMBER 1997 REVISED FEBRUARY 2004

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted) (1)
UNIT
Supply voltage (VDD to GND)

7V

Analog input voltage range

- 0.3 V to VDD + 0.3 V

Reference input voltage

VDD + 0.3 V

Digital input voltage range to GND

Operating free-air temperature range, TA

- 0.3 V to VDD + 0.3 V

TLV5619C

0C to 70C

TLV5619I

-40C to 85C

TLV5619Q

-40C to 125C

Storage temperature range, Tstg

-65C to 150C

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds

(1)

260C

Stresses beyond those listed under,, absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under,, recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

MIN

NOM

MAX

Supply voltage, VDD (5-V Supply)

4.5

5.5

Supply voltage, VDD (3-V Supply)

2.7

3.3

High-level digital input voltage, VIH

DVDD = 2.7 V

DVDD = 5.5 V

2.4

DVDD = 2.7 V
Low-level digital input voltage, VIL

DVDD = 5.5 V

0.6
TLV5619C and TLV5619I

TLV5619Q

0.8

Reference voltage, Vref to REFIN terminal (5-V Supply)

2.048

VDD-1.5

Reference voltage, Vref to REFIN terminal (3-V Supply)

1.024

VDD-1.5

Load resistance, RL

10

Load capacitance, CL
Operating free-air temperature, TA

UNIT

V
V
k

100
TLV5619C

70

TLV5619I

40

85

TLV5619Q

40

125

pF
C

TLV5619
SLAS172F DECEMBER 1997 REVISED FEBRUARY 2004

www.ti.com

ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range, sdupply voltages, and reference voltages (unless otherwise noted)

TLV5619
www.ti.com

SLAS172F DECEMBER 1997 REVISED FEBRUARY 2004

REFERENCE INPUT (REFIN)

PARAMETER
Vref

Reference input voltage

Ri

Reference input resistance

Ci

Reference input capacitance

TEST CONDITIONS
See

TYP

REFIN = 1 Vpp at 1 kHz + 1.024 V dc (see

Reference input bandwidth

REFIN = 0.2 Vpp + 1.024 V dc at -3 dB

(2))

MAX
VDD-1.5

10

Reference feed through

TIMING REQUIREMENTS

MIN

(1)

UNIT
V
M

pF

60

dB

1.4

TLV5619
www.ti.com

SLAS172F DECEMBER 1997 REVISED FEBRUARY 2004

PARAMETER MEASUREMENT INFORMATION

D(011)

Data

tsu(D)

th(D)

CS
tsu(CE-WE)

twh(WE)

WE
tsu(WE-LD)

LDAC

Figure 1. Timing Diagram

tw(LD)

TLV5619
www.ti.com

SLAS172F DECEMBER 1997 REVISED FEBRUARY 2004

TYPICAL CHARACTERISTICS
MAXIMUM OUTPUT VOLTAGE
vs
LOAD

MAXIMUM OUTPUT VOLTAGE

vs
LOAD

3
VDD = 5 V, Vref = 2 V,
Input Code = 4095

VDD = 3 V, Vref = 1.2 V,

Input Code = 4095
2.5
VO Output Voltage V

VO Output Voltage V

1.5

1
100 k

10 k
1k
100
RL Output Load

10

Figure 2.

0.5
100 k

10 k
1k
100
RL Output Load

Figure 3.

TOTAL HARMONIC DISTORTION

vs
LOAD
0
THD Total Harmonic Distortion dB

VDD = 5 V, Vref = 2 V,
Tone at 1 kHz
20

40

60

80

100
100 k

10 k
1k
100
RL Output Load

Figure 4.

10

Figure 5.

10

www.ti.com

SIGNAL-TO-NOISE + DISTORTION
vs
FREQUENCY
SNRD Signal-To-Noise Ratio + Distortion dB

80
VDD = 5 V
70
60
50
40
30
20
10
0
0

10

15

20

25

f Frequency kHz

30

35

TLV5619
www.ti.com

SLAS172F DECEMBER 1997 REVISED FEBRUARY 2004

TYPICAL CHARACTERISTICS (continued)

POWER DOWN SUPPLY CURRENT
vs
TIME
1

I DD Supply Current mA

0.1

0.01

0.001

0.0001

0.00001

0.000001
0

100

200

300

400

500

600

t Time ms

Figure 9.

TLV5619
SLAS172F DECEMBER 1997 REVISED FEBRUARY 2004

www.ti.com

APPLICATION INFORMATION
DEFINITIONS OF SPECIFICATIONS AND TERMINOLOGY
Integral Nonlinearity (INL)
The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum
deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale
errors.
Differential Nonlinearity (DNL)
The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the
measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage
changes in the same direction (or remains constant) as a change in the digital input code.
Zero-Scale Error (EZS)
Zero-scale error is defined as the deviation of the output from 0 V at a digital input value of 0.
Gain Error (EG)
Gain error is the error in slope of the DAC transfer function.
Signal-to-Noise Ratio + Distortion (S/N+D)
S/N+D is the ratio of the rms value of the output signal to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels.
Spurious Free Dynamic Range (SFDR)
SFDR is the difference between the rms value of the output signal and the rms value of the largese
Total Harmonic Distortion (THD)

TLV5619
www.ti.com

SLAS172F DECEMBER 1997 REVISED FEBRUARY 2004

APPLICATION INFORMATION (continued)

LINEARITY, OFFSET, AND GAIN ERROR SUING SINGLE END SUPPLIES
When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With
a positive offset, the output voltage changes on the first code change. With a negative offset the output voltage
may not change with the first code depending on the magnitude of the offset voltage.
The output amplifier attempts to drive the output to a negative voltage. However, because the most negative
supply rail is ground, the output cannot drive below ground and clamps the output at 0 V.
The output voltage remains at zero until the input code value produces a sufficient positive output voltage to
overcome the negative offset voltage, resulting in the transfer function shown in Figure 10.

Output
Voltage

0V
Negative
Offset

DAC Code

Figure 10. Effect of Negative Offset (Single Supply)

This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the
dotted line if the output buffer could drive below the ground rail.

For a DAC, linearity is measured between zero input code (all inputs 0) and full scale code (all inputs 1) after
offset and full scale at6 0 1 278.110 T42106f1 0 0 1 54 5 191.49 193.8 Tm 82.06 421.4 Tm(am(tr10 T42106 118.92 421.4 Tm.

GENERAL FUNCTION

2 REF CODE [V]

0x1000

TLV5619
www.ti.com

SLAS172F DECEMBER 1997 REVISED FEBRUARY 2004

PARALLEL INTERFACE

TMS320C2XX, 5X
A(015)
TLV5619
IS

Address
Decoder

CS
LDAC

WE

WE
D(011)

D(015)

TMS320C3X
A(015)
TLV5619
Address
Decoder
TCLK0

CS
LDAC

R/W
WE
IOSTROBE
D(011)

D(015)

TLV5619
www.ti.com

SLAS172F DECEMBER 1997 REVISED FEBRUARY 2004

APPLICATION INFORMATION (continued)

TLV5619 INTERFACED TO TMS320C203 DSP
Hardware Interface

Figure 13 shows an example of the connection between the TLV5619 and the TMS320C203 DSP. The only
other device that is needed in addition to the DSP and the DAC is the 74AC138 address decoding circuit . Using
this configuration, the DAC address is 0x0084 within the I/O memory2j11 01 0 0 1 362.2j1F1 786.65 159.j1F1 786.651.78.65 1

Software

TLV5619
SLAS172F DECEMBER 1997 REVISED FEBRUARY 2004

APPLICATION INFORMATION (continued)

SOFTWARE LISTING
; File: ramp.asm
; Description: This program generates a ramp.
;------------- I/O and memory mapped regs ----------.include "regs.asm"
TLV5619
.equ
0084h
;------------- vectors ------------------------------.ps
0h
b
start
b
INT1
b
INT23
b
TIM_ISR
*********************************************************************
* Main Program
*********************************************************************
.ps
1000h
.entry
start:
ldp
; disable interrupts
setc
splk
splk

#0

; set data page to 0

INTM ; disable maskable interrupts

#0ffffh, IFR
#0004h,
IMR

; set up the timer

splk
splk
out
out
splk
out

#0000h,
#0042h,
61h. PRD
60h, TIM
#0c2fh,
62h, TCR

; enable interrupts
clrc

INTM ; enable maskable interrupts

60h
61h

62h

; loop forever!
next
idle
; wait for interrupt
b
next
; all else fails stop here
done
b
done ; hang there
*********************************************************************
* Interrupt Service Routines
*********************************************************************
INT1:

ret

; do nothing and return

INT23:

ret

; do nothing and return

TIM_ISR:
; useful code
add
#1h ; increment accumulator
sacl
60h
14

www.ti.com

TLV5619
www.ti.com

SLAS172F DECEMBER 1997 REVISED FEBRUARY 2004

APPLICATION INFORMATION (continued)

out
clrc
ret
.end

60h, TLV5619 ; write to DAC

intm; re-enable interrupts
; return from interrupt

15

PACKAGE OPTION ADDENDUM

www.ti.com

6-Jan-2013

PACKAGING INFORMATION
Orderable Device

Status
(1)

Package Type Package Pins Package Qty

Drawing

Addendum-Page 1

Eco Plan
(2)

PACKAGE OPTION ADDENDUM

www.ti.com

6-Jan-2013

Orderable Device

Status
(1)

Package Type Package Pins Package Qty

Drawing

TLV5619QDWG4

ACTIVE

SOIC

DW

20

TLV5619QDWR

OBSOLETE

SOIC

DW

20

TLV5619QDWRG4

ACTIVE

SOIC

DW

20

Eco Plan

Lead/Ball Finish

MSL Peak Temp

Samples

(3)

(Requires Login)

(2)

25

Green (RoHS
& no Sb/Br)

CU NIPDAU

TBD

Call TI

2000

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM
Call TI
Level-1-260C-UNLIM

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLV5619 :

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

6-Jan-2013

Enhanced Product - Supports Defense, Aerospace and Medical Applications

Addendum-Page 3

PACKAGE MATERIALS INFORMATION

www.ti.com

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

TLV5619CDWR

SOIC

TLV5619CPWR
TLV5619IDWR
TLV5619IPWR

SPQ

Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)

B0
(mm)

K0
(mm)

P1
(mm)

W
Pin1
(mm) Quadrant

13.3

2.7

12.0

24.0

Q1

DW

20

2000

330.0

24.4

10.8

TSSOP

PW

20

2000

330.0

16.4

6.95

7.1

1.6

8.0

16.0

Q1

SOIC

DW

20

2000

330.0

24.4

10.8

13.3

2.7

12.0

24.0

Q1

TSSOP

PW

20

2000

330.0

16.4

6.95

7.1

1.6

8.0

16.0

Q1

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jan-2013

*All dimensions are nominal

Device

Package Type

Package Drawing

Pins

SPQ

Length (mm)

Width (mm)

Height (mm)

TLV5619CDWR

SOIC

DW

20

2000

367.0

367.0

45.0

TLV5619CPWR

TSSOP

PW

20

2000

367.0

367.0

38.0

TLV5619IDWR

SOIC

DW

20

2000

367.0

367.0

45.0

TLV5619IPWR

TSSOP

PW

20

2000

367.0

367.0

38.0

Pack Materials-Page 2

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