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The Effect of The Inversion Channel at The Aln/Si Interface On The Vertical Breakdown Characteristics of Gan-Based Devices
The Effect of The Inversion Channel at The Aln/Si Interface On The Vertical Breakdown Characteristics of Gan-Based Devices
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The effect of the inversion channel at the AlN/Si interface on the vertical breakdown
characteristics of GaN-based devices
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2014 Semicond. Sci. Technol. 29 115012
(http://iopscience.iop.org/0268-1242/29/11/115012)
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IP Address: 14.139.211.71
This content was downloaded on 06/12/2014 at 08:57
doi:10.1088/0268-1242/29/11/115012
E-mail: yacoub@gan.rwth-aachen.de
Received 23 May 2014, revised 18 July 2014
Accepted for publication 28 July 2014
Published 3 September 2014
Abstract
GaN-on-Si transistors attract increasing interest for power applications. However, the breakdown
behavior of such devices remains below theoretical expectations, for which the Si substrate is
typically made responsible. In this work, the effect of the thickness of an aluminum nitride buffer
layer on the vertical breakdown voltage, measured relative to a grounded silicon substrate, has
been investigated. A voltage-polarity-dependent breakdown mechanism has been observed. It
has been found that the breakdown in the positive bias voltage regime is initiated by carrier
injection, for which the carriers originate from an inversion channel formed between the epitaxial
layers and the p-silicon substrate. TCAD simulations have conrmed the proposed explanations,
and suggest that appropriate modication of the electronic structure at the AlN/silicon interface
could signicantly improve the vertical breakdown voltage.
Keywords: vertical breakdown, GaN-on- Silicon, inversion channel, asymmetric breakdown
(Some gures may appear in colour only in the online journal)
1. Introduction
H Yacoub et al
A). Shown are average values and standard deviation from several
measurements. Inset showing IV measurements on the 1 m thick
AlN samples
particular, we demonstrate that the inversion channel formation is responsible for the breakdown at the positive bias.
For the study of the AlN/Si interface a 20 nm thick AlN
nucleation layer was deposited on p-Si at 930 C after thermal
oxide removal (gure 1, structure B), AFM measurements
were done for the samples, giving a surface roughness RMS
of 1.1 nm, which is a clear indication that a closed layer is
grown. After local removal of the AlN, ohmic contacts were
deposited creating contact to the AlN/Si interface and the
silicon substrate simultaneously, thus forming van der Pauw
structures for conductivity and Hall measurements. The same
ohmic contacts were fabricated on bare silicon substrates for
the sake of Hall measurements calibration. Additionally, a Ni/
Au contact was deposited on top of the AlN as a Schottky
contact for capacitancevoltage (CV) measurements. Buffer
breakdown measurements on epitaxial structures were performed, in addition, Hall, CV and temperature-dependent
IV measurements were excuted on the 20 nm AlN nucleation
samples. All measurements were carried out with the silicon
substrate held at ground potential.
2. Experiment
All samples were grown in a planetary hot-wall metal-organic
vapor phase epitaxy (MOVPE) research system in a 10 2inch wafer conguration using standard precursors and carrier
gases. To remove any residuals from the reactor chamber, a
high-temperature bake (T = 1450 C) was performed before
every run. The native oxide of the p-type silicon substrate
(boron doped RSheet = 265 sq1) was removed by a thermal cleansing step at 920 C for 10 min under hydrogen
ambient and a pressure of 50 mbar. Afterwards, the temperature was raised to 970 C for AlN nucleation layer
(27 nm) growth, which was initiated by a short Al (TMAl)
pre-ow. The AlN buffer was divided into two sub-layers,
whereas the rst 240 nm were grown at a high V/III ratio and
the second at a low V/III ratio. The thickness of the second
sub-layer was adjusted to obtain total AlN thicknesses of
0.5 m, 1 m and 1.5 m, respectively. A 0.85 m thick Al
0.25Ga 0.75N layer was deposited on the HT-AlN buffer, followed by a 1.4 m thick GaN buffer, a 1 nm AlN spacer and a
28 nm Al 0.25Ga 0.75N barrier, (gure 1, sample structure A).
Deep mesa structures (of about 2.5 m) were etched
using a BCl3-based RIE process. Afterwards, Ti-Al-Ni-Au
ohmic contacts were evaporated and annealed at 830 C in
nitrogen atmosphere. Currentvoltage measurements were
carried out, for which positive and negative voltages were
applied to the top ohmic contact while contacting the silicon
substrate to ground via a highly conducting backside contact
(gure 1, structure A).
Currentvoltage characteristics in positive and negative
bias region were recorded to investigate the symmetry of the
current transport in the full structure. The breakdown voltage
was determined for both bias polarities, dened at a current
density of 1 A cm2 .
H Yacoub et al
qE
Jo =
R sh =
[10] .
kBT
To investigate the transport in more detail in the positive
regime, temperature-dependent IV measurements were performed on the sample structure A. Figure 4 shows the current
density versus the square root of the electric eld for different
temperatures from room temperature to 423 K. From the
Arrhenius plot of Jo found as the extrapolated y-axis intercept,
the emission barrier for PooleFrenkel transport was found to
be 0.68 eV. With PooleFrenkel mechanism dominating the
positive breakdown current, the source of the injected carriers
q pp + nn
RH =
pp2 nn2
q pp + nn
(1)
(2)
H Yacoub et al
coefcient. For the substrate hole mobility p and hole concentration p, the Hall results of sample C were inserted in
equation(1) & (2), and solved for electron carrier concentration n and mobility n according to:
nn2 = pp2
RH
qR sh2
(3)
and
nn =
1
p p
qR sh
(4)
With the corrections for the p-substrate measurements contribution, the Hall measurement results from sample B reveal
an electron channel at the interface with a temperature-independent density of about 3 1013 cm2 , and a mobility which
is slightly decreasing from 77 K to room temperature
(gure 5). This indicates a polarization-induced 2DEG
between the AlN and silicon substrate [13, 14].
4. Simulation
3.3. CV measurements
H Yacoub et al
References
[1] Selvaraj S, Watanabe A, Wakejima A and Egawa T 2012 1.4kV breakdown voltage for AlGaN/GaN high-electronmobility transistors on silicon substrate IEEE Electron
Device Lett. 33 13757
[2] Rowena I, Selvaraj S and Egawa T 2011 Buffer thickness
contribution to suppress vertical leakage current with high
breakdown eld (2.3 MV cm1) for GaN on Si IEEE
Electron Device Lett. 32 15346
[3] Hahn H, Benkhelifa F, Ambacher O, Alam A, Heuken M,
Yacoub H, Noculak A, Kalisch H and Vescan A 2013 GaNon-Si enhancement mode metal insulator semiconductor
heterostructure eld effect transistor with on-current of
1.35 A mm1 Japan. J. Appl. Phys. 52 090204
[4] Wr J, Bahat-Treidel E, Brunner F, Cho M, Hilt O, Knauer A,
Kotara P, Krueger O, Weyers M and Zhytnytska R 2013
Device breakdown and dynamic effects in GaN power
switching devices: Dependencies on material properties and
device design ECS Trans. 50 21122
5. Conclusion
In this work we have provided the rst direct experimental
proof for the existence of an inversion channel at the AlN/Si
interface, which is shown to be detrimental for the vertical
breakdown characteristics of GaN-on-Si structures.
5
H Yacoub et al