Compal Confidential Schematics for AMD S1G4/RS880M/SB820M Mobile Platform

A
Compal confidential
LC-Marseille 10AD
PWWAE LA-6843P Schematics Document

Mobile AMD S1G4/ RS880M / SB820M
3
2010-08-16 Rev. 1.0
Compal Secret Data
Security Classification
2010-08-25
Issued Date
2010-08-25
Deciphered Date
Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
SCHEMATICS,MB A6843
Rev
B
401982
Sheet
Wednesday, September 01, 2010

E
of
40
Compal Confidential
Thermal Sensor
ADM1032ARMZ
Model Name : PWWAA
Fan Control
page 5
page 7
AMD S1G4 CPU
Memory BUS(DDRIII)
Dual Channel
uFCPGA-638 Package
1.5V DDRIII 1066/1333MHZ
File Name : LA-6843P
200pin DDRIII-SO-DIMM X2
page 9,10
BANK 0, 1, 2, 3
page 5,6,7,8
Hyper Transport Link 2.6GHz

16X16
RTL8105E 10/100M
RJ45
PCIe port 3
page 24
page 24
AMD
CRT
page 16
RS880M
PCIe 4x
LCD Conn.
1.5V 2.5GHz(250MB/s)
page 17
WLAN
PCIe port 2
page 23
page 11,12,13,14,15
LAN
2
PCIe port 3
page 24
A-Link Express II
4X PCI-E
IO/B-- USB Right
USB port 0,1
page 23
USB
Card Reader
USB port 5
page 25
Int. Camera
SATA port 0
5V 480MHz
5V 1.5GHz(150MB/s)
AMD
USB port 9
page 17
SATA port 1
5V 1.5GHz(150MB/s)
SB820M
WLAN
SATA HDD
page 23
SATA ODD
page 23
USB
USB port 8
page 27
5V 480MHz
page 18,19,20,21,22
RTC CKT.
3.3V 33 MHz
LPC BUS
HD Audio
3.3V/1.5V 24MHz
HDA Codec
ALC259
page 26
Debug Port
Power On/Off CKT.

page 30
ENE KB926 E0
page 29
page 28
Power/B
Int.
MIC CONN
page 17
page 30
DC/DC Interface CKT.
Touch Pad
page 30
page 31
Int.KBD
page 29
MIC CONN
page 27
HP CONN
page 27
SPK CONN
page 27
EC ROM
page 29
Power Circuit DC/DC

4
page 31,32,33,34,35
36,37,38,39
Compal Secret Data
2010-08-25
Issued Date
2010-08-25
Deciphered Date
Title
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Date:
SCHEMATICS,MB A6843
Rev
B
401982
Sheet
E
of
40
DESIGN CURRENT 0.1A
+3VL
DESIGN CURRENT 0.1A
+5VL
DESIGN CURRENT 1A
+3VALW
DESIGN CURRENT 3.5A
+5VALW
B+
RT8205EGQW
SUSP
N-CHANNEL
SI4800
DESIGN CURRENT 2A
+5VS
DESIGN CURRENT 330mA
+3V_LAN
DESIGN CURRENT 1.5A
+3VS
DESIGN CURRENT 1A
+LCD_VDD
DESIGN CURRENT 300mA
+2.5VS
DESIGN CURRENT 2.5A
+1.8VS
DESIGN CURRENT 0.3A
+1.1VALW
DESIGN CURRENT 3.5A
+1.1VS
DESIGN CURRENT 6A
+NB_CORE
DESIGN CURRENT 18A
+CPU_CORE0
DESIGN CURRENT 18A
+CPU_CORE1
DESIGN CURRENT 4A
+VDDNB
DESIGN CURRENT 5A
+1.5V
DESIGN CURRENT 1A
+1.5VS
DESIGN CURRENT 1A
+0.75VS
DESIGN CURRENT 1.5A
+1.05VS
WOL_EN#
P-CHANNEL
AO-3413
SUSP
N-CHANNEL
SI4800
ENVDD
P-CHANNEL
AO-3413
APL5508
PWWAE LC-Marseille AMD
SUSP#
MP2121DQ
POK
RT8209BGQW
VLDT_EN#
N-CHANNEL
IRF8113
VLDT_EN#
N-CHANNEL
IRF8113
VR_ON
B
ISL6265A
SYSON
RT8209BGQW
SUSP
N-CHANNEL
IRF8113
SUSP
APL5331KAC
VR_ON#
APL5331KAC
Compal Secret Data
2010-08-25
Issued Date
2010-08-25
Deciphered Date
Title
Date:
SCHEMATICS,MB A6843
Rev
B
401982
Sheet

1
of
40
Voltage Rails
Platform
O : ON
CPU
NB
S1G4
Danube
X : OFF
VGA
RS880M
NA
SB
Comment
SB820M
+5VS
1
+3VS
power
plane
+1.8VS
+1.5VS
State
+B
+5VALW
+3VL
+3VALW
+5VL
+1.1VALW
+1.1VS
+1.5V
+1.05VS
+0.75VS
+VGA_CORE
+RTCVCC
+VDDNB
+CPU_CORE
S0
S1
@ : just reserve , no build

SB820MR1@ : just reserve for SB820MR1 only
R3@ : just reserve for R3 only
CONN@ : just reserve for Connector only
CAM@ : just reserve for WebCam only
BT@ : just reserve for Blue Tooth only
880MR1@: just reserve for 880MR1 only
8105E_VC@: just reserve for 10/100 LAN VC version only
8105E_VB@: just reserve for 10/100 LAN VBversion only
+2.5VS
BTO (Build-To-Order)
Option Table
S3
S5 S4/AC
Function
Camera
Description
S5 S4/ Battery only
S5 S4/AC & Battery

don't exist
(C)
Explain
CAM@
BTO
SMBUS Control Table

3
I2C / SMBUS ADDRESSING

DEVICE
HEX
SOURCE
ADDRESS
DDR SO-DIMM 0
A0
10100000
DDR SO-DIMM 1
A2
10100010
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
DDC_CLK0
EC SM Bus2 address
HEX
Address
Device
Smart Battery
16H
0001 011X b
EMC1032-1 CPU 98H
EC KB926E0
HEX
DDC_DATA0
SCL0
Address
SDA0
1001 100X b
SCL1
EC KB926E0
SDA1
KB926
SODIMM
I / II
CLK
GEN
WLAN
LCD
DDC
ROM
KB926
RS880M
I2C_DATA
Device
CPU
THERMAL
SENSOR
EC_SMB_CK1
I2C_CLK
EC SM Bus1 address
BATT
RS880M
SB820
SB820
Compal Secret Data
2010-08-25
Issued Date
2010-08-25
Deciphered Date
Title
Date:
SCHEMATICS,MB A6843
Rev
B
401982
Sheet

E
of
40
+1.1VS
250 mil
1
VLDT CAP.
1
C1
10U_0805_10V6K
Near CPU Socket

1
C2
10U_0805_10V6K
C3
0.22U_0603_16V4Z
C4
0.22U_0603_16V4Z
C5
180P_0402_50V8J
C6
180P_0402_50V8J
<11> H_CADIP[0..15]
<11> H_CADIN[0..15]
H_CADIP[0..15]
H_CADOP[0..15]
H_CADIN[0..15]
H_CADON[0..15]
H_CADOP[0..15]
<11>
H_CADON[0..15]
<11>
+1.1VS
+1.1VS
JCPUA
VLDT=500mA
< From NB >
H_CADIP0
H_CADIN0
H_CADIP1
H_CADIN1
H_CADIP2
H_CADIN2
H_CADIP3
H_CADIN3
H_CADIP4
H_CADIN4
H_CADIP5
H_CADIN5
H_CADIP6
H_CADIN6
H_CADIP7
H_CADIN7
H_CADIP8
H_CADIN8
H_CADIP9
H_CADIN9
H_CADIP10
H_CADIN10
H_CADIP11
H_CADIN11
H_CADIP12
H_CADIN12
H_CADIP13
H_CADIN13
H_CADIP14
H_CADIN14
H_CADIP15
H_CADIN15
HT LINK
D1
D2
D3
D4
VLDT_A0
VLDT_A1
VLDT_A2
VLDT_A3
E3
E2
E1
F1
G3
G2
G1
H1
J1
K1
L3
L2
L1
M1
N3
N2
E5
F5
F3
F4
G5
H5
H3
H4
K3
K4
L5
M5
M3
M4
N5
P5
L0_CADIN_H0
L0_CADIN_L0
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H15
L0_CADIN_L15
VLDT_B0
VLDT_B1
VLDT_B2
VLDT_B3
AE2
AE3
AE4
AE5
L0_CADOUT_H0
L0_CADOUT_L0
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H15
L0_CADOUT_L15
AD1
AC1
AC2
AC3
AB1
AA1
AA2
AA3
W2
W3
V1
U1
U2
U3
T1
R1
AD4
AD3
AD5
AC5
AB4
AB3
AB5
AA5
Y5
W5
V4
V3
V5
U5
T4
T3
H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADOP2
H_CADON2
H_CADOP3
H_CADON3
H_CADOP4
H_CADON4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7
H_CADOP8
H_CADON8
H_CADOP9
H_CADON9
H_CADOP10
H_CADON10
H_CADOP11
H_CADON11
H_CADOP12
H_CADON12
H_CADOP13
H_CADON13
H_CADOP14
H_CADON14
H_CADOP15
H_CADON15
C7
2 10U_0805_10V6K
< VLDT_A & VLDT_B : HyperTransport I/O ring power >
< To NB >
<11>
<11>
<11>
<11>
H_CLKIP0
H_CLKIN0
H_CLKIP1
H_CLKIN1
J3
J2
J5
K5
L0_CLKIN_H0
L0_CLKIN_L0
L0_CLKIN_H1
L0_CLKIN_L1
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1
Y1
W1
Y4
Y3
H_CLKOP0
H_CLKON0
H_CLKOP1
H_CLKON1
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
H_CTLIP0
H_CTLIN0
H_CTLIP1
H_CTLIN1
N1
P1
P3
P4
L0_CTLIN_H0
L0_CTLIN_L0
L0_CTLIN_H1
L0_CTLIN_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
R2
R3
T5
R5
H_CTLOP0
H_CTLON0
H_CTLOP1
H_CTLON1
<11>
<11>
<11>
<11>
FOX_PZ6382A-284S-41F_Champlian
CONN@
< FAN Control Circuit : Vout = 1.6 x Vset >

+5VS
1A
<28> EN_DFAN1
C1120
10U_0805_10V4Z
U31
1
2
3
4
EN
VIN
VOUT
VSET
JFAN
+FAN1
GND
GND
GND
GND
8
7
6
5
@
C1121
1000P_0402_25V8J
1
2
3
4
5
1
2
3
+3VS
1
C1119
10U_0805_10V4Z
R795
10K_0402_5%
GND
GND
ACES_85204-0300N
CONN@
APL5607KI-TRG_SO8
+FAN1
@
C1122
0.01U_0402_25V7K
Compal Secret Data
2010-08-25
Issued Date
FAN_SPEED1 <28>
2
2010-08-25
Deciphered Date
Title
Date:
SCHEMATICS,MB A6843
Rev
B
401982
Sheet

E
of
40
+1.5V
< Processor DDR3 Memory Interface >
< DDR2 VREF is 0.5 ratio >
< Close to CPU >

R1
JCPUC
<10> DDR_B_D[63..0]
1K_0402_1%
< From/To SO_DIMMB >
+MCH_REF
R2
C9
0.1U_0402_16V7K
C8
1000P_0402_25V8J
1K_0402_1%
+1.05VS
+1.05VS
JCPUB
Place them close to CPU within 1"
+1.5V
R4 1
R5 1
2 39.2_0402_1%
2 39.2_0402_1%
<9> MEM_MA_RST#
<9> DDR_A_ODT0
< To SO_DIMMA > <9> DDR_A_ODT1
< To SO_DIMMA >
<9> DDR_CS0_DIMMA#
<9> DDR_CS1_DIMMA#
<9> DDR_CKE0_DIMMA
< To SO_DIMMA > <9> DDR_CKE1_DIMMA

<9> DDR_A_CLK0
<9> DDR_A_CLK#0
MEM_P
MEM_N
<9> DDR_A_CLK1
<9> DDR_A_CLK#1
<9> DDR_A_BS#0
< To SO_DIMMA > <9> DDR_A_BS#1

<9> DDR_A_BS#2
< To SO_DIMMA >
<9> DDR_A_RAS#
<9> DDR_A_CAS#
<9> DDR_A_WE#
AF10
AE10
VDDR1 MEM:CMD/CTRL/CLK
VDDR5
VDDR2
VDDR6
VDDR3
VDDR7
VDDR4
VDDR8
VDDR9
MEMZP
MEMZN
VDDR_SENSE
W10
AC10
AB10
AA10
A10
Y10
VTT_SENSE
MEMVREF
W17
+MCH_REF
MB_RESET_L
B18
MB0_ODT0
MB0_ODT1
MB1_ODT0
W26
W23
Y26
DDR_B_ODT0
DDR_B_ODT1
MB0_CS_L0
MB0_CS_L1
MB1_CS_L0
V26
W25
U22
DDR_CS0_DIMMB#
DDR_CS1_DIMMB#
MB_CKE0
MB_CKE1
J25
H26
DDR_CKE0_DIMMB
DDR_CKE1_DIMMB
MB_CLK_H5
MB_CLK_L5
MB_CLK_H1
MB_CLK_L1
MB_CLK_H7
MB_CLK_L7
MB_CLK_H4
MB_CLK_L4
P22
R22
A17
A18
AF18
AF17
R26
R25
DDR_B_CLK0
DDR_B_CLK#0
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
MEM_MA_RST#
H16
MA_RESET_L
DDR_A_ODT0
DDR_A_ODT1
T19
V22
U21
V19
MA0_ODT0
MA0_ODT1
MA1_ODT0
MA1_ODT1
DDR_CS0_DIMMA# T20
DDR_CS1_DIMMA# U19
U20
V20
DDR_CKE0_DIMMA J22
DDR_CKE1_DIMMA J20
DDR_A_CLK0
DDR_A_CLK#0
MA0_CS_L0
MA0_CS_L1
MA1_CS_L0
MA1_CS_L1
MA_CKE0
MA_CKE1
< VTT regulator voltage >
MEM_MB_RST#
DDR_A_CLK1
DDR_A_CLK#1
N19
N20
E16
F16
Y16
AA16
P19
P20
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
N21
M20
N22
M19
M22
L20
M24
L21
L19
K22
R21
L22
K20
V24
K24
K19
MA_ADD0
MA_ADD1
MA_ADD2
MA_ADD3
MA_ADD4
MA_ADD5
MA_ADD6
MA_ADD7
MA_ADD8
MA_ADD9
MA_ADD10
MA_ADD11
MA_ADD12
MA_ADD13
MA_ADD14
MA_ADD15
MB_ADD0
MB_ADD1
MB_ADD2
MB_ADD3
MB_ADD4
MB_ADD5
MB_ADD6
MB_ADD7
MB_ADD8
MB_ADD9
MB_ADD10
MB_ADD11
MB_ADD12
MB_ADD13
MB_ADD14
MB_ADD15
P24
N24
P26
N23
N26
L23
N25
L24
M26
K26
T26
L26
L25
W24
J23
J24
DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2
R20
R23
J21
MA_BANK0
MA_BANK1
MA_BANK2
MB_BANK0
MB_BANK1
MB_BANK2
R24
U26
J26
DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
R19
T22
T24
MA_RAS_L
MA_CAS_L
MA_WE_L
MB_RAS_L
MB_CAS_L
MB_WE_L
U25
U24
U23
DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#
< To SO_DIMMA >
< To SO_DIMMA > <9> DDR_A_MA[15..0]
D10
C10
B10
AD10
MA_CLK_H5
MA_CLK_L5
MA_CLK_H1
MA_CLK_L1
MA_CLK_H7
MA_CLK_L7
MA_CLK_H4
MA_CLK_L4
PAD
T1
MEM_MB_RST# <10>
DDR_B_ODT0 <10>
DDR_B_ODT1 <10>
< To SO_DIMMB >
DDR_CS0_DIMMB# <10>
DDR_CS1_DIMMB# <10><
To SO_DIMMB >
DDR_CKE0_DIMMB <10>
DDR_CKE1_DIMMB <10><
To SO_DIMMB >
DDR_B_CLK0 <10>
DDR_B_CLK#0 <10>
< To SO_DIMMB >

DDR_B_CLK1
DDR_B_CLK#1
DDR_B_CLK1 <10>
DDR_B_CLK#1 <10>
DDR_B_MA[15..0] <10>
<10> DDR_B_DM[7..0]
< To SO_DIMMB >
DDR_B_BS#0 <10>
DDR_B_BS#1 <10>
DDR_B_BS#2 <10>
< To SO_DIMMB >
DDR_B_RAS# <10>
DDR_B_CAS# <10>
DDR_B_WE# <10>
< To SO_DIMMB >
< To SO_DIMMB >
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
DDR_B_DQS0
DDR_B_DQS#0
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS7
DDR_B_DQS#7
MEM:DATA
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
C11
A11
A14
B14
G11
E11
D12
A13
A15
A16
A19
A20
C14
D14
C18
D18
D20
A21
D24
C25
B20
C20
B24
C24
E23
E24
G25
G26
C26
D26
G23
G24
AA24
AA23
AD24
AE24
AA26
AA25
AD26
AE25
AC22
AD22
AE20
AF20
AF24
AF23
AC20
AD20
AD18
AE18
AC14
AD14
AF19
AC18
AF16
AF15
AF13
AC12
AB11
Y11
AE14
AF14
AF11
AD11
MB_DATA0
MB_DATA1
MB_DATA2
MB_DATA3
MB_DATA4
MB_DATA5
MB_DATA6
MB_DATA7
MB_DATA8
MB_DATA9
MB_DATA10
MB_DATA11
MB_DATA12
MB_DATA13
MB_DATA14
MB_DATA15
MB_DATA16
MB_DATA17
MB_DATA18
MB_DATA19
MB_DATA20
MB_DATA21
MB_DATA22
MB_DATA23
MB_DATA24
MB_DATA25
MB_DATA26
MB_DATA27
MB_DATA28
MB_DATA29
MB_DATA30
MB_DATA31
MB_DATA32
MB_DATA33
MB_DATA34
MB_DATA35
MB_DATA36
MB_DATA37
MB_DATA38
MB_DATA39
MB_DATA40
MB_DATA41
MB_DATA42
MB_DATA43
MB_DATA44
MB_DATA45
MB_DATA46
MB_DATA47
MB_DATA48
MB_DATA49
MB_DATA50
MB_DATA51
MB_DATA52
MB_DATA53
MB_DATA54
MB_DATA55
MB_DATA56
MB_DATA57
MB_DATA58
MB_DATA59
MB_DATA60
MB_DATA61
MB_DATA62
MB_DATA63
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
A12
B16
A22
E25
AB26
AE22
AC16
AD12
MB_DM0
MB_DM1
MB_DM2
MB_DM3
MB_DM4
MB_DM5
MB_DM6
MB_DM7
DDR_B_DQS0
DDR_B_DQS#0
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS7
DDR_B_DQS#7
C12
B12
D16
C16
A24
A23
F26
E26
AC25
AC26
AF21
AF22
AE16
AD16
AF12
AE12
MB_DQS_H0
MB_DQS_L0
MB_DQS_H1
MB_DQS_L1
MB_DQS_H2
MB_DQS_L2
MB_DQS_H3
MB_DQS_L3
MB_DQS_H4
MB_DQS_L4
MB_DQS_H5
MB_DQS_L5
MB_DQS_H6
MB_DQS_L6
MB_DQS_H7
MB_DQS_L7
< From/To SO_DIMMB >
DDR_A_D[63..0]
MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7
MA_DATA8
MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15
MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23
MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31
MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39
MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47
MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55
MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63
G12
F12
H14
G14
H11
H12
C13
E13
H15
E15
E17
H17
E14
F14
C17
G17
G18
C19
D22
E20
E18
F18
B22
C23
F20
F22
H24
J19
E21
E22
H20
H22
Y24
AB24
AB22
AA21
W22
W21
Y22
AA22
Y20
AA20
AA18
AB18
AB21
AD21
AD19
Y18
AD17
W16
W14
Y14
Y17
AB17
AB15
AD15
AB13
AD13
Y12
W11
AB14
AA14
AB12
AA12
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7
E12
C15
E19
F24
AC24
Y19
AB16
Y13
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
MA_DQS_H0
MA_DQS_L0
MA_DQS_H1
MA_DQS_L1
MA_DQS_H2
MA_DQS_L2
MA_DQS_H3
MA_DQS_L3
MA_DQS_H4
MA_DQS_L4
MA_DQS_H5
MA_DQS_L5
MA_DQS_H6
MA_DQS_L6
MA_DQS_H7
MA_DQS_L7
G13
H13
G16
G15
C22
C21
G22
G21
AD23
AC23
AB19
AB20
Y15
W15
W12
W13
DDR_A_DQS0
DDR_A_DQS#0
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS7
DDR_A_DQS#7
DDR_A_DM[7..0]
<9>
< To SO_DIMMA >
DDR_A_DQS0
DDR_A_DQS#0
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS7
DDR_A_DQS#7
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
< From/To SO_DIMMA >
CONN@
CONN@
<9>
< From/To SO_DIMMA >
Compal Secret Data
2010-08-25
Issued Date
2010-08-25
Deciphered Date
Title
Date:
SCHEMATICS,MB A6843
Rev
B
401982
Sheet

E
of
40
JCPUD
+1.5V
+2.5VDDA
+2.5VS
+2.5VDDA
CPU_CLKIN_SC_P
CPU_CLKIN_SC_N
VDDA=300mA
L1 1
2 FBM_L11_201209_300L_0805
1
1
C12
C13
+2.5VDDA
1
C14
LDT_RST#
H_PWRGD
LDT_STOP#
+ C11
@
2
150U_B2_6.3VM_R45M
4.7U_0805_10V4Z
3300P_0402_50V7K
0.22U_0603_16V4Z
T2
+1.5V
+1.5V
< 200-MHz PLL Reference Clock >

1
C16
2 3900P_0402_50V7K
+1.1VS
CPU_CLKIN_SC_P
R15
R16
2 1K_0402_5%
2 1K_0402_5%
1
1
PAD
CPU_HTREF0
CPU_HTREF1
CPU_VDD0_RUN_FB_H
CPU_VDD0_RUN_FB_L
R10
Address:100_1100
C15
2 3900P_0402_50V7K
CPU_CLKIN_SC_N
Place close to CPU wihtin 1.5"
2 510_0402_5%
CPU_TEST25L
R29
1 1K_0402_5%
CPU_TEST12
R30
1 1K_0402_5%
CPU_TEST18
R31
1 1K_0402_5%
CPU_TEST19
R32
1 1K_0402_5%
CPU_TEST20
R33
1 1K_0402_5%
CPU_TEST21
R34
1 1K_0402_5%
CPU_TEST22
R265 2
1 1K_0402_5%
CPU_TEST23
R35
1 1K_0402_5%
CPU_TEST24
HT_REF0
HT_REF1
F6
E6
PAD
PAD
VDDNB_FB_H
VDDNB_FB_L
H6
G6
CPU_VDDNB_RUN_FB_H
CPU_VDDNB_RUN_FB_L
DBREQ_L
E10
CPU_DBREQ#
TDO
AE9
CPU_TDO
TEST23
TEST18
TEST19
TEST28_H
TEST28_L
TEST21
TEST20
TEST24
TEST22
TEST12
TEST27
C2
AA6
TEST9
TEST6
A3
A5
B3
B5
C1
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
1K_0402_5% 1
2 R20
D7
E7
F7
C7
TEST7
TEST10
C3
K8
TEST8
C4
TEST29_H
TEST29_L
C9
C8
RSVD10
RSVD9
RSVD8
RSVD7
RSVD6
CPU_VDDNB_RUN_FB_H
CPU_VDDNB_RUN_FB_L
+1.5V
CPU_TEST17
CPU_TEST16
CPU_TEST15
CPU_TEST14
2 300_0402_5%
@ R13 1
2 0_0402_5%
H_PROCHOT# <18>
route as differential
as short as possible
testpoint under package
T15
T16
J7
H8
TEST17
TEST16
TEST15
TEST14
TEST25_H
TEST25_L
AB8
AF7
AE7
AE8
AC8
AF8
CPU_SVD
W9
Y9
H10
G9
2 R19
CPU_PROCHOT#
VDDIO_FB_H
VDDIO_FB_L
CPU_TEST18
CPU_TEST19
R11
+1.5V
VDD0_FB_H
VDD0_FB_L
AD7
2 0_0402_5%
AF6 CPU_THERMTRIP#_R
AC7 CPU_PROCHOT#
AA8
PAD T3
THERMDC_CPU
THERMDA_CPU
CPU_TEST23
THERMTRIP_L
PROCHOT_L
MEMHOT_L
W7
W8
DBRDY
TMS
TCK
TRST_L
TDI
E9
E8
CPU_SVC <38>
CPU_SVD <38>
1K_0402_5% 1
< Serial VID Interface clock & data >
THERMDC
THERMDA
VDD1_FB_H
VDD1_FB_L
R24
R27
R6
P6
CPU_SVC
CPU_SVD
CPU_SVC
PAD
PAD
PAD
PAD
T4
T5
T6
T7
<38>
<38>
R6
10K_0402_5%
R7
2 1K_0402_5%
CPU_THERMTRIP#_R
Q1
1
H_THERMTRIP# <19>
R28
2
SIC
SID
ALERT_L
Y6
AB6
CPU_TEST21
CPU_TEST20
CPU_TEST24
CPU_TEST22
CPU_TEST12
CPU_TEST27
CPU_TEST25H
CPU_TEST27
AF4
AF5
AE6
A6
A4
2
2
1 510_0402_5%
1
1K_0402_5%
RESET_L
PWROK
LDTSTOP_L
LDTREQ_L
SVC
SVD
M11
W18
R22
CLKIN_H
CLKIN_L
G10
AA9
AC9
AD9
AF9
CPU_TEST25H
CPU_TEST25L
+1.5V
A9
A8
VSS
RSVD11
CPU_DBRDY
CPU_TMS
CPU_TCK
CPU_TRST#
CPU_TDI
169_0402_1%
<18> CLK_CPU_BCLK#
VDDA1
VDDA2
B7
A7
F10
C6
CPU_SIC
CPU_SID
2 44.2_0402_1%
2 44.2_0402_1%
1
1
<38> CPU_VDD0_RUN_FB_H
<38> CPU_VDD0_RUN_FB_L
<18> CLK_CPU_BCLK
R12
R14
F8
F9
< Filtered PLL Supply Voltage >
MMBT3904_NL_SOT23-3
CPU_TEST29_H_FBCLKOUT_P
CPU_TEST29_L_FBCLKOUT_N
2
R25
1
80.6_0402_1%
H18
H19
AA7
D5
C5
CONN@
+1.5VS
R17
300_0402_5%
1
<18> LDT_RST#
LDT_RST#
C17
< Thermal Sensor >
@
2
0.01U_0402_25V7K
< HDT Connector >
U1
+3VS
JP2
+1.5VS
2
+1.5V
R21
300_0402_5%
<18,38> H_PWRGD
+1.5V
R40
2 300_0402_5%
1
R39
R38
R37
R36
1
1
1
1
2
2
2
2
H_PWRGD
+1.5V
C19
@
2
220_0402_5%
220_0402_5%
220_0402_5%
220_0402_5%
CPU_DBREQ#
CPU_DBRDY
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST#
CPU_TDO
1
3
5
7
9
11
13
15
17
19
21
23
2
4
6
8
10
12
14
16
18
20
22
24
26
C20
VDD
SMCLK
EC_SMB_CK2
THERMDA_CPU
DP
SMDATA
EC_SMB_DA2
THERMDC_CPU
2
2200P_0402_50V7K
CPU_THERM#
DN
ALERT#
THERM#
GND
1
C21
0.1U_0402_16V7K
+3VS
R44
1
2
10K_0402_5%
1
R41
EC_SMB_CK2 <28>
EC_SMB_DA2 <28>
2
10K_0402_5%
@
+3VS
EMC1402-1-ACZL-TR_MSOP8
LDT_RST#
Address:0100_1100 EMC1402-1
Address:0100_1101 EMC1402-2
0.1U_0402_16V7K
SAMTEC_ASP-68200-07
CONN@
3/30 Change U1 ADM1032 to EMC1402 for cost down

+1.5VS
4
R18
300_0402_5%
<12,18> LDT_STOP#
LDT_STOP#
Compal Secret Data
C18
2010-08-25
Issued Date
@
0.01U_0402_25V7K
2010-08-25
Deciphered Date
Title
Date:
SCHEMATICS,MB A6843
Rev
B
401982
Sheet

E
of
40
JCPUE
+CPU_CORE
VDD decoupling : +CPU_CORE

+CPU_CORE
1
+ C90
2
1
+ C25
2
330U_6.3V_M_R15
+ C26
330U_X_2VM_R6M
330U_6.3V_M_R15
330U_X_2VM_R6M
+CPU_CORE
+CPU_CORE
C35
C34
C28
C29
C36
C37
C38
+ C96
2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
0.22U_0603_16V4Z
0.01U_0402_25V7K
180P_0402_50V8J
Under CPU Socket
Under CPU Socket
Near CPU Socket
+ C23
2
1
+ C89
2
Near CPU Socket
1
+ C24
2
330U_6.3V_M_R15
330U_X_2VM_R6M
+CPU_CORE
330U_6.3V_M_R15
330U_X_2VM_R6M
+CPU_CORE
+CPU_CORE
C30
C31
C32
C33
C39
C40
C41
+ C95
2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
Under CPU Socket
0.22U_0603_16V4Z
0.01U_0402_25V7K
180P_0402_50V8J
+VDDNB
Under CPU Socket
+1.5V
VDDIO decoupling : DDR SDRAM I/O ring power

+1.5V
C44
22U_0805_6.3V6M
C45
22U_0805_6.3V6M
C46
0.22U_0603_16V4Z
C47
0.22U_0603_16V4Z
C48
180P_0402_50V8J
C50
180P_0402_50V8J
Under CPU Socket

+1.5V
2
C54
0.22U_0603_16V4Z
C51
0.22U_0603_16V4Z
C52
0.22U_0603_16V4Z
0.01U_0402_25V7K
C65
0.01U_0402_25V7K
180PF Qt'y follow the distance between CPU socket and DIMM0. <2.5inch>
180P_0402_50V8J
C68
180P_0402_50V8J
C69
180P_0402_50V8J
Between CPU Socket and DIMM
C56 Co-layout with C75
+1.5V
3
1
1
C71
4.7U_0805_10V4Z
C72
4.7U_0805_10V4Z
C73
4.7U_0805_10V4Z
C74
4.7U_0805_10V4Z
C75
+1.05VS
+
2
+1.5V
1
C56 +
2
390U_2.5V_M_R10
C67
330U_D2E_2.5VM_R6M
180P_0402_50V8J
VDDR decoupling.
C57
4.7U_0805_10V4Z
C58
4.7U_0805_10V4Z
C59
0.22U_0603_16V4Z
C60
0.22U_0603_16V4Z
C61
1000P_0402_25V8J
C62
1000P_0402_25V8J
C63
180P_0402_50V8J
C70
C78
0.22U_0603_16V4Z
C79
0.22U_0603_16V4Z
C80
1000P_0402_25V8J
C81
1000P_0402_25V8J
C82
180P_0402_50V8J
C83
180P_0402_50V8J
1
+
2
390U_2.5V_M_R10
+1.05VS
C1124
C77
4.7U_0805_10V4Z
C1125
330U_D2E_2.5VM
Near CPU Socket Right side
C76
4.7U_0805_10V4Z
+1.05VS
180P_0402_50V8J
+1.05VS
H25
J17
K18
K21
K23
K25
L17
M18
M21
M23
M25
N17
VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12
AA4
AA11
AA13
AA15
AA17
AA19
AB2
AB7
AB9
AB23
AB25
AC11
AC13
AC15
AC17
AC19
AC21
AD6
AD8
AD25
AE11
AE13
AE15
AE17
AE19
AE21
AE23
B4
B6
B8
B9
B11
B13
B15
B17
B19
B21
B23
B25
D6
D8
D9
D11
D13
D15
D17
D19
D21
D23
D25
E4
F2
F11
F13
F15
F17
F19
F21
F23
F25
H7
H9
H21
H23
J4
+1.5V
C66
VDDNB_1
VDDNB_2
VDDNB_3
VDDNB_4
VDDNB_5
P8
P10
R4
R7
R9
R11
T2
T6
T8
T10
T12
T14
U7
U9
U11
U13
U15
V6
V8
V10
V12
V14
W4
Y2
AC4
AD2
VDDIO27
VDDIO26
VDDIO25
VDDIO24
VDDIO23
VDDIO22
VDDIO21
VDDIO20
VDDIO19
VDDIO18
VDDIO17
VDDIO16
VDDIO15
VDDIO14
VDDIO13
Y25
V25
V23
V21
V18
U17
T25
T23
T21
T18
R17
P25
P23
P21
P18
+1.5V
JCPUF
0.22U_0603_16V4Z
K16
M16
P16
T16
V16
VDD1_1
VDD1_2
VDD1_3
VDD1_4
VDD1_5
VDD1_6
VDD1_7
VDD1_8
VDD1_9
VDD1_10
VDD1_11
VDD1_12
VDD1_13
VDD1_14
VDD1_15
VDD1_16
VDD1_17
VDD1_18
VDD1_19
VDD1_20
VDD1_21
VDD1_22
VDD1_23
VDD1_24
VDD1_25
VDD1_26
CONN@
+1.5V
C64
VDD0_1
VDD0_2
VDD0_3
VDD0_4
VDD0_5
VDD0_6
VDD0_7
VDD0_8
VDD0_9
VDD0_10
VDD0_11
VDD0_12
VDD0_13
VDD0_14
VDD0_15
VDD0_16
VDD0_17
VDD0_18
VDD0_19
VDD0_20
VDD0_21
VDD0_22
VDD0_23
C53
G4
H2
J9
J11
J13
J15
K6
K10
K12
K14
L4
L7
L9
L11
L13
L15
M2
M6
M8
M10
N7
N9
N11
+CPU_CORE
Near CPU Socket Left side

4
+VDDNB decoupling : Northbridge power

+VDDNB
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
J6
J8
J10
J12
J14
J16
J18
K2
K7
K9
K11
K13
K15
K17
L6
L8
L10
L12
L14
L16
L18
M7
M9
AC6
M17
N4
N8
N10
N16
N18
P2
P7
P9
P11
P17
R8
R10
R16
R18
T7
T9
T11
T13
T15
T17
U4
U6
U8
U10
U12
U14
U16
U18
V2
V7
V9
V11
V13
V15
V17
W6
Y21
Y23
N6
CONN@
1
C42
22U_0805_6.3V6M
C43
22U_0805_6.3V6M
Compal Secret Data
C49
2010-08-25
Issued Date
22U_0805_6.3V6M
2010-08-25
Deciphered Date
Title
Date:
SCHEMATICS,MB A6843
Rev
B
401982
Sheet

E
of
40
+1.5V
+1.5V
JDDRL
C10
DDR_A_DM0
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9
<6> DDR_A_DQS#1
<6> DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D16
DDR_A_D17
<6> DDR_A_DQS#2
<6> DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_DM3
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1
VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
DDR_A_D4
DDR_A_D5
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_DQS#0 <6>
DDR_A_DQS0 <6>
DDR_A_D[0..63]
DDR_A_D6
DDR_A_D7
DDR_A_DM[0..7]
DDR_A_D[0..63]
<6>
DDR_A_DM[0..7]
<6>
1
DDR_A_D12
DDR_A_D13
DDR_A_MA[0..15]
DDR_A_DM1
MEM_MA_RST#
DDR_A_MA[0..15] <6>
MEM_MA_RST# <6>
DDR_A_D14
DDR_A_D15
DDR_A_D20
DDR_A_D21
DDR_A_DM2
DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
+1.5V
+1.5V
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_DQS#3 <6>
DDR_A_DQS3 <6>
DDR_A_D30
DDR_A_D31
R310
1K_0402_1%
R48
1K_0402_1%
1
DDR_A_D26
DDR_A_D27
VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25
C85
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
1000P_0402_25V8J
C84
0.01U_0402_25V7K
4.7U_0805_10V4Z
DDR_A_D0
DDR_A_D1
+VREF_DQ
+VREF_DQ
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
<6> DDR_A_CLK0
<6> DDR_A_CLK#0
<6> DDR_A_BS#0
<6> DDR_A_WE#
<6> DDR_A_CAS#
<6> DDR_CS1_DIMMA#
DDR_A_CLK0
DDR_A_CLK#0
DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#
DDR_A_CAS#
DDR_A_MA13
DDR_CS1_DIMMA#
DDR_A_D32
DDR_A_D33
<6> DDR_A_DQS#4
<6> DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
<6> DDR_A_DQS#6
<6> DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_DM7
DDR_A_D58
DDR_A_D59
+3VS
+0.75VS
4
C91
0.1U_0402_16V4Z 2
205
206
G2
G1
DDR_A_MA15
DDR_A_MA14
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_CLK1
DDR_A_CLK#1
DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#
DDR_A_ODT0
DDR_A_ODT1
< Close to JDDRH & JDDRL >
DDR_A_CLK1 <6>
DDR_A_CLK#1 <6>
DDR_A_BS#1 <6>
DDR_A_RAS# <6>
DDR_CS0_DIMMA# <6>
DDR_A_ODT0 <6>
DDR_A_ODT1 <6>
+VREF_CA
DDR_A_D36
DDR_A_D37
DDR_A_DM4
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
1
C680
2
C235
2
C351
+1.5V
0.1U_0402_16V4Z
2
C87
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C88
C640
C641
1
0.1U_0402_16V4Z
DDR_A_DQS#5 <6>
DDR_A_DQS5 <6>
0.1U_0402_16V4Z
2
C642
1
0.1U_0402_16V4Z
C643
1
0.1U_0402_16V4Z
2
C644
1
0.1U_0402_16V4Z
C645
1
0.1U_0402_16V4Z
2
C646
1
0.1U_0402_16V4Z
C647
1
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
DDR_A_DM6
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
+0.75VS
DDR_A_DQS#7 <6>
DDR_A_DQS7 <6>
DDR_A_D62
DDR_A_D63
0.1U_0402_16V4Z
2
C665
C664
1
0.1U_0402_16V4Z
C961
2
4.7U_0603_6.3V6K
SMB_CK_DAT0 <10,19>
SMB_CK_CLK0 <10,19>
+0.75VS
4
TYCO_2-2013289-1
CONN@
Compal Secret Data
DIMM_A STD H:5.2 mm
2010-08-25
Issued Date
2010-08-25
Deciphered Date
Title
<Address: 00>
Date:
R315
1K_0402_1%
R49
1K_0402_1%
DDR_A_MA11
DDR_A_MA7
DDR_A_MA12
DDR_A_MA9
+VREF_CA
DDR_CKE1_DIMMA <6>
DDR_A_BS#2
DDR_CKE1_DIMMA
0.01U_0402_25V7K
<6> DDR_A_BS#2
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
4.7U_0805_10V4Z
CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
1000P_0402_25V8J
DDR_CKE0_DIMMA
<6> DDR_CKE0_DIMMA
SCHEMATICS,MB A6843
Rev
B
401982
Sheet

E
of
40
+1.5V
+1.5V
JDDRH
C92
1000P_0402_25V8J
0.1U_0402_16V4Z
4.7U_0805_10V4Z
+VREF_DQ
C93
DDR_B_D0
DDR_B_D1
1
DDR_B_DM0
C682
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
<6> DDR_B_DQS#1
<6> DDR_B_DQS1
DDR_B_D10
DDR_B_D11
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
<6> DDR_B_DQS#2
<6> DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B_DM3
DDR_B_D26
DDR_B_D27
DDR_CKE0_DIMMB
<6> DDR_CKE0_DIMMB
2
DDR_B_BS#2
<6> DDR_B_BS#2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
DDR_B_CLK0
DDR_B_CLK#0
<6> DDR_B_CLK0
<6> DDR_B_CLK#0
DDR_B_MA10
DDR_B_BS#0
<6> DDR_B_BS#0
DDR_B_WE#
DDR_B_CAS#
<6> DDR_B_WE#
<6> DDR_B_CAS#
DDR_B_MA13
DDR_CS1_DIMMB#
<6> DDR_CS1_DIMMB#
DDR_B_D40
DDR_B_D41
DDR_B_DM5
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
<6> DDR_B_DQS#6
<6> DDR_B_DQS6
DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57
DDR_B_DM7
DDR_B_D58
DDR_B_D59
+3VS
+0.75VS
4
CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1
205
G1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
G2
206
DDR_B_D4
DDR_B_D5
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_DQS#0 <6>
DDR_B_DQS0 <6>
DDR_B_D[0..63]
DDR_B_D6
DDR_B_D7
DDR_B_D[0..63]
DDR_B_DM[0..7]
DDR_B_DM[0..7]
<6>
<6>
1
DDR_B_D12
DDR_B_D13
DDR_B_MA[0..15]
DDR_B_MA[0..15]
DDR_B_DM1
MEM_MB_RST#
<6>
MEM_MB_RST# <6>
DDR_B_D14
DDR_B_D15
DDR_B_D20
DDR_B_D21
DDR_B_DM2
DDR_B_D22
DDR_B_D23
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_DQS#3 <6>
DDR_B_DQS3 <6>
DDR_B_D30
DDR_B_D31
DDR_CKE1_DIMMB
DDR_CKE1_DIMMB <6>
DDR_B_MA15
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDR_B_CLK1
DDR_B_CLK#1
DDR_B_CLK1 <6>
DDR_B_CLK#1 <6>
DDR_B_BS#1
DDR_B_RAS#
DDR_B_BS#1 <6>
DDR_B_RAS# <6>
DDR_CS0_DIMMB#
DDR_B_ODT0
DDR_CS0_DIMMB# <6>
DDR_B_ODT0 <6>
DDR_B_ODT1
DDR_B_ODT1 <6>
+VREF_CA
DDR_B_D36
DDR_B_D37
DDR_B_DM4
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
C683
0.1U_0402_16V4Z
DDR_B_D34
DDR_B_D35
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26
4.7U_0805_10V4Z
DDR_B_DQS#4
DDR_B_DQS4
<6> DDR_B_DQS#4
<6> DDR_B_DQS4
VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25
1000P_0402_25V8J
DDR_B_D32
DDR_B_D33
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
C352
C353
3
DDR_B_DQS#5 <6>
DDR_B_DQS5 <6>
DDR_B_D46
DDR_B_D47
+1.5V
DDR_B_D52
DDR_B_D53
0.1U_0402_16V4Z
2
DDR_B_DM6
C666
1
0.1U_0402_16V4Z
DDR_B_D54
DDR_B_D55
0.1U_0402_16V4Z
2
C667
1
C668
1
0.1U_0402_16V4Z
C669
1
0.1U_0402_16V4Z
2
C670
C671
1
0.1U_0402_16V4Z
DDR_B_DQS#7
DDR_B_DQS7
C674
C677
1
0.1U_0402_16V4Z
+0.75VS
+1.5V
DDR_B_D62
DDR_B_D63
DIMM_B STD H:9.2 mm
0.1U_0402_16V4Z
2
C676
SMB_CK_DAT0 <9,19>
SMB_CK_CLK0 <9,19>
1
0.1U_0402_16V4Z
+0.75VS
C675
1
+1.5V
1
+
C925
2
4.7U_0603_6.3V6K
1
C86
330U_X_2VM_R6M
C128
2
390U_2.5V_M_R10
4
Place near DIMM2
Compal Secret Data

2010-08-25
Issued Date
2010-08-25
Deciphered Date
Title
Date:
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C673

DDR_B_DQS#7 <6>
DDR_B_DQS7 <6>
C672
DDR_B_D60
DDR_B_D61
LOTES_AAA-DDR-111-K01
CONN@
<Address: 01>
0.1U_0402_16V4Z
2
SCHEMATICS,MB A6843
Rev
B
401982
Sheet

E
10
of
40
U3B
<23>
<23>
<24>
<24>
< WLAN >

< LAN >
PCIE_PTX_C_IRX_P2
PCIE_PTX_C_IRX_N2
PCIE_PTX_C_IRX_P3
PCIE_PTX_C_IRX_N3
< From SB820 : x4 PCIE A-link >
<18>
<18>
<18>
<18>
<18>
<18>
<18>
<18>
SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N
GFX_RX0P
GFX_RX0N
GFX_RX1P
GFX_RX1N
GFX_RX2P
GFX_RX2N
GFX_RX3P
GFX_RX3N
GFX_RX4P
GFX_RX4N
GFX_RX5P
GFX_RX5N
GFX_RX6P
GFX_RX6N
GFX_RX7P
GFX_RX7N
GFX_RX8P
GFX_RX8N
GFX_RX9P
GFX_RX9N
GFX_RX10P
GFX_RX10N
GFX_RX11P
GFX_RX11N
GFX_RX12P
GFX_RX12N
GFX_RX13P
GFX_RX13N
GFX_RX14P
GFX_RX14N
GFX_RX15P
GFX_RX15N
AE3
AD4
AE2
AD3
AD1
AD2
V5
W6
U5
U6
U8
U7
GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N
GPP_RX4P
GPP_RX4N
GPP_RX5P
GPP_RX5N
AA8
Y8
AA7
Y7
AA5
AA6
W5
Y5
SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N
880MR1@
GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P
GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N
A5
B5
A4
B4
C3
B2
D1
D2
E2
E1
F4
F3
F1
F2
H4
H3
H1
H2
J2
J1
K4
K3
K1
K2
M4
M3
M1
M2
N2
N1
P1
P2
GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
GPP_TX4P
GPP_TX4N
GPP_TX5P
GPP_TX5N
AC1
AC2
AB4
AB3
AA2
AA1
Y1
Y2
Y4
Y3
V1
V2
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N
AD7
AE7
AE6
AD6
AB6
AC6
AD5
AE5
SB_TX0P_C
SB_TX0N_C
SB_TX1P_C
SB_TX1N_C
SB_TX2P_C
SB_TX2N_C
SB_TX3P_C
SB_TX3N_C
PCE_CALRP(PCE_BCALRP)
PCE_CALRN(PCE_BCALRN)
AC8
AB8
PCIE_CALRP
PCIE_CALRN
PART 2 OF 6
PCIE I/F GFX
D4
C4
A3
B3
C2
C1
E5
F5
G5
G6
H5
H6
J6
J5
J7
J8
L5
L6
M8
L8
P7
M7
P5
M5
R8
P8
R6
R5
P4
P3
T4
T3
PCIE I/F GPP
PCIE I/F SB
PCIE PORT LIST
PCIE_ITX_PRX_P2
PCIE_ITX_PRX_N2
PCIE_ITX_PRX_P3
PCIE_ITX_PRX_N3
C129
C130
C131
C132
1
1
1
1
2
2
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
C133
C134
C135
C136
C137
C138
C139
C140
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
PCIE_ITX_C_PRX_P2
PCIE_ITX_C_PRX_N2
PCIE_ITX_C_PRX_P3
PCIE_ITX_C_PRX_N3
<23>
<23>
<24>
<24>
PORT
DEVICE
PCIE-2 WLAN
PCIE-3 LAN
< WLAN >
< LAN >
R59
R58
1
1
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N
1.27K_0402_1%
2K_0402_1%
2
2
<18>
<18>
<18>
<18>
<18>
<18>
<18>
<18>
< To SB820 : x4 PCEI A-link>
< TX Impedance Calibration. Connect to GND >

< RX Impedance Calibration. Connect to VDDPCIE >
+1.1VS
RS780M_FCBGA528
U3A
H_CADON[0..15]
H_CADOP[0..15]
<5>
H_CADON[0..15]
<5>
H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADOP2
H_CADON2
H_CADOP3
H_CADON3
H_CADOP4
H_CADON4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7
< From S1G4 CPU : x16 HT>
<5>
<5>
<5>
<5>
H_CLKOP0
H_CLKON0
H_CLKOP1
H_CLKON1
<5>
<5>
<5>
<5>
H_CTLOP0
H_CTLON0
H_CTLOP1
H_CTLON1
301_0402_1%1
Y25
Y24
V22
V23
V25
V24
U24
U25
T25
T24
P22
P23
P25
P24
N24
N25
H_CADOP8
H_CADON8
H_CADOP9
H_CADON9
H_CADOP10
H_CADON10
H_CADOP11
H_CADON11
H_CADOP12
H_CADON12
H_CADOP13
H_CADON13
H_CADOP14
H_CADON14
H_CADOP15
H_CADON15
2 R60
PART 1 OF 6
HT_TXCAD0P
HT_TXCAD0N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD7P
HT_TXCAD7N
D24
D25
E24
E25
F24
F25
F23
F22
H23
H22
J25
J24
K24
K25
K23
K22
H_CADIP0
H_CADIN0
H_CADIP1
H_CADIN1
H_CADIP2
H_CADIN2
H_CADIP3
H_CADIN3
H_CADIP4
H_CADIN4
H_CADIP5
H_CADIN5
H_CADIP6
H_CADIN6
H_CADIP7
H_CADIN7
HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD15P
HT_TXCAD15N
F21
G21
G20
H21
J20
J21
J18
K17
L19
J19
M19
L18
M21
P21
P18
M18
H_CADIP8
H_CADIN8
H_CADIP9
H_CADIN9
H_CADIP10
H_CADIN10
H_CADIP11
H_CADIN11
H_CADIP12
H_CADIN12
H_CADIP13
H_CADIN13
H_CADIP14
H_CADIN14
H_CADIP15
H_CADIN15
HT_TXCLK0P
HT_TXCLK0N
HT_TXCLK1P
HT_TXCLK1N
H24
H25
L21
L20
AC24
AC25
AB25
AB24
AA24
AA25
Y22
Y23
W21
W20
V21
V20
U20
U21
U19
U18
HT_RXCAD8P
HT_RXCAD8N
HT_RXCAD9P
HT_RXCAD9N
HT_RXCAD10P
HT_RXCAD10N
HT_RXCAD11P
HT_RXCAD11N
HT_RXCAD12P
HT_RXCAD12N
HT_RXCAD13P
HT_RXCAD13N
HT_RXCAD14P
HT_RXCAD14N
HT_RXCAD15P
HT_RXCAD15N
T22
T23
AB23
AA22
HT_RXCLK0P
HT_RXCLK0N
HT_RXCLK1P
HT_RXCLK1N
H_CTLOP0
H_CTLON0
H_CTLOP1
H_CTLON1
M22
M23
R21
R20
HT_RXCTL0P
HT_RXCTL0N
HT_RXCTL1P
HT_RXCTL1N
HT_TXCTL0P
HT_TXCTL0N
HT_TXCTL1P
HT_TXCTL1N
M24
M25
P19
R18
H_CTLIP0
H_CTLIN0
H_CTLIP1
H_CTLIN1
HT_RXCALP
HT_RXCALN
C23
A24
HT_RXCALP
HT_RXCALN
HT_TXCALP
HT_TXCALN
B24
B25
HT_TXCALP
HT_TXCALN
880MR1@ RS780M_FCBGA528
0718 Place within 1"

layout 1:2
HT_RXCAD0P
HT_RXCAD0N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD2P
HT_RXCAD2N
HT_RXCAD3P
HT_RXCAD3N
HT_RXCAD4P
HT_RXCAD4N
HT_RXCAD5P
HT_RXCAD5N
HT_RXCAD6P
HT_RXCAD6N
HT_RXCAD7P
HT_RXCAD7N
HYPER TRANSPORT CPU I/F
H_CADOP[0..15]
H_CADIP[0..15]
H_CADIN[0..15]
H_CADIP[0..15]
<5>
H_CADIN[0..15]
<5>
< To S1G4 CPU : x16 HT>
H_CLKIP0
H_CLKIN0
H_CLKIP1
H_CLKIN1
<5>
<5>
<5>
<5>
H_CTLIP0
H_CTLIN0
H_CTLIP1
H_CTLIN1
<5>
<5>
<5>
<5>
R61
2 301_0402_1%
< Transmitter Calibration Resistor to HT_TXCALN >
0718 Place within 1"

layout 1:2
Compal Secret Data
2010-08-25
Issued Date
2010-08-25
Deciphered Date
Title
Date:
SCHEMATICS,MB A6843
Rev
B
401982
Sheet

E
11
of
40
+AVDD2
+AVDDQ
C144
2.2U_0603_6.3V4Z
+1.8VS
L4
+AVDD2
0_0603_5%
1
C142
C145
2.2U_0603_6.3V4Z
0.1U_0402_16V7K
+1.8VS
L6
2 BLM18PG121SN1D_0603
+AVDDQ
1
<16> UMA_CRT_R
<16> UMA_CRT_G
<16> UMA_CRT_B
<15,16>
<15,16>
<16>
<16>
UMA_CRT_HSYNC
UMA_CRT_VSYNC
UMA_CRT_CLK
UMA_CRT_DATA
R65 1
C148
2 715_0402_1%
+NB_PLLVDD
+NB_HTPVDD
2.2U_0603_6.3V4Z
+VDDA18HTPLL
+1.1VS
+VDDA18PCIEPLL
L2
2 BLM18PG121SN1D_0603
C141
2.2U_0603_6.3V4Z
R66 1
<15,18,23,24,28,29> PLT_RST#
<19> NB_PWRGD
NB_LDTSTOP#
<18> CPU_LDT_REQ#
L5
2 BLM18PG121SN1D_0603
+NB_HTPVDD
1
C146
2.2U_0603_6.3V4Z
LCD_EDID_CLK
LCD_EDID_DATA
<17> LCD_EDID_CLK
<17> LCD_EDID_DATA
T10 PAD
L7
2 BLM18PG121SN1D_0603
+VDDA18HTPLL
1
C150
T8
2.2U_0603_6.3V4Z
G18
G17
E18
F18
E19
F19
RED(DFT_GPIO0)
REDb(NC)
GREEN(DFT_GPIO1)
GREENb(NC)
BLUE(DFT_GPIO3)
BLUEb(NC)
A11
B11
F8
E8
DAC_HSYNC(PWM_GPIO4)
DAC_VSYNC(PWM_GPIO6)
DAC_SCL(PCE_RCALRN)
DAC_SDA(PCE_TCALRN)
G14
DAC_RSET(PWM_GPIO1)
A12
D14
B12
PLLVDD(NC)
PLLVDD18(NC)
PLLVSS(NC)
H17
VDDA18HTPLL
SYSRESETb
POWERGOOD
LDTSTOPb
ALLOW_LDTSTOP
<18> CLK_SBSRC_BCLK
<18> CLK_SBSRC_BCLK#
+1.8VS
C_Pr(DFT_GPIO5)
Y(DFT_GPIO2)
COMP_Pb(DFT_GPIO4)
VDDA18PCIEPLL1
VDDA18PCIEPLL2
NB_REFCLK_P
NB_REFCLK_N
R330 4.7K_0402_5%
2
1
2
1
R331 4.7K_0402_5%
<18> NB_REFCLK_P
<18> NB_REFCLK_N
E17
F17
F15
2 0_0402_5% NB_RESET# D8
A10
C10
C12
<18> HT_REFCLKP
<18> HT_REFCLKN
+1.8VS
AVDD1(NC)
AVDD2(NC)
AVDDDI(NC)
AVSSDI(NC)
AVDDQ(NC)
AVSSQ(NC)
D7
E7
+NB_PLLVDD
1
F12
E12
F14
G15
H15
H14
PAD
C25
C24
HT_REFCLKP
HT_REFCLKN
E11
F11
REFCLK_P/OSCIN(OSCIN)
REFCLK_N(PWM_GPIO3)
T2
T1
GFX_REFCLKP
GFX_REFCLKN
U1
U2
GPP_REFCLKP
GPP_REFCLKN
V4
V3
GPPSB_REFCLKP(SB_REFCLKP)
GPPSB_REFCLKN(SB_REFCLKN)
B9
A9
B8
A8
B7
A7
I2C_CLK
I2C_DATA
DDC_DATA0/AUX0N(NC)
DDC_CLK0/AUX0P(NC)
DDC_CLK1/AUX1P(NC)
DDC_DATA1/AUX1N(NC)
B10
STRP_DATA
G11
RSVD
Strap pin
C8
<15> AUX_CAL
+1.8VS
LCD_TXOUT0+
LCD_TXOUT0LCD_TXOUT1+
LCD_TXOUT-
A22
B22
A21
B21
B20
A20
A19
B19
< LVDS dual channel : channel 1 >
TXOUT_U0P(NC)
TXOUT_U0N(NC)
TXOUT_U1P(PCIE_RESET_GPIO3)
TXOUT_U1N(PCIE_RESET_GPIO2)
TXOUT_U2P(NC)
TXOUT_U2N(NC)
TXOUT_U3P(PCIE_RESET_GPIO5)
TXOUT_U3N(NC)
B18
A18
A17
B17
D20
D21
D18
D19
< LVDS dual channel : channel 2 >
TXCLK_LP(DBG_GPIO1)
TXCLK_LN(DBG_GPIO3)
TXCLK_UP(PCIE_RESET_GPIO4)
TXCLK_UN(PCIE_RESET_GPIO1)
B16
A16
D16
D17
VDDLTP18(NC)
VSSLTP18(NC)
A13
B13
+VDDLTP18
VDDLT18_1(NC)
VDDLT18_2(NC)
VDDLT33_1(NC)
VDDLT33_2(NC)
A15
B15
A14
B14
+VDDLT18
VSSLT1(VSS)
VSSLT2(VSS)
VSSLT3(VSS)
VSSLT4(VSS)
VSSLT5(VSS)
VSSLT6(VSS)
VSSLT7(VSS)
C14
D15
C16
C18
C20
E20
C22
LVDS_DIGON(PCE_TCALRP)
LVDS_BLON(PCE_RCALRP)
LVDS_ENA_BL(PWM_GPIO2)
LCD_TXOUT0+
LCD_TXOUT2-
<17>
<17>
<17>
<17>
<17>
<17>
LCD_TXCLK+
LCD_TXCLK-
LCD_TXCLK+ <17>
LCD_TXCLK- <17>
+1.8VS
+VDDLTP18
C153
2.2U_0603_6.3V4Z
L8
BLM18PG121SN1D_0603 1
1
+1.8VS
+VDDLT18
C156
C157
0.1U_0402_16V7K 4.7U_0805_10V4Z
2
E9
F7
G12
UMA_ENBKL
@R71
@
R71 1
L10
BLM18PG121SN1D_0603 1
1
UMA_ENVDD <17>
2 0_0402_5%
UMA_ENBKL <28>
UMA_INVT_PWM <17>
MIS.
TMDS_HPD(NC)
HPD(NC)
D9
D10
SUS_STAT#(PWM_GPIO5)
D12
THERMALDIODE_P
THERMALDIODE_N
AE8
AD8
TESTMODE
D13
TMDS_HPD
PAD
T9
SUS_STAT# <15,19>
R84 1
< Strap option pin or gate side-port memory IO >
2 1.8K_0402_5%
AUX_CAL(NC)
880MR1@ RS780M_FCBGA528
L9
2 BLM18PG121SN1D_0603
TXOUT_L0P(NC)
TXOUT_L0N(NC)
TXOUT_L1P(NC)
TXOUT_L1N(NC)
TXOUT_L2P(NC)
TXOUT_L2N(DBG_GPIO0)
TXOUT_L3P(NC)
TXOUT_L3N(DBG_GPIO2)
PART 3 OF 6
CRT/TVOUT
+AVDD1
PLL PWR
LVTM
+AVDD1
L3
2 BLM18PG121SN1D_0603
PM
+3VS
U3C
AVDD=100mA
CLOCKs
+VDDA18PCIEPLL
1
C154
< Dedicated power for the DAC which can affect display quality >
2.2U_0603_6.3V4Z
+1.8VS
R68
R366 1
2 300_0402_5% NB_PWRGD
2
+1.8VS
+1.8VS
2 1K_0402_1% CPU_LDT_REQ#
R980
2.2K_0402_5%
C1256
2 140_0402_1% UMA_CRT_R
R988
2 150_0402_1% UMA_CRT_G
R989
2 150_0402_1% UMA_CRT_B
<7,18> LDT_STOP#
U57
Y
NB_LDTSTOP#
NC7SZ08P5X_NL_SC70-5
0.1U_0402_16V7K
R987
1
R981
2
0_0402_5%
Compal Secret Data
2010-08-25
Issued Date
2010-08-25
Deciphered Date
Title

SCHEMATICS,MB A6843
Date:
Rev
B
401982
Sheet

E
12
of
40
U3D
MEM_A0(NC)
MEM_A1(NC)
MEM_A2(NC)
MEM_A3(NC)
MEM_A4(NC)
MEM_A5(NC)
MEM_A6(NC)
MEM_A7(NC)
MEM_A8(NC)
MEM_A9(NC)
MEM_A10(NC)
MEM_A11(NC)
MEM_A12(NC)
MEM_A13(NC)
AD16
AE17
AD17
MEM_BA0(NC)
MEM_BA1(NC)
MEM_BA2(NC)
W12
Y12
AD18
AB13
AB18
V14
MEM_RASb(NC)
MEM_CASb(NC)
MEM_WEb(NC)
MEM_CSb(NC)
MEM_CKE(NC)
MEM_ODT(NC)
V15
W14
MEM_CKP(NC)
MEM_CKN(NC)
AE12
AD12
SBD_MEM/DVO_I/F
PAR 4 OF 6
AB12
AE16
V11
AE15
AA12
AB16
AB14
AD14
AD13
AD15
AC16
AE13
AC14
Y14
MEM_COMPP(NC)
MEM_COMPN(NC)
MEM_DQ0/DVO_VSYNC(NC)
MEM_DQ1/DVO_HSYNC(NC)
MEM_DQ2/DVO_DE(NC)
MEM_DQ3/DVO_D0(NC)
MEM_DQ4(NC)
MEM_DQ5/DVO_D1(NC)
MEM_DQ6/DVO_D2(NC)
MEM_DQ7/DVO_D4(NC)
MEM_DQ8/DVO_D3(NC)
MEM_DQ9/DVO_D5(NC)
MEM_DQ10/DVO_D6(NC)
MEM_DQ11/DVO_D7(NC)
MEM_DQ12(NC)
MEM_DQ13/DVO_D9(NC)
MEM_DQ14/DVO_D10(NC)
MEM_DQ15/DVO_D11(NC)
AA18
AA20
AA19
Y19
V17
AA17
AA15
Y15
AC20
AD19
AE22
AC18
AB20
AD22
AC22
AD21
MEM_DQS0P/DVO_IDCKP(NC)
MEM_DQS0N/DVO_IDCKN(NC)
MEM_DQS1P(NC)
MEM_DQS1N(NC)
Y17
W18
AD20
AE21
MEM_DM0(NC)
MEM_DM1/DVO_D8(NC)
W17
AE19
IOPLLVDD18(NC)
IOPLLVDD(NC)
AE23
AE24
IOPLLVSS(NC)
AD23
MEM_VREF(NC)
AE18
+1.8VS
+1.1VS
B
880MR1@
RS780M_FCBGA528
Compal Secret Data
Issued Date
2010-08-25
Deciphered Date
2010-08-25
Title

SCHEMATICS,MB A6843
Date:
Rev
B
401982
Sheet
13
of
40
0.1U_0402_16V7K
4.7U_0805_10V4Z
0.1U_0402_16V7K
C1128
4.7U_0805_10V4Z
C185
0.1U_0402_16V7K
C190
0.1U_0402_16V7K
0.1U_0402_16V7K
C186
0.1U_0402_16V7K
C192
0.1U_0402_16V7K
+VDDA18PCIE
J10
P10
K10
M10
L10
W9
H9
T10
R10
Y9
AA9
AB9
AD9
AE9
U10
VDDA18PCIE_1
VDDA18PCIE_2
VDDA18PCIE_3
VDDA18PCIE_4
VDDA18PCIE_5
VDDA18PCIE_6
VDDA18PCIE_7
VDDA18PCIE_8
VDDA18PCIE_9
VDDA18PCIE_10
VDDA18PCIE_11
VDDA18PCIE_12
VDDA18PCIE_13
VDDA18PCIE_14
VDDA18PCIE_15
< 1.8V IO transform power >

F9
G9
AE11
AD11
+1.8VS
1
C197
1U_0402_6.3V4Z
VDD_MEM1(NC)
VDD_MEM2(NC)
VDD_MEM3(NC)
VDD_MEM4(NC)
VDD_MEM5(NC)
VDD_MEM6(NC)
VDD18_1
VDD18_2
VDD18_MEM1(NC)
VDD18_MEM2(NC)
880MR1@
VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8
VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
VDD33_1(NC)
VDD33_2(NC)
K12
J14
U16
J11
K15
M12
L14
L11
M13
M15
N12
N14
P11
P13
P14
R12
R15
T11
T15
U12
T14
J16
C171
C172
10U_0805_10V4Z
10U_0805_10V4Z
C163
0.1U_0402_16V7K
C1126
C162
C160
VDDHTTX_1
VDDHTTX_2
VDDHTTX_3
VDDHTTX_4
VDDHTTX_5
VDDHTTX_6
VDDHTTX_7
VDDHTTX_8
VDDHTTX_9
VDDHTTX_10
VDDHTTX_11
VDDHTTX_12
VDDHTTX_13
C174
AE25
AD24
AC23
AB22
AA21
Y20
W19
V18
U17
T17
R17
P17
M17
0.1U_0402_16V7K
+VDDHTTX
C178
< 1.8V IO power for PCI-E graphics, SB, and GPP interfaces >
0_0805_5%
C181
C177
+NB_CORE
< Core power >
VDD_CORE:GM=5A/PM=10A
C189
0.1U_0402_16V7K
C176
330U_D2E_2.5VM
C175
+1.1VS
C196
0.1U_0402_16V7K
10U_0805_10V4Z
+1.8VS
L15
C184
2A
2
4.7U_0805_10V4Z
0.1U_0402_16V7K
< IO power for HyperTransport transmit interface >
0_0805_5%
C1127
10U_0805_10V4Z
0.1U_0402_16V7K
C195
2 L44
0.1U_0402_16V7K
L14
0.1U_0402_16V7K
C183
2A
2
+1.1VS
VDDHTRX_1
VDDHTRX_2
VDDHTRX_3
VDDHTRX_4
VDDHTRX_5
VDDHTRX_6
VDDHTRX_7
0.1U_0402_16V7K
10U_0805_10V4Z
H18
G19
F20
E21
D22
B23
A23
1U_0402_6.3V4Z
+VDDHTRX
C161
C188
C170
0.1U_0402_16V7K
C169
1U_0402_6.3V4Z
C180
C164
0.1U_0402_16V7K
C173
0.1U_0402_16V7K
1U_0402_6.3V4Z
FBMA-L11-201209-221LMA30T_0805
1U_0402_6.3V4Z
0.1U_0402_16V7K
+VDDA11PCIE
VDDA_12=2.5A
C194
0_0805_5%
C179
< IO power for HyperTransport receive interface >
PART 5/6
C193
0.1U_0402_16V7K
C159
0.1U_0402_16V7K
C168
A6
B6
C6
D6
E6
F6
G7
H8
J9
K9
M9
L9
P9
R9
T9
V9
U9
C187
0.1U_0402_16V7K
C167
VDDPCIE_1
VDDPCIE_2
VDDPCIE_3
VDDPCIE_4
VDDPCIE_5
VDDPCIE_6
VDDPCIE_7
VDDPCIE_8
VDDPCIE_9
VDDPCIE_10
VDDPCIE_11
VDDPCIE_12
VDDPCIE_13
VDDPCIE_14
VDDPCIE_15
VDDPCIE_16
VDDPCIE_17
0.1U_0402_16V7K
L13
VDDHT_1
VDDHT_2
VDDHT_3
VDDHT_4
VDDHT_5
VDDHT_6
VDDHT_7
C182
4.7U_0805_10V4Z
C166
J17
K16
L16
M16
P16
R16
T16
0.1U_0402_16V7K
2A
C165
< Main IO power for PCI-E graphics, SB, and GPP interfaces >
U3E
+VDDHT
C191
< Digital IO power for HyperTransport interface >
0_0805_5%
0.1U_0402_16V7K
L11
0.1U_0402_16V7K
2A
2
+1.1VS
POWER
+NB_CORE
1
+
C1129
330U_2.5V_M
2 @
2
AE10
AA11
Y11
AD10
AB10
AC10
H11
H12
< 3.3V IO power >

+3VS
1
RS780M_FCBGA528
C198
0.1U_0402_16V4Z
C199
0.1U_0402_16V4Z
U3F
VSSAHT1
VSSAHT2
VSSAHT3
VSSAHT4
VSSAHT5
VSSAHT6
VSSAHT7
VSSAHT8
VSSAHT9
VSSAHT10
VSSAHT11
VSSAHT12
VSSAHT13
VSSAHT14
VSSAHT15
VSSAHT16
VSSAHT17
VSSAHT18
VSSAHT19
VSSAHT20
VSSAHT21
VSSAHT22
VSSAHT23
VSSAHT24
VSSAHT25
VSSAHT26
VSSAHT27
L12
M14
N13
P12
P15
R11
R14
T12
U14
U11
U15
V12
W11
W15
AC12
AA14
Y18
AB11
AB15
AB17
AB19
AE20
AB21
K11
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
880MR1@
PART 6/6
GROUND
A25
D23
E22
G22
G24
G25
H19
J22
L17
L22
L24
L25
M20
N22
P20
R19
R22
R24
R25
H20
U22
V19
W22
W24
W25
Y21
AD25
VSSAPCIE1
VSSAPCIE2
VSSAPCIE3
VSSAPCIE4
VSSAPCIE5
VSSAPCIE6
VSSAPCIE7
VSSAPCIE8
VSSAPCIE9
VSSAPCIE10
VSSAPCIE11
VSSAPCIE12
VSSAPCIE13
VSSAPCIE14
VSSAPCIE15
VSSAPCIE16
VSSAPCIE17
VSSAPCIE18
VSSAPCIE19
VSSAPCIE20
VSSAPCIE21
VSSAPCIE22
VSSAPCIE23
VSSAPCIE24
VSSAPCIE25
VSSAPCIE26
VSSAPCIE27
VSSAPCIE28
VSSAPCIE29
VSSAPCIE30
VSSAPCIE31
VSSAPCIE32
VSSAPCIE33
VSSAPCIE34
VSSAPCIE35
VSSAPCIE36
VSSAPCIE37
VSSAPCIE38
VSSAPCIE39
VSSAPCIE40
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
AE14
D11
G8
E14
E15
J15
J12
K14
M11
L15
RS780M_FCBGA528
Compal Secret Data
2010-08-25
Issued Date
A2
B1
D3
D5
E4
G1
G2
G4
H7
J4
R7
L1
L2
L4
L7
M6
N4
P6
R1
R2
R4
V7
U4
V8
V6
W1
W2
W4
W7
W8
Y6
AA4
AB5
AB1
AB7
AC3
AC4
AE1
AE4
AB2
2010-08-25
Deciphered Date
Title

SCHEMATICS,MB A6843
Date:
Rev
B
401982
Sheet

E
14
of
40
< RS880 VSYNC mux at CRT_VSYNC pull High to 3K >
< VSYNC : STRAP_DEBUG_BUS_GPIO_ENABLEb >

Enables the Test Debug Bus using GPIO.
R92
3K_0402_5%
@ 2
R93
3K_0402_5%
<12,16> UMA_CRT_VSYNC
+3VS
1 : Disable (RX881, RS880)

0 : Enable (RX881, RS880)
PIN: RS880--> VSYNC#
< DFT_GPIO[4:2] : STRAP_PCIE_GPP_CFG[2:0] >
< RS880 use register to control PCI-E configure >
These pin straps are used to configure PCI-E GPP mode.

000 : 00001
001 : 00010
010 : 01011
011 : 00100
100 : 01010
101 : 01100
111 : 01011
< SUS_SATA# : LOAD_EEPROM_STRAPS >
< RS880 SUS_STAT# >
Selects Loading of STRAPS from EPROM

1
<12> AUX_CAL
R85
150_0402_1%
1 : Bypass the loading of EEPROM straps and use Hardware Default Values
0 : I2C Master can load strap values from EEPROM if connected, or use default values if not connected
<12,19> SUS_STAT#
@ 2
RS880:SUS_STAT#
D1
1 CH751H-40PT_SOD323-2
PLT_RST# <12,18,23,24,28,29>
< HSYNC : STRAP_DEBUG_BUS_PCIE_ENABLEb >
< RS880 use HSYNC to enable SIDE PORT (internal pull high) >
RX881: Enables the Test Debug Bus using PCIE bus

<12,16> UMA_CRT_HSYNC
R94
3K_0402_5%
+3VS
1 : Disable ( Can still be enabled using nbcfg register access )

0 : Enable
RS880: Enables Side port memory ( RS780 use HSYNC#)
1. Disable (RS880)
0 : Enable (RS880)
Compal Secret Data
2010-08-25
Issued Date
2010-08-25
Deciphered Date
Title
Date:
SCHEMATICS,MB A6843
Rev
B
401982
Sheet

E
15
of
40
+5VS
+R_CRT_VCC
D7
< CRT CONNECTOR >
+CRT_VCC
F1
2 1.1A_6V_MINISMDC110F-2
2
1
1
@
RB491D_SOT23-3
C237
0.1U_0402_16V4Z
D19
DAN217_SC59 @
D20
DAN217_SC59 @
D21
DAN217_SC59
JCRT
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
RED_L
+3VS
D_DDCDATA
GREEN_L
<12> UMA_CRT_R
<12> UMA_CRT_G
R100
150_0402_1%
C239
6P_0402_50V8K
C240
6P_0402_50V8K
L22
2 NBQ100505T-800Y-N_2P
L23
2 NBQ100505T-800Y-N_2P
L24
2 NBQ100505T-800Y-N_2P
+CRT_VCC
VSYNC
GREEN_L
D_DDCCLK
BLUE_L
C241
6P_0402_50V8K
HSYNC
BLUE_L
RED_L
C242
6P_0402_50V8K
C243
6P_0402_50V8K
G
G
16
17
ALLTO_C10532-11505-L_15P-T
CONN@
C244
6P_0402_50V8K
R98
R99
140_0402_1% 150_0402_1%
2
<12> UMA_CRT_B
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
+CRT_VCC
2
2 0.1U_0402_16V4Z
R817
2 10K_0402_5%
<12,15> UMA_CRT_HSYNC
P
OE#
5
1
C245 1
D_HSYNC
L25 1
2 10_0402_5%
HSYNC
L26 1
2 10_0402_5%
VSYNC
U5
SN74AHCT1G125GW_SOT353-5
< SYNC SIGNAL >
+CRT_VCC
<12,15> UMA_CRT_VSYNC
P
OE#
5
1
C247
10P_0402_50V8J @
2
Y
C248
10P_0402_50V8J
D_VSYNC
4
U6
SN74AHCT1G125GW_SOT353-5
+CRT_VCC
+3VS
C255
R806
2K_0402_1%
Q32B
3 2N7002DW-T/R7_SOT363-6
R805
2K_0402_1%
2
1
<12> UMA_CRT_DATA
+3VS
R825
4.7K_0402_5%
R824
4.7K_0402_5%
D_DDCDATA
@
2
33P_0402_50V8K
< Display Data Channel >
+3VS
<12> UMA_CRT_CLK
C256
Q32A
6 2N7002DW-T/R7_SOT363-6
D_DDCCLK
33P_0402_50V8K
@
C251
470P_0402_50V8J
1
@
C252
470P_0402_50V8J
FOR EMI
4
Compal Secret Data
2010-08-25
Issued Date
2010-08-25
Deciphered Date
Title
Date:
SCHEMATICS,MB A6843
Rev
B
401982
Sheet

E
16
of
40
+LCD_VDD
2N7002DW-T/R7_SOT363-6
R896
100K_0402_5%
W=60mils
Inrush current = 0A
C262
0.1U_0402_16V7K
Q33B
ENVDD 5
Q4
AO3413_SOT23
C260
C259
2
R91
47K_0402_5%
0.1U_0402_16V7K
W=60mils
0.01U_0402_25V7K
1
2
LCD_TXOUT0+
LCD_TXOUT2LCD_TXCLK+
LCD_TXCLK-
Q33A
2N7002DW-T/R7_SOT363-6
<12>
<12>
<12>
<12>
<12>
<12>
<12>
<12>
R90
100K_0402_5%
+LCD_VDD
+3VS
W=20mils
D84
CAM@
0.1U_0402_16V4Z
2
+3VS_LVDS_CAM 1
1
2
2
1
R808
0_0603_5%
C265
3
JLVDS
AZ5125-02S.R7G
1 1
2
LCD_EDID_CLK <12>
2
USB20_P9_L
3 3
LCD_EDID_DATA <12>
4 4
USB20_N9_L
INT_MIC_CLK
5 5
INT_MIC_CLK <26>
6 6
INT_MIC_DATA
7 7
INT_MIC_DATA <26>
8 8
INVT_PWM
9 9
10 10
BKOFF#_R
BKOFF#
R983 2
11 11
1 33_0402_5%
BKOFF# <28>
12 12
13 13
<12> UMA_ENVDD
14 14
R200 1
15 15
2 10K_0402_5%
16 16
17 17
18 18
19 19
20
+3VS
20
21 21
2A
22 22
+LCDVDD_R
23 23
2 L12
1
+LCD_VDD
24 24
0_0805_5%
25 25
1
1
26 26
27 27
1
1
+LCD_INV
28 28
C266
C267
29 29
30 30
@ C152
C264
0.1U_0402_16V4Z
4.7U_0805_10V4Z
2
2
680P_0402_50V7K
0.1U_0402_16V4Z
31 GND1
2
2
EMI
32 GND2
CAM@
LCD/PANEL BD. Conn.
+3VS
R807
150_0603_5%
6 2
1
+3VS
ACES_87242-3001-09
CONN@
CAM@
1
2
R134
0_0402_5%
+LCD_INV
B+
L45
1
C268
68P_0402_50V8J
2
2
1
1 FBMA-L11-201209-221LMA30T_0805
@
C27
@ L20
1
<19> USB20_P9
<19> USB20_N9
USB20_P9_L
USB20_N9_L
WCM-2012-900T_0805
C263
0.1U_0402_25V6
2
1
R133
@
R23 1
10P_0402_50V8J
INT_MIC_CLK
2
10_0402_5%
Reserve C27, R231 for EMI
2
0_0402_5%
CAM@
R96
2 0_0402_5%
R897 1
2 0_0402_5%
INVT_PWM
<28> EC_INVT_PWM
R319
10K_0402_5%
2
<12> UMA_INVT_PWM
+3VS
LCD_EDID_CLK
2.2K_0402_5% 2
1 R117
LCD_EDID_DATA
2.2K_0402_5% 2
1 R118
Compal Secret Data
2010-08-25
Issued Date
2010-08-25
Deciphered Date
Title
Date:
SCHEMATICS,MB A6843
Rev
B
401982
Sheet

E
17
of
40
1
8.2K_0402_5%
M23
P23
PCIE_RCLKP/NB_LNK_CLKP
PCIE_RCLKN/NB_LNK_CLKN
NB_REFCLK_P
NB_REFCLK_N
U29
U28
NB_DISP_CLKP
NB_DISP_CLKN
HT_REFCLKP
HT_REFCLKN
T26
T27
NB_HT_CLKP
NB_HT_CLKN
V21
T21
CPU_HT_CLKP
CPU_HT_CLKN
V23
T23
SLT_GFX_CLKP
SLT_GFX_CLKN
<12> NB_REFCLK_P
<12> NB_REFCLK_N
+3VS
+1.8VS
<12> HT_REFCLKP
<12> HT_REFCLKN
<7> CLK_CPU_BCLK
<7> CLK_CPU_BCLK#
R329
4.7K_0402_5%
H_PWRGD_L <38>
Q21
<24> CLK_PCIE_LAN
<24> CLK_PCIE_LAN#
L29
L28
<23> CLK_PCIE_MCARD2
<23> CLK_PCIE_MCARD2#
N29
N28
GPP_CLK1P
GPP_CLK1N
M29
M28
GPP_CLK2P
GPP_CLK2N
T25
V25
GPP_CLK3P
GPP_CLK3N
L24
L23
GPP_CLK4P
GPP_CLK4N
P25
M25
GPP_CLK5P
GPP_CLK5N
P29
P28
GPP_CLK6P
GPP_CLK6N
N26
N27
GPP_CLK7P
GPP_CLK7N
T29
T28
GPP_CLK8P
GPP_CLK8N
L25
14M_25M_48M_OSC
FDV301N_NL_SOT23-3
level shift to ISL6265

ISL6265 PWROK input, TTL level: 0.8V~2.0V
25M_CLK_X1
1
2
C1254
27P_0402_50V8J
When this pin is high, the SVI interface is

active and I2C protocol is running. While this
pin is low, the SVC, SVD, and VFIXEN input
states determine the pre-PWROK metal VID or
VFIX mode voltage. This pin must be low prior
to the ISL6265 PGOOD output going high
Y6
25MHZ_20PF_7A25000012
R971
1M_0402_5%
1
2
C1255
27P_0402_50V8J
CLK_48M_CR
<25> CLK_48M_CR
25M_CLK_X2
4/26 Add test point T38 to T64 for debug
25M_CLK_X1
25M_CLK_X2
@ R332 20M_0402_5%
@R332
1
2
L27
2/23 Reserve R796 pull-down to CLKRUN#

1
R796
1
2
C586
NC
OSC
NC
BT_DET#
1
R260
BT_PWR#
LPCCLK0
LPCCLK1
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ0#
LDRQ1#/CLK_REQ6#/GPIO49
SERIRQ/GPIO48
ALLOW_LDTSTP/DMA_ACTIVE#
PROCHOT#
LDT_PG
LDT_STP#
LDT_RST#
H24
H25
J27
J26
H29
H28
G28
J25
AA18
AB19
2
8.2K_0402_5%
2
100K_0402_5%
+3VS
+3VS
CLK_PCI_EC <22,28>
CLK_PCI_SIO <22,29>
LPC_AD0 <28,29>
LPC_AD1 <28,29>
LPC_AD2 <28,29>
LPC_AD3 <28,29>
LPC_FRAME# <28,29>
SERIRQ <28,29>
G21
H21
K19
G22
J24 R26
2 0_0402_5%
32K_X1
C1
SB_32KHI
32K_X2
C2
SB_32KHO
RTCCLK
INTRUDER_ALERT#
VDDBT_RTC_G
D2
B2
B1
CPU_LDT_REQ# <12>
H_PROCHOT# <7>
H_PWRGD <7,38>
LDT_STOP# <7,12>
LDT_RST# <7>
7/2 Add Net RTCCLK for EC Crystal cost down
+RTCVCC
+RTCBATT
D8
RTCCLK <28>
C584 1
7/21 Change U8 P/N to SA00003IWA0 (A13)
1
2
R333
120_0402_5%
W=20mils
1 C585
1
R142
2
120_0402_5%
+3VL
R141
3
1
2
1K_0402_5%
CHN202UPT SC-70
J1
JUMP_43X39
C583
@
for Clear CMOS
7/22 Change D8 from DAN202U to CHN202UPT
Close to SB
SUYIN_060003HA002G202ZL
32.768KHZ_12.5PF_Q13MC14610002
SB_32KHO
@JRTC
@
JRTC
R335
20M_0603_5%
4
OSC
BT_PWR# <23>
BT_DET#
Y3
7/15 Add R260 pull up to +3VS
2
10K_0402_5%
R95
25M_X1
25M_X2
<22>
<20,22>
<22>
<22>
<22>
<22>
<22>
SB820MR1@
SB_32KHI
18P_0402_50V8J
L26
INTE#/GPIO32
INTF#/GPIO33
INTG#/GPIO34
INTH#/GPIO35
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
AJ6
AG6
AG4
AJ4
SB820M_FCBGA605
C582
GPP_CLK0P
GPP_CLK0N
CLOCK GENERATOR
<12> CLK_SBSRC_BCLK
<12> CLK_SBSRC_BCLK#
H_PWRGD
GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N
PLT_RST# <12,15,23,24,28,29>
AA22
Y21
AA25
AA24
W23
V24
W24
W25
AA1
AA4
AA3
AB1
AA5
AB2
AB6
AB5
AA6
AC2
AC3
AC4
AC1
AD1
AD2
AC6
AE2
AE1
AF8
AE3
AF1
AG1
AF2
AE9
AD9
AC11
AF6
AF4
AF3
AH2
AG2
AH3
AA8
AD5
AD8
AA10
AE8
AB9
AJ3
AE7
AC5
AF5
AE6
AE4
AE11
AH5
AH4
AC12
AD12
AJ5
AH6
AB12
AB11
AD7
GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
AD0/GPIO0
AD1/GPIO1
AD2/GPIO2
AD3/GPIO3
AD4/GPIO4
AD5/GPIO5
AD6/GPIO6
AD7/GPIO7
AD8/GPIO8
AD9/GPIO9
AD10/GPIO10
AD11/GPIO11
AD12/GPIO12
AD13/GPIO13
AD14/GPIO14
AD15/GPIO15
AD16/GPIO16
AD17/GPIO17
AD18/GPIO18
AD19/GPIO19
AD20/GPIO20
AD21/GPIO21
AD22/GPIO22
AD23/GPIO23
AD24/GPIO24
AD25/GPIO25
AD26/GPIO26
AD27/GPIO27
AD28/GPIO28
AD29/GPIO29
AD30/GPIO30
AD31/GPIO31
CBE0#
CBE1#
CBE2#
CBE3#
FRAME#
DEVSEL#
IRDY#
TRDY#
PAR
STOP#
PERR#
SERR#
REQ0#
REQ1#/GPIO40
REQ2#/CLK_REQ8#/GPIO41
REQ3#/CLK_REQ5#/GPIO42
GNT0#
GNT1#/GPO44
GNT2#/GPO45
GNT3#/CLK_REQ7#/GPIO46
CLKRUN#
LOCK#
0.1U_0402_16V4Z
PCIE_CALRP
PCIE_CALRN
AA28
AA29
Y29
Y28
Y26
Y27
W28
W29
V2
<22>
<22>
<22>
<22>
AD29
AD28
PCIRST#
PCI_CLK1
PCI_CLK2
PCI_CLK3
PCI_CLK4
U21
A_RX0P
A_RX0N
A_RX1P
A_RX1N
A_RX2P
A_RX2N
A_RX3P
A_RX3N
@
2
R328
A_RST#
0.1U_0402_16V4Z
2
1 590_0402_1%
1 2K_0402_1%
+3VALW
C581
2
2
AE24
AE23
AD25
AD24
AC24
AC25
AB25
AB24
W2
W1
W3
W4
Y1
R326
R327
+1.1VS_PCIE
A_TX0P
A_TX0N
A_TX1P
A_TX1N
A_TX2P
A_TX2N
A_TX3P
A_TX3N
PCICLK0
PCICLK1/GPO36
PCICLK2/GPO37
PCICLK3/GPO38
PCICLK4/14M_OSC/GPO39
AD26
AD27
AC28
AC29
AB29
AB28
AB26
AB27
Part 1 of 5
1U_0402_6.3V4Z
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N
SB_RX0P_C
SB_RX0N_C
SB_RX1P_C
SB_RX1N_C
SB_RX2P_C
SB_RX2N_C
SB_RX3P_C
SB_RX3N_C
SB800
PCIE_RST#
A_RST#
0.1U_0402_16V4Z
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
2
2
2
2
2
2
2
2
P1
L1
PCI INTERFACE
SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N
1
1
1
1
1
1
1
1
U8A
33_0402_5%
1
LPC
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
C579
C573
C574
C575
C576
C580
C577
C578
CPU
R325
2
RTC
2 150P_0402_50V8J
A_RST#
PCI CLKS
C572 1
PCI EXPRESS INTERFACES
18P_0402_50V8J
Compal Secret Data
2010-08-25
Issued Date
2010-08-25
Deciphered Date
Title

SCHEMATICS,MB A6843
Date:
Rev
B
401982
Sheet

E
18
of
40
7/2 Add D27 for abnormal shutdown RSMRST#

D27
SB_PWRGD
POK <33,35,36>
CH751H-40PT_SOD323-2
U8D
R351 1
R402 1
<26> AZ_SYNC_HD
<26> AZ_RST_HD#
2 33_0402_5%
2 33_0402_5%
2 33_0402_5%
2 33_0402_5%
GBE_COL
GBE_CRS
GBE_MDIO
+3VALW
GBE_MDIO
1
R358
1
R353
1
R356
10K_0402_5%
GBE_RXERR
GBE_COL
10K_0402_5%
GBE_RXERR
10K_0402_5%
+3VALW
GBE_PHY_INTR
GBE_CRS
10K_0402_5%
1
R354
CIR_EN#
R984
10K_0402_5%
1
R357
1
R359
1
R360
1
R361
1
R362
1
R363
2
100K_0402_5%
SB_SIC
2
2.2K_0402_5%
SB_SID
2
2.2K_0402_5%
H_THERMTRIP#
2
10K_0402_5%
SMB_CK_CLK1
2
2.2K_0402_5%
SMB_CK_DAT1
2
2.2K_0402_5%
CIR_EN#
@
R985
1K_0402_5%
H3
D1
E4
D4
E8
F7
E7
F8
BLINK/USB_OC7#/GEVENT18#
USB_OC6#/IR_TX1/GEVENT6#
USB_OC5#/IR_TX0/GEVENT17#
USB_OC4#/IR_RX0/GEVENT16#
USB_OC3#/AC_PRES/TDO/GEVENT15#
USB_OC2#/TCK/GEVENT14#
USB_OC1#/TDI/GEVENT13#
USB_OC0#/TRST#/GEVENT12#
M3
N1
L2
M2
M1
M4
N2
P2
AZ_BITCLK
AZ_SDOUT
AZ_SDIN0/GPIO167
AZ_SDIN1/GPIO168
AZ_SDIN2/GPIO169
AZ_SDIN3/GPIO170
AZ_SYNC
AZ_RST#
T1
T4
L6
L5
T9
U1
U3
T2
U2
T5
V5
P5
M5
P9
T7
P7
M7
P4
M9
V7
GBE_COL
GBE_CRS
GBE_MDCK
GBE_MDIO
GBE_RXCLK
GBE_RXD3
GBE_RXD2
GBE_RXD1
GBE_RXD0
GBE_RXCTL/RXDV
GBE_RXERR
GBE_TXCLK
GBE_TXD3
GBE_TXD2
GBE_TXD1
GBE_TXD0
GBE_TXCTL/TXEN
GBE_PHY_PD
GBE_PHY_RST#
GBE_PHY_INTR
E23
E24
F21
G29
PS2_DAT/SDA4/GPIO187
PS2_CLK/SCL4/GPIO188
SPI_CS2#/GBE_STAT2/GPIO166
FC_RST#/GPO160
D27
F28
F29
E27
PS2KB_DAT/GPIO189
PS2KB_CLK/GPIO190
PS2M_DAT/GPIO191
PS2M_CLK/GPIO192
SB820M_FCBGA605
SB820MR1@
+3VALW
EC_LID_OUT#
USB-8 WLAN
USB_HSD7P
USB_HSD7N
G12
G14
USB_HSD6P
USB_HSD6N
G16
G18
USB_HSD5P
USB_HSD5N
D16
C16
USB20_P5 <25>
USB20_N5 <25>
USB-5 Card Reader 2 IN 1
USB_HSD4P
USB_HSD4N
B14
A14
USB_HSD3P
USB_HSD3N
E18
E16
USB_HSD2P
USB_HSD2N
J16
J18
USB_HSD1P
USB_HSD1N
B17
A17
USB20_P1 <23>
USB20_N1 <23>
USB-1 Right side
USB_HSD0P
USB_HSD0N
A16
B16
USB20_P0 <23>
USB20_N0 <23>
USB-0 Right side
SCL2/GPIO193
SDA2/GPIO194
SCL3_LV/GPIO195
SDA3_LV/GPIO196
EC_PWM0/EC_TIMER0/GPIO197
D25
F23
B26
E26
F25
E22
F22
E21
KSI_0/GPIO201
KSI_1/GPIO202
KSI_2/GPIO203
KSI_3/GPIO204
KSI_4/GPIO205
KSI_5/GPIO206
KSI_6/GPIO207
KSI_7/GPIO208
G24
G25
E28
E29
D29
D28
C29
C28
KSO_0/GPIO209
KSO_1/GPIO210
KSO_2/GPIO211
KSO_3/GPIO212
KSO_4/GPIO213
KSO_5/GPIO214
KSO_6/GPIO215
KSO_7/GPIO216
KSO_8/GPIO217
KSO_9/GPIO218
KSO_10/GPIO219
KSO_11/GPIO220
KSO_12/GPIO221
KSO_13/GPIO222
KSO_14/GPIO223
KSO_15/GPIO224
KSO_16/GPIO225
KSO_17/GPIO226
B28
A27
B27
D26
A26
C26
A24
B25
A25
D24
B24
C24
B23
A23
D22
C22
A22
B22
2010-08-25
Issued Date
SB_SIC
SB_SID
+3VALW
GPIO199 <22>
GPIO200 <22>
GPIO201
GPIO202
GPIO203
GPIO204
GPIO205
STRAP PIN
@ R919
10K_0402_5%
+3VALW
GPIO201
GPIO202
GPIO203
R922
10K_0402_5%
@
GPIO204
GPIO205
R923
10K_0402_5%
R926
10K_0402_5%
Madison LP
GPIO204
GPIO205
Low
Low
Low
High
Park XT
High
Low
M92 XTX
High
None
2010-08-25
Deciphered Date
R924
1K_0402_1%
R925
1K_0402_1%
GPIO201
GPIO202
GPIO203
High
High
Nile-S
High
High
Low
Danube Marseille
Low
Low
Low
Danube Hamburg
Low
Low
High
Danube LC Marseille
Low
Low
High
High
Title

SCHEMATICS,MB A6843
@ R928
@R928
10K_0402_5%
High
Date:
R921
10K_0402_5%
Nile-M
A
@ R920
@R920
10K_0402_5%
R927
10K_0402_5%
@
Compal Secret Data
R345 1
R346 1
<26> AZ_BITCLK_HD
<26> AZ_SDOUT_HD
<22> HDA_SDOUT
<26> AZ_SDIN0_HD
GBE_PHY_INTR
2
10K_0402_5%
USB20_P8 <23>
USB20_N8 <23>
<23,28> USB_OC#0
USB-9 Int Camera
D13
C13
AZ_BITCLK_HD
<28> EC_LID_OUT#
1
R352
USB20_P9 <17>
USB20_N9 <17>
USB_HSD8P
USB_HSD8N
@R135
@
R135
2
1
10_0402_5%
A13
B13
1 10P_0402_50V8J
USB_HSD9P
USB_HSD9N
@ C143 2
J12
J14
<23> CLKREQ_MCARD2#
CLK_REQ4#/SATA_IS0#/GPIO64
SMARTVOLT1/SATA_IS2#/GPIO50
SATA_IS4#/FANOUT3/GPIO55
SATA_IS5#/FANIN3/GPIO59
SPKR/GPIO66
SCL0/GPIO43
SDA0/GPIO47
SCL1/GPIO227
SDA1/GPIO228
CLK_REQ2#/FANIN4/GPIO62
CLK_REQ1#/FANOUT4/GPIO61
IR_LED#/LLB#/GPIO184
SMARTVOLT2/SHUTDOWN#/GPIO51
DDR3_RST#/GEVENT7#
GBE_LED0/GPIO183
GBE_LED1/GEVENT9#
GBE_LED2/GEVENT10#
GBE_STAT0/GEVENT11#
CLK_REQG#/GPIO65/OSCIN
R107
10K_0402_5%
USB_HSD10P
USB_HSD10N
RSMRST#
HDMI_DET
<26> PCH_SPKR
SMB_CK_CLK0
SMB_CK_DAT0
SMB_CK_CLK1
SMB_CK_DAT1
E14
E12
<9,10>
<9,10>
<23>
<23>
USB_HSD11P
USB_HSD11N
R105
10K_0402_5%
@
F11
E11
<24> CLKREQ_LAN#
USB_HSD12P
USB_HSD12N
DEVICE
USB0(Right)
USB1(Right)
Card Reader
WLAN
Int Camera
AD19
AA16
AB21
AC18
AF20
AE19
AF19
AD22
AE22
F5
F4
AH21
AB18
E1
AJ21
H4
D5
D7
G5
K3
AA20
B12
A12
HDMI_DET
PORT
USB0
USB1
USB5
USB8
USB9
USB_HSD13P
USB_HSD13N
+3VS
USB PORT LIST
G1
<28> EC_RSMRST#
<7> H_THERMTRIP#
<12> NB_PWRGD
2
R338
<24> EC_SWI#
T20
SUS_STAT#
H9
J8
PAD
USB_RCOMP 1
11.8K_0402_1%
2 4.7K_0402_5%
USB_FSD0P/GPIO185
USB_FSD0N
USB OC
2 2.2K_0402_5% SMB_CK_DAT0
R344 1
J10
H11
EMBEDDED CTRL
R343 1
USB_FSD1P/GPIO186
USB_FSD1N
EMBEDDED CTRL
2 2.2K_0402_5% SMB_CK_CLK0
GATEA20
KB_RST#
EC_SCI#
EC_SMI#
HD AUDIO
R342 1
<28>
<28>
<28>
<28>
SB800
G19
+3VS
PAD
PAD
PAD
A10
USB_RCOMP
USB 1.1 USB MISC
T14
T12
T13
USBCLK/14M_25M_48M_OSC
USB 2.0
PM_SLP_S3#
PM_SLP_S5#
PBTN_OUT#
SB_PWRGD
SUS_STAT#
ACPI / WAKE UP EVENTS
<28>
<28>
<28>
<28>
<12,15>
PCI_PME#/GEVENT4#
RI#/GEVENT22#
SPI_CS3#/GBE_STAT1/GEVENT21#
SLP_S3#
SLP_S5#
PWR_BTN#
PWR_GOOD
SUS_STAT#
Part 4 of 5
TEST0
TEST1/TMS
TEST2
GA20IN/GEVENT0#
KBRST#/GEVENT1#
LPC_PME#/GEVENT3#
LPC_SMI#/GEVENT23#
GEVENT5#
SYS_RESET#/GEVENT19#
WAKE#/GEVENT8#
IR_RX1/GEVENT20#
THRMTRIP#/SMBALERT#/GEVENT2#
NB_PWRGD
GPIO
EC_RSMRST#
2
2.2K_0402_5%
GBE LAN
1
R339
J2
K1
D3
F1
H1
F2
H5
G6
B3
C4
F6
AD21
AE21
K2
J29
H2
J1
H6
F3
J6
AC19
Rev
B
401982
Sheet

E
19
of
40
U8B
<23> SATA_SRX_C_DTX_N0
<23> SATA_SRX_C_DTX_P0
AJ8
AH8
SATA_RX0N
SATA_RX0P
<23> SATA_STX_DRX_P1
<23> SATA_STX_DRX_N1
AH10
AJ10
SATA_TX1P
SATA_TX1N
<23> SATA_SRX_C_DTX_N1
<23> SATA_SRX_C_DTX_P1
AG10
AF10
SATA_RX1N
SATA_RX1P
AG12
AF12
SATA_TX2P
SATA_TX2N
AJ12
AH12
SATA_RX2N
SATA_RX2P
AH14
AJ14
SATA_TX3P
SATA_TX3N
AG14
AF14
SATA_RX3N
SATA_RX3P
AG17
AF17
SATA_TX4P
SATA_TX4N
AJ17
AH17
SATA_RX4N
SATA_RX4P
AJ18
AH18
SATA_TX5P
SATA_TX5N
AH19
AJ19
SATA_RX5N
SATA_RX5P
R364 2
R365 2
+1.1VS_SATA
1 1K_0402_1% SATA_CALRP
1 931_0402_1% SATA_CALRN
SATA_X1
SATA_X2
DO
DI
CLK
CS#
VCC
C445
0.1U_0402_16V4Z
HOLD
CS#
CLK
DI
AD11
SATA_ACT#/GPIO67
AD16
AC16
J5
E2
K4
K9
G2
SATA_X1
SATA_X2
SPI_DI/GPIO164
SPI_DO/GPIO163
SPI_CLK/GPIO162
SPI_CS1#/GPIO165
ROM_RST#/GPIO161
FC_OE#/GPIOD145
FC_AVD#/GPIOD146
FC_WE#/GPIOD148
FC_CE1#/GPIOD149
FC_CE2#/GPIOD150
FC_INT1/GPIOD144
FC_INT2/GPIOD147
AF28
AG29
AG26
AF27
AE29
AF29
AH27
FC_ADQ0/GPIOD128
FC_ADQ1/GPIOD129
FC_ADQ2/GPIOD130
FC_ADQ3/GPIOD131
FC_ADQ4/GPIOD132
FC_ADQ5/GPIOD133
FC_ADQ6/GPIOD134
FC_ADQ7/GPIOD135
FC_ADQ8/GPIOD136
FC_ADQ9/GPIOD137
FC_ADQ10/GPIOD138
FC_ADQ11/GPIOD139
FC_ADQ12/GPIOD140
FC_ADQ13/GPIOD141
FC_ADQ14/GPIOD142
FC_ADQ15/GPIOD143
AJ27
AJ26
AH25
AH24
AG23
AH23
AJ22
AG21
AF21
AH22
AJ23
AF23
AJ24
AJ25
AG25
AH26
FANOUT0/GPIO52
FANOUT1/GPIO53
FANOUT2/GPIO54
W5
W6
Y9
FANIN0/GPIO56
FANIN1/GPIO57
FANIN2/GPIO58
W7
V9
W8
TEMPIN0/GPIO171
TEMPIN1/GPIO172
TEMPIN2/GPIO173
TEMPIN3/TALERT#/GPIO174
TEMP_COMM
B6
A6
A5
B5
C7
VIN0/GPIO175
VIN1/GPIO176
VIN2/GPIO177
VIN3/GPIO178
VIN4/GPIO179
VIN5/GPIO180
VIN6/GBE_STAT3/GPIO181
VIN7/GBE_LED3/GPIO182
A3
B4
A4
C5
A7
B7
B8
A8
NC1
NC2
R43
2 150K_0402_5% +3VALW
1 D22
MEM_1V5
G27
Y2
VSS
MEM_1V5 is for gating the

glitch on PCI_AD24
2/23 Reserve MEM_1V5 circuit for unsupport DDR-1333

+3VS
DO
@ C688
2
MX25L1605DM2I-12G_SO8-200mil
1
5
0.1U_0402_16V4Z
@
R86
10_0402_5%
MEM_1V5
1
@R422
@
R422
2
0_0402_5%
@
C155
10P_0402_50V8J
1
@ R423
PCI_AD24
1 : VDDR=1.05V
0 : VDDR=0.9V
@U23
@
U23
Y
<18,22> PCI_AD24
ACIN <28,34>
1
@ R424
SATA_CALRP
SATA_CALRN
AH28
AG28
AF26
U47
20mils
1
AB14
AA14
FC_CLK
FC_FBCLKOUT
FC_FBCLKIN
SB820M_FCBGA605
SB820MR1@
+3VALW
Part 2 of 5
FLASH
SATA_TX0P
SATA_TX0N
SERIAL ATA
ODD
AH9
AJ9
HW MONITOR
HDD
SB800
<23> SATA_STX_DRX_P0
<23> SATA_STX_DRX_N0
SPI ROM
2
33_0402_5%
VDDR_SW <37>
2
2
0_0402_5%
@ C689
150P_0402_50V8J
For VDDR Voltage Switch, AMD suggest

4
Compal Secret Data
2010-08-25
Issued Date
2010-08-25
Deciphered Date
Title

SCHEMATICS,MB A6843
Date:
4/16 Change U47 from SA00002TO00 to SA00003FO00
Rev
B
401982
Sheet

E
20
of
40
U8E
+1.1VS_VDDC
510mA
1
R369
U8C
71mA
AF22
AE25
AF24
AC22
2
0_0402_5%
VDDIO_18_FC_1
VDDIO_18_FC_2
VDDIO_18_FC_3
VDDIO_18_FC_4
POWER
43mA
AE28
+VDDPL_3V_PCIE
+1.1VS_PCIE
L70
2
1
FBMA-L11-201209-221LMA30T_0805
+1.1VS
C604
C605
C606
C607
1
1
1
1
2
2
2
2
600mA
+VDDPL_3V_SATA
C610
C611
C612
C613
C614
1
1
1
1
1
2
2
2
2
2
VDDAN_11_PCIE_1
VDDAN_11_PCIE_2
VDDAN_11_PCIE_3
VDDAN_11_PCIE_4
VDDAN_11_PCIE_5
VDDAN_11_PCIE_6
VDDAN_11_PCIE_7
VDDAN_11_PCIE_8
22U_0805_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
AD14
VDDPL_33_SATA
AJ20
AF18
AH20
AG19
AE18
AD18
AE16
VDDAN_11_SATA_1
VDDAN_11_SATA_4
VDDAN_11_SATA_2
VDDAN_11_SATA_3
VDDAN_11_SATA_5
VDDAN_11_SATA_6
VDDAN_11_SATA_7
10U_0805_10V4Z
10U_0805_10V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
+1.1V_USB
L74
2
1
FBMA-L11-160808-221LMT 0603
+1.1VALW
C625 2
C626 2
VDDAN_33_USB_S_1
VDDAN_33_USB_S_2
VDDAN_33_USB_S_3
VDDAN_33_USB_S_4
VDDAN_33_USB_S_5
VDDAN_33_USB_S_6
VDDAN_33_USB_S_7
VDDAN_33_USB_S_8
VDDAN_33_USB_S_9
VDDAN_33_USB_S_10
VDDAN_33_USB_S_11
VDDAN_33_USB_S_12
200mA
C11
D11
CORE S0
1
2
2
2
2
22U_0805_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
V1
M10
C590
1
1
1
1
C596
C594
C597
C598
L69
2
1
FBMA-L11-201209-221LMA30T_0805
1
R372
1
R373
2
0_0402_5%
2
0_0402_5%
L7
L9
1
R374
2
0_0402_5%
VDDIO_GBE_S_1
VDDIO_GBE_S_2
M6
P8
1
R375
2
0_0402_5%
VDDAN_11_USB_S_1
VDDAN_11_USB_S_2
VDDIO_33_S_1
VDDIO_33_S_2
VDDIO_33_S_3
VDDIO_33_S_4
VDDIO_33_S_5
VDDIO_33_S_6
VDDIO_33_S_7
VDDIO_33_S_8
A21
D21
B21
K10
L10
J9
T6
T8
VDDCR_11_S_1
VDDCR_11_S_2
F26
G26
VDDIO_AZ_S
M8
VDDCR_11_USB_S_1
VDDCR_11_USB_S_2
A11
B11
VDDPL_33_SYS
M21
VDDPL_11_SYS_S
L22
VDDPL_33_USB_S
F19
VDDAN_33_HWM_S
VDDXL_33_S
1 2.2U_0603_6.3V4Z
1 0.1U_0402_16V4Z
+1.1VS_CKVDD
400mA
VDDCR_11_GBE_S_1
VDDCR_11_GBE_S_2
CORE S5
2
2
2
2
2
A18
A19
A20
B18
B19
B20
C18
C20
D18
D19
D20
E19
PLL
1
1
1
1
1
658mA
USB I/O
+AVDD_USB
L72
2
1
FBMA-L11-201209-221LMA30T_0805
C617
C618
C619
C620
C621
K28
K29
J28
K26
J21
J20
K21
J22
10U_0805_10V4Z
+1.1VS
1
2
2
2
2
+1.1VS
C595
External Clock, connect to +1.1VS

directly, no need thick trace
1
1
1
1
C600
C601
C602
C603
check can be removed?
D6
L20
32mA
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
1
1
2
2
C608
C609
+1.1VALW
C615 2
C616 2
113mA
1 1U_0402_6.3V4Z
1 1U_0402_6.3V4Z
TBD
+VDDIO_AZ
2
1
L73 FBMA-L11-160808-221LMT 0603
C622
1
2 10U_0805_10V4Z
47mA
62mA
17mA
+VDDPL_3V
C623
C624
+VDDPL_11V
1 0.1U_0402_16V4Z
1 0.1U_0402_16V4Z
2
2
+VDDPL_3V_USB
5mA
197mA
+3V_HWM
SB800
VSSIO_SATA_1
VSSIO_SATA_2
VSSIO_SATA_3
VSSIO_SATA_4
VSSIO_SATA_5
VSSIO_SATA_6
VSSIO_SATA_7
VSSIO_SATA_8
VSSIO_SATA_9
VSSIO_SATA_10
VSSIO_SATA_11
VSSIO_SATA_12
VSSIO_SATA_13
VSSIO_SATA_14
VSSIO_SATA_15
VSSIO_SATA_16
VSSIO_SATA_17
VSSIO_SATA_18
VSSIO_SATA_19
VSSIO_USB_1
VSSIO_USB_2
VSSIO_USB_3
VSSIO_USB_4
VSSIO_USB_5
VSSIO_USB_6
VSSIO_USB_7
VSSIO_USB_8
VSSIO_USB_9
VSSIO_USB_10
VSSIO_USB_11
VSSIO_USB_12
VSSIO_USB_13
VSSIO_USB_14
VSSIO_USB_15
VSSIO_USB_16
VSSIO_USB_17
VSSIO_USB_18
VSSIO_USB_19
VSSIO_USB_20
VSSIO_USB_21
VSSIO_USB_22
VSSIO_USB_23
VSSIO_USB_24
VSSIO_USB_25
VSSIO_USB_26
VSSIO_USB_27
VSSIO_USB_28
Y4
EFUSE
D8
VSSAN_HWM
M19
VSSXL
P21
P20
M22
M24
M26
P22
P24
P26
T20
T22
T24
V20
J23
VSSIO_PCIECLK_1
VSSIO_PCIECLK_2
VSSIO_PCIECLK_3
VSSIO_PCIECLK_4
VSSIO_PCIECLK_5
VSSIO_PCIECLK_6
VSSIO_PCIECLK_7
VSSIO_PCIECLK_8
VSSIO_PCIECLK_9
VSSIO_PCIECLK_10
VSSIO_PCIECLK_11
VSSIO_PCIECLK_12
VSSIO_PCIECLK_13
AJ2
A28
A2
E5
D23
E25
E6
F24
N15
R13
R17
T10
P10
V11
U15
M18
V19
M11
L12
L18
J7
P3
V4
AD6
AD4
AB7
AC9
V8
W9
W10
AJ28
B29
U4
Y18
Y10
Y12
Y11
AA11
AA12
G4
J4
G8
G9
M12
AF25
H7
AH29
V10
P6
N4
L4
L8
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
M20
VSSPL_SYS
+1.1VALW
+VDDCR_USB
197mA
Y14
Y16
AB16
AC14
AE12
AE14
AF9
AF11
AF13
AF16
AG8
AH7
AH11
AH13
AH16
AJ7
AJ11
AJ13
AJ16
A9
B10
K11
B9
D10
D12
D14
D17
E9
F9
F12
F14
F16
C9
G11
F18
D9
H12
H14
H16
H18
J11
J19
K12
K14
K16
K18
H19
+3VALW
check 220ohm bead
+3VALW
VDDAN_11_CLK_1
VDDAN_11_CLK_2
VDDAN_11_CLK_3
VDDAN_11_CLK_4
VDDAN_11_CLK_5
VDDAN_11_CLK_6
VDDAN_11_CLK_7
VDDAN_11_CLK_8
2
0_0805_5%
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
93mA
+1.1VS_SATA
L71
2
1
FBMA-L11-201209-221LMA30T_0805
567mA
+1.1VS
N13
R15
N17
U13
U17
V12
V18
W12
W18
VDDIO_33_GBE_S
VDDPL_33_PCIE
U26
V22
V26
V27
V28
V29
W22
W26
22U_0805_6.3V6M
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
VDDCR_11_1
VDDCR_11_2
VDDCR_11_3
VDDCR_11_4
VDDCR_11_5
VDDCR_11_6
VDDCR_11_7
VDDCR_11_8
VDDCR_11_9
VDDRF_GBE_S
3.3V_S5 I/O
1
R371
PCI/GPIO I/O
22U_0805_6.3V6M
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
CLKGEN I/O
2
2
2
GBE LAN
1
1
1
FLASH I/O
VDDIO_33_PCIGP_1
VDDIO_33_PCIGP_2
VDDIO_33_PCIGP_3
VDDIO_33_PCIGP_4
VDDIO_33_PCIGP_5
VDDIO_33_PCIGP_6
VDDIO_33_PCIGP_7
VDDIO_33_PCIGP_8
VDDIO_33_PCIGP_9
VDDIO_33_PCIGP_10
VDDIO_33_PCIGP_11
VDDIO_33_PCIGP_12
SERIAL ATA
C591
C592
C593
C599
Part 3 of 5
SB800
AH1
V6
Y19
AE5
AC21
AA2
AB4
AC8
AA7
AA9
AF7
AA19
PCI EXPRESS
131mA
+3VS
GROUND
+3VALW
+VDDLX_3V
2
1
L75 FBMA-L11-160808-221LMT 0603
C627 1
2 2.2U_0603_6.3V4Z
SB820M_FCBGA605
SB820MR1@
H23
H26
AA21
AA23
AB23
AD23
AA26
AC26
Y20
W21
W20
AE26
L21
K20
VSSIO_PCIECLK_14
VSSIO_PCIECLK_15
VSSIO_PCIECLK_16
VSSIO_PCIECLK_17
VSSIO_PCIECLK_18
VSSIO_PCIECLK_19
VSSIO_PCIECLK_20
VSSIO_PCIECLK_21
VSSIO_PCIECLK_22
VSSIO_PCIECLK_23
VSSIO_PCIECLK_24
VSSIO_PCIECLK_25
VSSIO_PCIECLK_26
VSSIO_PCIECLK_27
Part 5 of 5
SB820M_FCBGA605
+VDDPL_11V
+VDDPL_3V_PCIE
+3VS
+VDDPL_3V
+VDDPL_3V_USB
L76
2
1
FBMA-L11-160808-221LMT 0603
L80
2
1
FBMA-L11-160808-221LMT 0603
+1.1VALW
0.1U_0402_16V4Z
2
1
FBMA-L11-160808-221LMT 0603
1
C634
2.2U_0603_6.3V4Z
+VDDPL_3V_SATA
+3VS
+3V_HWM
+3VALW
L77
2
1
C628
+3VALW
+3VS
L79
C635
2.2U_0603_6.3V4Z
+VDDIO_AZ
C630
C629
2.2U_0603_6.3V4Z
0.1U_0402_16V4Z
L78
2
1
FBMA-L11-160808-221LMT 0603
1
0_0603_5%
C632
C631
2.2U_0603_6.3V4Z
0.1U_0402_16V4Z
C633
2.2U_0603_6.3V4Z
+3VALW
L81
4
2
1
FBMA-L11-160808-221LMT 0603
C636
0.1U_0402_16V4Z
1
C637
2.2U_0603_6.3V4Z
1
R376
1
R52
2
2
0_0402_5% +1.5VS
0_0402_5%
@
C638
2.2U_0603_6.3V4Z
For 3V AZ device
Compal Secret Data
2010-08-25
Issued Date
2010-08-25
Deciphered Date
Title
Date:
SCHEMATICS,MB A6843
Rev
B
401982
Sheet

E
21
of
40
REQUIRED STRAPS
PCI_CLK2
LOW POWER ALLOW PCIE WATCHDOG

MODE
GEN2
TIMER
ENABLE
PCI_CLK3
USE
DEBUG
STRAP
PCI_CLK4
Inter CLK
Gen Mode
LPC_CLK0
LPC_CLK1
EC
ENABLE
CLOCKGEN
ENABLE
DEFAULT
IGNORE
DEBUG
STRAP
+3VS
+3VS
+3VS
R380
10K_0402_5%
2
1
DEFAULT
R379
10K_0402_5%
2
1
DEFAULT
R378
10K_0402_5%
2
1
DEFAULT
R377
10K_0402_5%
2
1
+VDDIO_AZ
WATCHDOG
TIMER
DISABLE
Inter CLK
Gen Mode
EC
DISABLE
L,H = LPC ROM

L,L = FWH ROM
CLOCKGEN
DISABLE
Disable
DEFAULT
+3VS
+3VALW
+3VALW
+3VALW
<19> HDA_SDOUT
<18> PCI_CLK1
<18> PCI_CLK2
<18> PCI_CLK3
<18> PCI_CLK4
<18,28> CLK_PCI_EC
<18,29> CLK_PCI_SIO
<19> GPIO200
<19> GPIO199
USE FC PLL
USE DEFAULT
PCIE STRAPS
DISABLE PCI
MEM BOOT
PULL
LOW
BYPASS
PCI PLL
Check AD29,AD28 strap function
DEFAULT
DEFAULT
DEFAULT
DEFAULT
ENABLE ILA
AUTORUN
BYPASS
FC PLL
USE EEPROM
PCIE STRAPS
ENABLE PCI
MEM BOOT
<18>
<18>
<18>
<18>
<18>
<18,20>
<18>
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
check default
R401
2.2K_0402_5%
2
1
DISABLE ILA
AUTORUN
R400
2.2K_0402_5%
2
1
USE PCI
PLL
DEFAULT
PCI_AD23
R399
2.2K_0402_5%
2
1
PCI_AD24
R398
2.2K_0402_5%
2
1
PCI_AD25
R397
2.2K_0402_5%
2
1
PULL
HIGH
PCI_AD26
+3VS
R396
10K_0402_5%
2
1
R395
10K_0402_5%
2
1
DEBUG STRAPS
SB800 HAS 15K INTERNAL PU FOR PCI_AD[27:23]
R394
2.2K_0402_5%
2
1
+3VS
PCI_AD27
R393
2.2K_0402_5%
2
1
R392
10K_0402_5%
2
1
R391
10K_0402_5%
2
1
R390
10K_0402_5%
2
1
R389
10K_0402_5%
2
1
R388
10K_0402_5%
2
1
R387
10K_0402_5%
2
1
+3VALW
R386
10K_0402_5%
2
1
H,L = SPI ROM (Default )
DEFAULT
R382
10K_0402_5%
2
1
FORCE PCIE
GEN1
R381
10K_0402_5%
2
1
Performance
MODE
GPIO199
H,H = Reserved
Enable
DEFAULT
PULL
LOW
GPIO200
R385
2.2K_0402_5%
2
1
PCI_CLK1
Check Internal PU/PD
R384
10K_0402_5%
2
1
AZ_SDOUT
PULL
HIGH
R383
10K_0402_5%
2
1
Compal Secret Data
2010-08-25
Issued Date
2010-08-25
Deciphered Date
Title
Date:
SCHEMATICS,MB A6843
Rev
B
401982
Sheet

E
22
of
40
SATA HDD Conn.

+5VS
Place closely JHDD SATA CONN.
1.2A
1
C1247
10U_0805_10V4Z
C1248
0.1U_0402_16V4Z
C1249
0.1U_0402_16V4Z
C1250
0.1U_0402_16V4Z
SSD HDD need 400mA for 3V(PHISON)
+3VS
+3VS rail reserve for SSD

C1251
10U_0805_10V4Z
@
C1159
0.1U_0402_16V4Z
@
C1152
0.1U_0402_16V4Z
@
JHDD
GND
A+
AGND
BB+
GND
1
2
3
4
5
6
7
DP
+5V
+5V
MD
GND
GND
8
9
10
11
12
13
SATA_STX_C_DRX_P1
SATA_STX_C_DRX_N1
C1143 1
C1138 1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
SATA_SRX_DTX_N1
SATA_SRX_DTX_P1
C1137 1
C1136 1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
+5VS
+5VS
SATA_STX_DRX_P1 <20>
SATA_STX_DRX_N1 <20>
SATA_SRX_C_DTX_N1 <20>
SATA_SRX_C_DTX_P1 <20>
Place components closely ODD CONN.
1.1A
1
SANTA_206401-1_RV
CONN@
C1153 1
C1154 1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
SATA_SRX_DTX_N0
SATA_SRX_DTX_P0
C1155 1
C1156 1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
C1144
C1146
@
10U_0805_10V4Z 1U_0402_6.3V4Z
2
2
10U_0805_10V4Z
C1145
1
C1147
0.1U_0402_16V4Z
C1148
0.1U_0402_16V4Z
SATA_STX_DRX_P0 <20>
SATA_STX_DRX_N0 <20>
SATA_SRX_C_DTX_N0 <20>
SATA_SRX_C_DTX_P0 <20>
Reserve for EMI request
USB Port 0 & Port1
@ R828 0_0402_5%
1
2
L82
+3VS
10
D91
RCLAMP0524P.TCT~D
@
+5VS
W=60mils
1.4A
+5VALW
+USB_VCCA
U48
USB_EN#
1
2
3
4
GND VOUT
VIN VOUT
VIN VOUT
EN
FLG
<28> USB_EN#
8
7
6
5
2
C1157
<19> USB20_P0
<19> USB20_N0
C1158
4.7U_0805_10V4Z
2 @
2/23 Reserve D91 for ESD
USB20_P0_R
USB20_N0_R
<19> USB20_N1
@ R830 0_0402_5%
1
2
L83
1 1
2
USB20_N1_R
<19> USB20_P1
USB20_P1_R
USB_OC#0 <19,28>
SANTA_191201-1
CONN@
WCM-2012-900T_0805
1
2
@ R829 0_0402_5%
For EMI request

1
1000P_0402_50V7K
RT9715BGS_SO8
V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12
V12
V12
GND
GND
C1253
0.1U_0402_16V4Z
@
SATA_STX_C_DRX_P0
SATA_STX_C_DRX_N0
24
23
GND
GND
Close to JODD
Close to JHDD
1
2
3
4
5
6
7
GND
A+
AGND
BB+
GND
15
14
SATA ODD Conn

JODD
WCM-2012-900T_0805
1
2
@ R831 0_0402_5%
Slot#1 Half PCIe Mini Card-WLAN

2
1
JUMP_43X79
WLAN&BT Combo module circuits
+3V_WLAN
Short PJ27 for WLAN

CLKREQ_MCARD2#
1
@ R259
2
8.2K_0402_5%
BT
on module
BT
on module
Enable
Disable
BT_CRTL
BT_PWR#
+3V_WLAN
**If +3V_WLAN is +3VS, please

remove DM2
CM24
2
2
2
0.01U_0402_25V7K 4.7U_0805_10V4Z
CM20
CM22
47P_0402_50V8J
CM23
<18> BT_PWR#
W=40mils
W=40mils
BT_CTRL
CM19
2
2
2
0.01U_0402_25V7K 4.7U_0805_10V4Z
+USB_VCCA
+USB_VCCA
@ DM2
SUSP#
<28,31,37> SUSP#
CM17
For SED
0.1U_0402_16V4Z
1
1
CM18
CM21
47P_0402_50V8J
2
G
3
For SED
0.1U_0402_16V4Z
1
1
+3V_WLAN
+1.5VS
7/9 Mount L82,L83 ,Reserve R828,R830 for EMI request
D
QM1
BT@
S 2N7002_SOT23-3
+ C339
220U_6.3V_M
1
C340
0.1U_0402_16V4Z
C341
1000P_0402_50V7K
JUSB1
<11> PCIE_PTX_C_IRX_N2
<11> PCIE_PTX_C_IRX_P2
<11> PCIE_ITX_C_PRX_N2
<11> PCIE_ITX_C_PRX_P2
A
WLAN/ WiFi
+3V_WLAN
<28> E51_TXD
<28> E51_RXD
RM16 1
1
RM15
20_0402_5%
E51_RXD_R
2
0_0402_5%
Debug card using
53
GND1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
GND2
54
BT_CTRL R50
2 1K_0402_5% E51_RXD_R
C343
1000P_0402_50V7K
GND
GND
GND
GND
JUSB2
5
6
7
8
1
2
3
4
USB20_N1_R
USB20_P1_R
ALLTOP C107L8-10405-L
WL_OFF# <28>
PLT_RST# <12,15,18,24,28,29>
GND
GND
GND
GND
5
6
7
8
ALLTOP C107L8-10405-L
SMB_CK_CLK1 <19>
SMB_CK_DAT1 <19>
USB20_N8 <19>
USB20_P8 <19>
Issued Date
Compal Secret Data
2010-08-25
Deciphered Date
2010-08-25
Title
Size
FOX_AS0B226-S40N-7F
CONN@
Date:
VCC
DD+
GND
D10
@
PJDLC05_SOT23-3
D9
@
PJDLC05_SOT23-3
7/25 Add R50 for Intel Rainbow Peak module
PLT_RST#
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
VCC
DD+
GND
<18> CLK_PCIE_MCARD2#
<18> CLK_PCIE_MCARD2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
1
2
3
4
USB20_N0_R
USB20_P0_R
BT_CTRL
<19> CLKREQ_MCARD2#
7/25 Reserver DM2 for +3V_WLAN is +3VS
+3V_WLAN
1 A
C342
0.1U_0402_16V4Z
+1.5VS
1 A
JWLAN
2
@ PJ27
+3VS
SCHEMATICS,MB A6843
Document Number
Rev
B
401982
1
Sheet
23
of
40
UL1
<11> PCIE_PTX_C_IRX_P3
CL1
2 0.1U_0402_16V7K PCIE_PTX_IRX_P3
22
HSOP
<11> PCIE_PTX_C_IRX_N3
CL2
2 0.1U_0402_16V7K PCIE_PTX_IRX_N3
23
HSON
17
18
HSIP
HSIN
PCIE_ITX_C_PRX_P3
PCIE_ITX_C_PRX_N3
<11> PCIE_ITX_C_PRX_P3
<11> PCIE_ITX_C_PRX_N3
RL19
<19> CLKREQ_LAN#
YL1
LAN_X1
0_0402_5% CLKREQ_LAN#_R
16
CLKREQB
PLT_RST#
25
PERSTB
CLK_PCIE_LAN
CLK_PCIE_LAN#
19
20
REFCLK_P
REFCLK_N
<12,15,18,23,28,29> PLT_RST#
LAN_X2
<18> CLK_PCIE_LAN
<18> CLK_PCIE_LAN#
25MHZ_20PF_7A25000012
1
CL26
27P_0402_50V8J
2
CL27
27P_0402_50V8J
2
<19> EC_SWI#
+3VS
RL7
15K_0402_5%
RTL8111E
NC
NC
Pin15
NC
Pin38
1K ohm Pull-high
MDIP0
MDIN0
MDIP1
MDIN1
NC/MDIP2
NC/MDIN2
NC/MDIP3
NC/MDIN3
1
2
4
5
7
8
10
11
DVDD10
DVDD10
DVDD10
13
29
41
LAN_X2
44
CKXTAL2
EC_SWI#
28
LANWAKEB
ISOLATEB
26
ISOLATEB
DVDD33
DVDD33
27
39
14
15
38
NC/SMBCLK
NC/SMBDATA
GPO/SMBALERT
AVDD33
AVDD33
AVDD33
AVDD33
12
42
47
48
EVDD10
21
2 1K_0402_5%
1
2
2
RTL8105E
Pin14
30
32
CKXTAL1
+LAN_VDDREG
ISOLATEB
EECS/SCL
EEDI/SDA
43
ENSWREG
RL6
1K_0402_1%
@
31
37
40
LAN_X1
RL22 1
+3V_LAN
LED3/EEDO
LED1/EESK
LED0
1
RL5
2
2.49K_0402_1%
10K ohm PD
33
ENSWREG
34
35
VDDREG
VDDREG
46
RSET
24
49
GND
PGND
LL1,CL13 will be changed to

2.2uH&4.7uF after EVT test
RL2
RL1
1 10K_0402_5%
1 10K_0402_5%
2
2
LAN_MDI0+
LAN_MDI0LAN_MDI1+
LAN_MDI1-
3
6
9
45
REGOUT
36
+3VALW TO +3V_LAN
2
1
1
3
1
PJ28
JUMP_43X39
@
+3V_LAN
0.1U_0402_16V4Z
CL17
0.1U_0402_16V4Z
1
CL3
10U_0805_10V4Z
2 @
CL7
10U_0805_10V4Z
1
CL8
1U_0402_6.3V4Z
4.7U_0805_10V4Z
CL15
EC_SWI#
+LAN_EVDD10
0.1U_0402_16V4Z
+LAN_VDD10
0.1U_0402_16V4Z
+3V_LAN
+LAN_VDDREG
8105E_VB@
2
1
0_0603_5%
LL3
UL1
+LAN_REGOUT
CL28
8105E_VB@
4.7U_0603_6.3V6K
0.1U_0402_16V4Z
2
CL19
2
CL20
2
CL21
2
CL22
1
1
1
CL29
8105E_VB@
0.1U_0402_16V4Z
1
LAN Conn.
+3V_LAN
RL4
8105E_VB@
0_0402_5%
change connector to w/o LED

(use NPVAA LAN conn. before LAN symol ready)
ENSWREG
JLAN CONN@
RL23
8105E_VC@
0_0402_5%
PR4-
PR4+
PR2-
PR3-
PR3+
RJ45_MIDI1+
PR2+
RJ45_MIDI0-
PR1-
RJ45_MIDI0+
PR1+
1 10K_0402_5%
1 10K_0402_5%
WOL_EN#
ISOLATEB
@ RL11
0_0402_5%
RL12
0_0402_5%
8/7 Chagne UL4 from NS681680 to NS681695

<28> WOL_EN
UL4
LAN_MDI0LAN_MDI0+
Place these components

colsed to LAN chip
TX+
TXCT
NC
NC
CT
RX+
RX-
16
15
14
13
12
11
10
9
RJ45_MIDI1RJ45_MIDI1+
RJ45_MIDI0RJ45_MIDI0+
CL41 1000P_0402_50V7K
2
1
1
RL15
2
75_0402_1%
1
RL13
2
75_0402_1%
RJ45_GND
RJ45_GND
1
CL36
SHLD2
10
LANGND
2 1000P_1808_3KV7K
1
7/23 Chagne UL4 from LF-H1201P-2 to NS681680
CL34
0.1U_0402_25V6
SHLD1
SANTA_130452-C
CL42 1000P_0402_50V7K
2
1
NS681610
TD+
TDCT
NC
NC
CT
RD+
RD-
1
2
3
4
5
6
7
8
LAN_MDI1LAN_MDI1+
8105E_VC@
@RL10
@
RL10 2
@RL3
@
RL3
+LAN_VDD10
RJ45_MIDI13
Close to Pin 3,6,9,13,29,41,45
0.1U_0402_16V4Z
+3V_LAN
CLKREQ_LAN#_R
2
CL10
2
CL4
2
CL5
2
CL6
Close to Pin 21
+3V_LAN
<28> WOL_EN#
CL12
0.1U_0402_16V7K
QL1
@
1
1
2
2
RL16
47K_0402_5%
@
1
@
AO3413_SOT23
CL14
0.01U_0402_25V7K
@
2
1
LL2
CL18
1U_0402_6.3V4Z
7/16 For LDO mode :

1. Remove RL4, mount RL23.
2. Remove LL1, CL13, CL9, LL3, CL28, CL29.
0.1U_0402_16V4Z
+LAN_EVDD10
+3V_LAN
Vgs=-4.5V,Id=3A,Rds<97mohm
RL25
100K_0402_5%
@
+LAN_VDD10
7/16 Change UL1 from RTL8105E-VB (SA00003PO10)

to RTL8105E-VC (SA00003PO20)
+3VALW
CL9
8105E_VB@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
RTL8105E-VB QFN _6X6

8105E_VB@
+3VALW
0.1U_0402_16V4Z
+LAN_VDD10
+3V_LAN
Close to Pin 27,39,12,47,48
1
Layout Note: LL1 must be
CL13
within 200mil to Pin36,
8105E_VB@
CL13,CL9 must be within
4.7U_0603_6.3V6K
2
200mil to LL1
+LAN_REGOUT: Width =60mil
2
0_0603_5%
AVDD10
AVDD10
AVDD10
AVDD10
+LAN_VDD10
LL1 8105E_VB@
+LAN_REGOUT
1
2
2.2UH +-5% NLC252018T-2R2J-N
CL37
120P_0402_ 50VJ
4.7U_0603_6.3V6K
D13
8/7 Chagne UL4 from NS681680 to NS681695
CL38
PJDLC05_SOT23-3
Compal Secret Data
2010-08-25
Issued Date
Deciphered Date
2010-08-25
Title

SCHEMATICS,MB A6843
Date:
Rev
B
401982
Sheet
E
24
of
40
@ CC2
1
2 100P_0402_50V8J
RC1
6.19K_0402_1%
2
1
UC1
2
0_0603_5%
DM
DP
+V1_8
4
5
6
3V3_IN
CARD_3V3
V18
XD_CD#
+VCC_3IN1
CC1
4.7U_0805_10V4Z
CC3
CC4
1U_0402_6.3V4Z
SDWP_MSCLK
8
9
10
11
12
SD_DATA1
SD_DATA0
SP1
SP2
SP3
SP4
SP5
25
0.1U_0402_16V4Z
1
RC4
+3VS
REFE
2
3
EPAD
<19> USB20_N5
<19> USB20_P5
+3VS_CR
1
USB20_N5
USB20_P5
GPIO0
17
CLK_IN
24
XD_D7
23
SP14
SP13
SP12
SP11
SP10
SP9
SP8
SP7
SP6
22
21
20
19
18
16
15
14
13
CLK_48M_CR_R
1
RC5
2
0_0402_5%
CLK_48M_CR <18>
< 48MHz >
SD_DATA2_MS_DATA5
MS_DATA1_SD_DATA3
SDCMD
MS_DATA2_SDCLK
1
RC6
2 MS_DATA2_SDCLK_R
0_0402_5%
SDCD#
RTS5137-GR QFN 24P_4X4

2
8/6 Change Net name from v1_8 to +V1_8

7/16 Change UC1 from RTS5138 (SA000030600) to RTS5137 (SA000043500)
for EMI request
@CC7
@
CC7
10P_0402_50V8J
@CC8
@
CC8
10P_0402_50V8J
@CC9
@
CC9
10P_0402_50V8J
@RC2
@
RC21
MS_DATA2_SDCLK
10_0402_5%
@RC3
@
RC31
SDWP_MSCLK
10_0402_5%
@RC7
@
RC71
CLK_48M_CR_R
10_0402_5%
< 2 in 1 Card Reader >

JREAD
1
2
3
4
5
6
MS_DATA1_SD_DATA3
SDCMD
D0
D1
D2
WP
CD
7
8
9
10
11
SD_DATA0
SD_DATA1
SD_DATA2_MS_DATA5
SDWP_MSCLK
SDCD#
GND1
GND2
GND3
GND4
12
13
14
15
D3
CMD
VSS1
VDD
CLK
VSS2
+VCC_3IN1
MS_DATA2_SDCLK_R
1
CC5
0.1U_0402_16V4Z
CC6
1U_0402_6.3V4Z
TAITW_PSDAT3-09GLAS1N14N
CONN@
Issued Date
Compal Secret Data
2010-08-25
Deciphered Date
2010-08-25
Title
Size
Date:
SCHEMATICS,MB A6843
Document Number
Rev
B
401982
D
Sheet
25
of
40
Codec
0.1U_0402_16V4Z
1
1
CA57
2
CA2
CA1
10U_0805_10V4Z
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
+AVDD
CA7
10U_0805_10V4Z
2
2
<27> MIC1_R_R
INT_MIC_CLK
CA21
1
2
4.7U_0805_10V4Z
1
CA22
INT_MIC_DATA
<17> INT_MIC_DATA
<17> INT_MIC_CLK
4.7U_0805_10V4Z
2
RA48 CAM@
FBMA-10-100505-301T
CA28
27P_0402_50V8J
<28> EC_MUTE#
@
EC_MUTE#
MONO_IN
2
100P_0402_50V8J
1
CA12
SENSE_A
1
2
CA15
2.2U_0603_6.3V4Z
+MIC1_VREFO_L
CA47 1
2 0.1U_0603_50V7K
CA48 1
2 0.1U_0603_50V7K
CA49 1
2 0.1U_0603_50V7K
CA50 1
2 0.1U_0603_50V7K
1
RA27
Sense Pin
Impedance
2
10U_0805_10V4Z
10U_0805_10V4Z 0.1U_0402_16V4Z 1
2
0_0603_5%
25
SPK_OUT_R+
SPK_OUT_R-
45
44
21
22
MIC1_L
MIC1_R
16
17
MIC2_L
MIC2_R
HP_OUT_L
HP_OUT_R
GPIO0/DMIC_DATA
GPIO1/DMIC_CLK
PD#
RESET#
12
PCBEEP
13
SENSE A
CA3
CA4
CA5
PCI Beep
10
BCLK
SDATA_OUT
SDATA_IN
EAPD
47
SPDIFO
48
MONO_IN
0.1U_0402_16V4Z
CA6
place close to chip
1
RA12
10K_0402_5%
CA18
0.1U_0402_16V4Z
SPKR+ <27>
SPKR- <27>
RA4
RA5
75_0402_1%
75_0402_1%
HP_L <27>
HP_R <27>
AZ_SYNC_HD
<19>
AZ_BITCLK_HD <19>
AZ_SDOUT_HD <19>
AZ_SDIN0_HD_R
2
RA6
1
33_0402_5%
AZ_SDIN0_HD
<19>
place close to chip
MONO_OUT
20
MIC2_VREFO
29
+MIC2_VREFO
30
28
+MIC1_VREFO_R CA23 10U_0805_10V4Z

1
2
SENSE B
CA13
1
2
RA8
1
2
47K_0402_5%
<19> PCH_SPKR
+5VS
SPKL+ <27>
SPKL- <27>
32
33
SYNC
RA7
1
2
47K_0402_5%
<28> EC_BEEP#
36
CBP
MIC1_VREFO_R
LDO_CAP
35
CBN
VREF
27
AC_VREF
AC_JDREF2 RA9
1
CA14
31
MIC1_VREFO_L
JDREF
19
43
42
49
7
PVSS2
PVSS1
DVSS2
DVSS1
CPVEE
34
AVSS1
AVSS2
26
37
+MIC1_VREFO_R
1
1 20K_0402_1%
1
2
2.2U_0603_6.3V4Z
CA17
2
0.1U_0402_16V4Z
+MIC1_VREFO_L
@
CA52
1U_0402_6.3V4Z
+MIC2_VREFO
@
CA51
1U_0402_6.3V4Z
@
CA46
1U_0402_6.3V4Z
B
CA16
10U_0805_10V4Z
2 @
ALC259-GR_QFN48_7X7
place close to chip
DGND
AGND
2
0_0603_5%
Codec Signals
Function
39.2K
PORT-I (PIN 32, 33)
Headphone out
20K
PORT-B (PIN 21, 22)
Ext. MIC
10K
PORT-C (PIN 23, 24)
place close to chip
<27> NBA_PLUG
5.1K
46
39
SPK_OUT_L+
SPK_OUT_L-
LINE2_L
LINE2_R
<27> MIC_SENSE
SENSE A
PVDD2
PVDD1
LINE1_L
LINE1_R
14
15
18
EC control EC_MUTE# behavior:

High-state / low-state
EC Beep
0.1U_0402_16V4Z
+5VS
1
1
CA62
@
@
CA58
2
2
2
2
10U_0805_10V4Z 0.1U_0402_16V4Z
40
41
RA22
4.7K_0402_5%
UA1
23
24
11
<19> AZ_RST_HD#
EC_MUTE#
RA11
1
2
0_0603_5%
1
@
CA63
2
10U_0805_10V4Z
68 mA
DVDD
Ext. Mic
<27> MIC1_R_L
Beep sound
RA3
CA8
35 mA
2
1
0_0603_5%
2
10U_0805_10V4Z
+PVDD2
1
CA61
DVDD_IO
+3VS
place close to chip
+3VS_DVDD
place close to chip

RA1
2
10U_0805_10V4Z
@
2
RA20 0_0603_5%
JA1
JUMP_43X39
+DVDD_IO
+5VS
CA43
+1.5VS
0.1U_0402_16V4Z
38
2
RA19 0_0603_5%
0.1U_0402_16V4Z
1
1
CA44
CA56
AVDD2
AVDD1
+3VS
D
RA2
1
2
0_0603_5%
600 mA
+PVDD1
2
RA10
1
20K_0402_1%
RA21
39.2K_0402_1%
SENSE_A
(PIN 48)
SENSE B
39.2K
PORT-E (PIN 14, 15)
20K
PORT-F (PIN 16, 17)
10K
PORT-H (PIN 20)
Compal Secret Data
2010-08-25
Issued Date
Deciphered Date
2010-08-25
Title
Size
Date:
SCHEMATICS,MB A6843
Document Number
Rev
B
401982
Sheet
1
26
of
40
Speaker Connector
D
placement near Audio Codec

RA30
2
1
0_0603_5%
SPK_L1
1
CA31
@ 10U_0805_10V4Z
2
@DA5
@
DA5
2
1
CA33
@ 10U_0805_10V4Z
RA34
2
2
1
0_0603_5%
SPKL-
<26> SPKL-
CA32
1U_0402_6.3V4Z
@
SPKR+
2
1
0_0603_5%
JSPK
SPK_L1
SPK_L2
SPK_R1
SPK_R2
SPK_L2
SPKR-
<26> SPKR-
ACES_85204-0400N
CONN@
CA53
100P_0402_50V8J
CA54
100P_0402_50V8J
1
2
6
3
3
6
2
1
+MIC1_VREFO_L
C
10
9
8
7
FOX_JA63331-B39S4-7F
CONN@
1
3
MIC1_L
1 RA29
2.2K_0402_5%
4
LA101
2 HP_R_L
KC FBM-L11-160808-121LMT 0603
LA121
2 HP_L_L
KC FBM-L11-160808-121LMT 0603
+MIC1_VREFO_R
MIC1_R
JLINE
<26> NBA_PLUG
<26> HP_L
2
1
1K_0402_5%
RA32
1 RA31
2.2K_0402_5%
SPK_R2
<26> HP_R
RA33
1K_0402_5%
2
1
<26> MIC1_R_R
CA35
1U_0402_6.3V4Z
@
HeadPhone/LINE Out JACK

B
1
2
3
4
<26> MIC1_R_L
2
1
CA36
@ 10U_0805_10V4Z
RA24
2
2
1
0_0603_5%
1
2
3
4
@DA10
@
DA10 AZ5125-02S.R7G
3
1
2
SPK_R1
CA34
@ 10U_0805_10V4Z
2
Ext.MIC/LINE IN JACK
RA23
<26> SPKR+
AZ5125-02S.R7G
2
7
8
GND
GND
SPKL+
<26> SPKL+
CA11 @
2
0.1U_0402_16V4Z
DA8 @
PJDLC05_SOT23-3
7/23 Change JLINE/JEXMIC to FOX_JA6331-B39S4-7F for DFX
For EMI
Ext.MIC/LINE IN JACK
JEXMIC
MIC1_L
LA8 1
2 MIC1_L_R
KC FBM-L11-160808-121LMT 0603
LA131
2 MIC1_L_L
KC FBM-L11-160808-121LMT 0603
3
6
2
1
1
2
6
3
MIC1_R
<26> MIC_SENSE
7
8
GND
GND
10
9
8
7
FOX_JA63331-B39S4-7F
CONN@
3
1
2
CA55
100P_0402_50V8J
CA59
100P_0402_50V8J
DA9 @
PJDLC05_SOT23-3
CA30 @
2
0.1U_0402_16V4Z
Compal Secret Data
For EMI
2010-08-25
Issued Date
Deciphered Date
2010-08-25
Title

SCHEMATICS,MB A6843
Date:
Rev
B
401982
Sheet
1
27
of
40
+3VL
+3VL
C1191
0.1U_0402_16V4Z
C1193
2
2
0.1U_0402_16V4Z
C1194
1
1
1000P_0402_50V7K
U52
0.1U_0402_16V4Z
1
R855
@ 10_0402_5%
2
1
C1196
@ 10P_0402_50V8J
GATEA20
<19> GATEA20
<19> KB_RST#
<18,29> SERIRQ
<18,29> LPC_FRAME#
<18,29> LPC_AD3
<18,29> LPC_AD2
<18,29> LPC_AD1
<18,29> LPC_AD0
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
CLK_PCI_EC
PLT_RST#
ECRST#
EC_SCI#
<18,22> CLK_PCI_EC
<12,15,18,23,24,29> PLT_RST#
+3VL
R859
47K_0402_5%
2
1
2
C1197
<19> EC_SCI#
1
2
3
4
+3VS
8
7
6
5
BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43
63
64
65
66
75
76
DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F
68
70
71
72
PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F
83
84
85
86
87
88
DA Output
PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A
to avoid EC entry ENE test mode
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D
6
14
15
16
17
18
19
25
28
29
30
31
32
34
36
KSO2
<33>
<33>
<7>
<7>
AD
SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47
KSO1
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
MISC
77
78
79
80
+3VL
21
23
26
27
EC_BEEP#
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49
PS2 Interface
BATT_TEMPA <33>
R208
2 100K_0402_5%
ADP_V
ADP_V <34>
EN_DFAN1
IREF
CHGVADJ
ADP_I <34>
C387
2 0.22U_0603_16V4Z
EN_DFAN1 <5>
IREF <34>
CHGVADJ <34>
EC_MUTE#
USB_EN#
EC_MUTE# <26>
USB_EN# <23>
TP_CLK
TP_DATA
+5VS
TP_CLK <30>
TP_DATA <30>
SDICS#/GPXOA00
SDICLK/GPXOA01
SDIDO/GPXOA02
SDIDI/GPXID0
97
98
99
109
VGATE
WOL_EN#
VLDT_EN
LID_SW#
SPIDI/RD#
SPIDO/WR#
SPICLK/GPIO58
SPICS#
119
120
126
128
EC_SI_SPI_SO
EC_SO_SPI_SI
SPI_CLK
SPI_CS#
CIR_RX/GPIO40
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59
73
74
89
90
91
92
93
95
121
127
SM Bus
EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
GPO
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11
100
101
102
103
104
105
106
107
108
PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7
110
112
114
115
116
117
118
V18R
124
1
R861
TP_DATA
1
R863
VGATE <31,38>
WOL_EN# <24>
VLDT_EN <31>
LID_SW# <29>
SPI Device Interface
GPIO
ACOFF <32,34>
BATT_TEMPA
TP_CLK
SPI Flash ROM
2
100P_0402_50V8J
2
100P_0402_50V8J
EC_BEEP# <26>
ACOFF
PWM Output
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
KSO[0..17]
RP1
INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13
55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82
2
47K_0402_5%
2
47K_0402_5%
GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC &
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
KSI[0..7]
<29> KSI[0..7]
<29> KSO[0..17]
+3VL
12
13
37
20
38
ECRST#
1
0.1U_0402_16V4Z
1
R862
1
R864
1
2
3
4
5
7
8
10
BATT_TEMPA
1
C1187
ACIN_D
1
C1189
AVCC
CLK_PCI_EC
D
C1188
1
2
C1195
1000P_0402_50V7K
VCC
VCC
VCC
VCC
VCC
VCC
for EMI request
C1192
67
0.1U_0402_16V4Z
1
2
9
22
33
96
111
125
C1190
0.1U_0402_16V4Z
1
1
2
4.7K_0402_5%
2
4.7K_0402_5%
+3VALW
FSTCHG
BATT_FULL_LED#
CAPS_LED#
BATT_CHG_LOW_LED#
SYSON
VR_ON
ACIN_D
EC_SI_SPI_SO <29>
EC_SO_SPI_SI <29>
SPI_CLK <29>
SPI_CS# <29>
LID_SW#
2
47K_0402_5%
SYSON
FSTCHG <34>
BATT_FULL_LED# <30>
CAPS_LED# <29>
BATT_CHG_LOW_LED# <30>
+3VL
1
R865
1
2
R866 4.7K_0402_5%
R867 330K_0402_5%
1
2
D26
ACIN_D
SYSON <31,36>
VR_ON <31,38>
ACIN <20,34>
2.2K_0804_8P4R_5%
7/7 Change WOL_EN from pin 103 to pin 17

EC_INVT_PWM
FAN_SPEED1
<17> EC_INVT_PWM
<5> FAN_SPEED1
7/6 For Power LED PWM function

R872
CRY1
2CRY2
E51_TXD
E51_RXD
ON/OFFBTN#
PWR_LED#
NUM_LED#
<23> E51_TXD
<23> E51_RXD
<30> ON/OFFBTN#
<30> PWR_LED#
<29> NUM_LED#
GPI
10M_0402_5%
@
XCLK1
XCLK0
7/2 For EC Crystal cost down
32.768KHZ_12.5PF_Q13MC14610002
@
C1206
SB_PWRGD <19>
BKOFF# <17>
WL_OFF# <23>
SUSP#
R869 2
1 10K_0402_5%
VR_ON
R462 2
1 10K_0402_5%
B
UMA_ENBKL <12>
SUSP#
PBTN_OUT#
USB_OC#0
SUSP# <23,31,37>
PBTN_OUT# <19>
USB_OC#0 <19,23>
+EC_V18R
C448
4.7U_0805_10V4Z
KB926QFE0_LQFP128_14X14
+3VALW
18P_0402_50V8J
R246
100K_0402_5%
7/27 Change R867 pull up from +3VALW to +3VL
C1200
@
122
123
SB_PWRGD
BKOFF#
WL_OFF#
EC_ID
EC_RSMRST# <19>
EC_LID_OUT# <19>
EC_ON <30,31,35>
7/7 Change ED_ID from pin 108 to pin 107
AGND
0_0402_5%
0_0402_5%
0_0402_5%
69
@ R991
@R991
@R992
@
R992
R990
GND
GND
GND
GND
GND
<18> RTCCLK
18P_0402_50V8J
4
OSC
OSC
NC
NC
Y5
@
18P_0402_50V8J
C1199
@
11
24
35
94
113
CRY1
CRY2
1
EC_RSMRST#
EC_LID_OUT#
EC_ON
R435
100K_0402_5%
@
EC_ID
EC ver.
KB926D3
KB926E0
PM_SLP_S3#
PM_SLP_S5#
EC_SMI#
<19> PM_SLP_S3#
<19> PM_SLP_S5#
<19> EC_SMI#
<34> 75W_65W
<24> WOL_EN
EC_ID
R874 2
1 100K_0402_5% E51_TXD
R783 1
2 100K_0402_5% PLT_RST#
2
@C1238
@
C1238
1
0.1U_0402_16V4Z
Compal Secret Data
For ESD request
2010-08-25
Issued Date
Deciphered Date
2010-08-25
Title
Size
Date:
R436
100K_0402_5%
@
1
7/20 PVT reserve C1199,Y5, C1200
SCHEMATICS,MB A6843
Document Number
Rev
B
401982
Sheet
1
28
of
40
SPI Flash (256KB)
LPC Debug Port Please
Lid SW
place the PAD under DDR DIMM.

H7
+3VS
7/7 Change U13 from MXIC to WINBOND for EOL
+3VALW
VSS
C1201
0.1U_0402_16V4Z
HOLD
<28> SPI_CS#
<28> SPI_CLK
SPI_CS#
SPI_CLK
<28> EC_SO_SPI_SI
VDD
VOUT
PLT_RST# <12,15,18,23,24,28>
<18,28> LPC_AD3
C1202
0.1U_0402_16V4Z
LPC_AD2 <18,28>
<18,28> LPC_AD1
LPC_AD0 <18,28>
10
CLK_PCI_SIO <18,22>
<18,28> SERIRQ
LID_SW# <28>
1
C1203
10P_0402_50V8J
2
<18,28> LPC_FRAME#
EC_SI_SPI_SO <28>
VCC
GND
U13
20mils
1
U54
APX9132ATI-TRL_SOT23-3
+3VL
W25X20BVSNIG SOIC 8P
R876
22_0402_5%
@
@ DEBUG_PAD
SPI_CLK
1 R877 @2
10_0402_5%
1
C1205
8/6 Change U13 footprint to M25P10-AVMN6T_SO8
2
C1204
22P_0402_50V8J
1 @
2
@ 10P_0402_50V8J
reserve for EMI, close to U13

reserve for EMI
KEYBOARD CONN.
KSI[0..7]
KSO[0..17]
please close to JKB1
KSI[0..7] <28>
KSO16
KSO[0..17] <28>
1
C1207
1
C1208
KSO2
1
C1209
KSO1
1
C1210
KSO0
1
C1211
KSO4
1
C1212
KSO3
1
C1213
KSO5
1
C1214
KSO14
1
C1215
KSO6
1
C1216
KSO7
1
C1217
KSO13
1
C1218
KSO8
1
C1219
KSO9
1
C1220
KSO10
1
C1221
KSO11
1
C1222
KSO12
1
C1223
KSO15
1
C1224
KSI7
1
C1225
KSI2
1
C1226
KSI3
1
C1227
KSI4
1
C1228
KSI0
1
C1229
KSI5
1
C1230
KSI6
1
C1231
KSI1
1
C1232
CAPS_LED#
1
C1233
NUM_LED#
1
C1234
KSO17
JKB
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
JKB34
KSO16
1
2
R881 300_0402_5%
+3VS
KSO17
KSO2
KSO1
KSO0
KSO4
KSO3
KSO5
KSO14
KSO6
KSO7
KSO13
KSO8
KSO9
KSO10
KSO11
KSO12
KSO15
KSI7
KSI2
KSI3
KSI4
KSI0
KSI5
KSI6
KSI1
JKB4
2
1
CAPS_LED# R882 300_0402_5%
NUM_LED#
ACES_88170-3400
CONN@
+3VS
CAPS_LED# <28>
NUM_LED# <28>
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
Issued Date
Compal Secret Data
2010-08-25
Deciphered Date
2010-08-25
Title
Size
Date:
SCHEMATICS,MB A6843
Document Number
Rev
B
401982
Sheet
29
of
40
< Touch / B Connector >
+3VL
Power Button
R883
51_ON# <32>
ON/OFFBTN#
Q163A
2N7002DW-T/R7_SOT363-6
BTM side
Right Switch
SW4
R884
10K_0402_5%
JPOWER
1 1
2 2
3 3
4 4
5 G1
6 G2
ON/OFFBTN#
<28> ON/OFFBTN#
For EMI request
1
2
3
4
5
6
+5VS
<28> TP_CLK
<28> TP_DATA
TP_SWL
TP_SWR
Left Switch
3
G7
G8
7
8
1
2
3
4
5
6
P-TWO_161021-06021_6P-T
CONN@
AZ5125-02S.R7G
D11
SW1
TP_SWL
JTOUCH
4
SMT1-05-A_4P
ACES_85201-0405N
CONN@
D12
@
AZ5125-02S.R7G
TP_SWR
< Power / B Connector >
<28,31,35> EC_ON
6
5
SMT1-05-A_4P
C1235
0.1U_0402_25V6
@
6
5
DEBUG@
3
100K_0402_5%
SW6
1
debug phase using
4
6
5
SMT1-05-A_4P
7/13 For ESD request
Screw Hole
Vf=1.9V(typ),2.4V(max)
If=20mA(max)
H13
H14
H_3P0
@
H_3P0
@
H_3P0
@
H12
H_3P0
@
PWR_LED# <28>
BATT_CHG_LOW_LED#
3 R773 1
2 510_0402_5%
BATT_FULL_LED# <28>
YG
3
H2
H_2P7x3P2N
@
<28>
H3
H_2P7N
@
H15
H_1P0N
@
H16
H_5P0N
@
H_5P0N
@
2 510_0402_5%
YG
2 R774 1
+5VALW
2 510_0402_5%
H11
H_3P0
@
H1
D67
R768 1
H10
H_3P0
@
D70
+5VALW
H9
H_3P0
@
H_3P0
@
H_3P0
@
Vf=1.8V(typ),2.0V(max) for amber

Vf=1.8V(typ),2.0V(max) for green
If=20mA(max)
H8
H6
H5
DC IN/ BATT CHARGE
POWER/SUSPEND LED
HT-110UYG5_YELLOW GREEN
HT-210UD5-UYG5_AMBER-YEL GRN
CPU
H18
H_4P9
@
H19
H_3P3
@
H_3P3
@
H23
H_4P2x4P7
@
H22
H_4P2x4P7
@
H21
H_4P2
@
7/6 For Power LED PWM function

7/15 Change D67/D70 to 5mA type
7/23 Change R773 from 120 to 510 ohm
7/23 Change Net name from+3VALW to +5VALW
MINI CARD -- WLAN
H20
7/23 Change R773 from 120 to 510 ohm

7/23 Change Net name from+3VALW to +5VALW
8/6 Add R774 link to BATT_CHG_LOW_LED#
8/6 Change R773 link to BATT_FULL_LED#
PCB Fedical Mark PAD

1
FD3
@
FD4
@
FD2
@
FD1
@
B
ESD reserved
+5VS
+3VS
B+
+3VS
+1.1VS
ISPD
7/13 Change P/N to DC30100A400

PJP1
C1258
0.1U_0402_16V7K
C1262
0.1U_0402_16V7K
C1263
0.1U_0402_16V7K
C1261
0.1U_0402_16V7K
C1260
0.1U_0402_16V7K
C1259
0.1U_0402_16V7K
C1257
0.1U_0402_16V7K
ZZZ
DC-IN
PCB
PCB SKU LA-6843P Rev10
U3
U8
NB R3
Near H5
Near H11
Near H12
Near H8
Near H14
Near H13
PJP1
45@
SB R3
RS880M
R3@
Near R972
SB820M_FCBGA605_A13
R3@
7/21 Change P/N to SA00003IWB0

Issued Date
Compal Secret Data
2010-08-25
2010-08-25
Deciphered Date
Title
Size
Date:
SCHEMATICS,MB A6843
Document Number
Rev
B
401982
1
Sheet
30
of
40
+1.5V
< +1.5V TO +1.5VS >
Q5
+5VS
Q2
C449
RUNON
2
SI4800BDY_SO8
C462
1U_0402_6.3V4Z
C463
10U_0805_10V4Z
4.7U_0805_10V4Z
R305
2
4.7U_0805_10V4Z
1.5VS_ENABLE
R285
750K_0402_1% +VSB
SUSP
C466
R286
2N7002DW-T/R7_SOT363-6
Q34B
10M_0402_5%
0.01U_0402_25V7K
SUSP
< +1.1VALW TO +1.1VS >

+1.1VALW
C469
8
7
6
5
R251
4.7U_0805_10V4Z
RUNON
+VSB
SUSP
2
1
C476
Q14A
2N7002DW-T/R7_SOT363-6
< +1.1VALW TO +NB_CORE >
1 0_0402_5%
VGATE#
R290
330K_0402_5%
R300
+VSB
470_0805_5%
Q12B
10M_0402_5%
0.01U_0402_25V7K
2
1
4.7U_0805_10V4Z
4.7U_0805_10V4Z
Q14B
2N7002DW-T/R7_SOT363-6
0.01U_0402_25V7K
1U_0402_6.3V4Z
VLDT_EN#
BOOT_ON @
@R47
R47 2
+ C158
@
390U_2.5V_M_R10
2
C475
R291
C474
1 0_0402_5%
C472
470_0805_5%
R287
1 750K_0402_1%
C471
1U_0402_6.3V4Z
SI4800BDY_SO8
1
2
3
SUSP
R46 2
C468
Inrush current = 0A
1 0_0402_5%
BOOT_ON
31
1
2
3
4
S
S
S
G
4.7U_0805_10V4Z
D
D
D
D
Q6
IRF8113PBF_SO8
Inrush current = 0A
BOOT_ON @
@R45
R45 2
BOOT_ON
2N7002DW-T/R7_SOT363-6
Q12A
2N7002DW-T/R7_SOT363-6
Q3
C470
+1.1VS
+3VS
+3VALW
2N7002DW-T/R7_SOT363-6
Q11A
2N7002DW-T/R7_SOT363-6
< +3VALW TO +3VS >
Q11B
7/8 Change Q5 from FDS6676AS to SI4800DBY
8
7
6
5
470_0805_5%
SI4800BDY_SO8
1U_0402_6.3V4Z
C464
470_0805_5%
C450
4.7U_0805_10V4Z
1
2
3
4
S
S
S
G
Inrush current = 0A
1
2
3
4
S
S
S
G
C452
D
D
D
D
R250
Inrush current = 0A
D
D
D
D
8
7
6
5
8
7
6
5
+5VS
+5VALW
+1.5VS
< +5VALW TO +5VS >
< Inversion of SYSON, SUSP#, VLDT_EN, EC_ON >
+1.1VALW
+NB_CORE
+5VALW
Inrush current = 0A
+5VALW
C481
Q15B
2N7002DW-T/R7_SOT363-6
5
<28,36> SYSON
Q13B
0.01U_0402_25V7K
BOOT_ON
Q13A
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
VLDT_EN#
Q15A
2N7002DW-T/R7_SOT363-6
2
SUSP# <23,28,37>
4
SUSP <37>
EC_ON#
<28> VLDT_EN
Q16B
2N7002DW-T/R7_SOT363-6
5
EC_ON <28,30,35>
VLDT_EN 2
Q16A
2N7002DW-T/R7_SOT363-6
10M_0402_5%
SUSP
SYSON#
470_0805_5%
+VSB
R292
330K_0402_5%
R293
R815
@
100K_0402_5%
2
1
4.7U_0805_10V4Z
R306
R816
100K_0402_5%
100K_0402_5%
C480
100K_0402_5%
3 1
R245
4.7U_0805_10V4Z
1U_0402_6.3V4Z
R814
2
+5VALW
C478
C479
+5VALW
1
2
3
Q7
IRF8113PBF_SO8
8
7
6
5
< Discharge circuit >
+5VALW
R258
470_0805_5%
470_0805_5%
2
1
1
SUSP
D
Q23
2
G
S 2N7002_SOT23-3
EC_ON#
S 2N7002_SOT23-3
S 2N7002_SOT23-3
D
Q10
2
G
SUSP
D
Q17
2
G
3
SYSON#
VR_ON# <37>
Q35A
2N7002DW-T/R7_SOT363-6
2
VR_ON <28,38>
Q22
@
S 2N7002_SOT23-3
2
G
Q35B
2N7002DW-T/R7_SOT363-6
5
R254
@
470_0805_5%
470_0805_5%
VR_ON#
3
R253
R257
100K_0402_5%
VGATE#
+1.1VALW
2
R803
+1.8VS
R802
100K_0402_5%
<28,38> VGATE
+0.75VS
+1.5V
+5VALW
Compal Secret Data
Issued Date
2010-08-25
2010-08-25
Deciphered Date
Title
Date:
SCHEMATICS,MB A6843
Rev
B
401982

E
Sheet
31
of
40
PreCHG
PQ2 @
BSS84_SOT23-3
VIN
2
@ PR5
1
2
1K_1206_5%
PC4
100P_0402_50V8J
PR4
PR3
100K_0402_5%
@
100K_0402_5%
@
1
@ PR6
1
2
1K_1206_5%
PR7 @
100K_0402_5%
1
1 2
@ PR8
1
2
1K_1206_5%
PD4
2
1
<35> +5VALWP
3
RB715F_SOT323-3
3
PQ5
PQ3 @
DTC115EUA_SC70-3
DTC115EUA_SC70-3
N1
<29>
51_ON#
VS
1
PC8
0.1U_0603_25V7K
PC7
0.22U_0603_25V7K
PR12
100K_0402_1%
RLS4148_LL34-2
BATT+
PD3
PR10
68_1206_5%
2
PR9
68_1206_5%
PQ1
BSS84_SOT23-3
PD2
RLS4148_LL34-2
@
3
<28,34> ACOFF
VIN
B+
1
2
PC3
1000P_0402_50V7K
RLS4148_LL34-2
@ PR2
1
2
1K_1206_5%
1
1
2
@SINGA_2DW-0005-B03
PC2
100P_0402_50V8J
PC17
680P_0402_50V7K
PC1
1000P_0402_50V7K
1
2
0_1206_5%
VIN
SMB3025500YA_2P
PL1
DC_IN_S2
7A_24VDC_429007.WRML
DC_IN_S1 1
PJP1
PD1
1
PF1
DC301001M80
PR1
PR15
22K_0402_1%
+3VALWP
PJ1
+3VALW
+1.1VALWP
JUMP_43X118
3
OCP(min) = 8.33A
2
PJ5
PJ2
+1.1VALW
+3VLP
JUMP_43X118
@ PJ4
2 2
1 1
(5A,200mils, Via NO.= 10)
+5VALWP
+2.5VSP
+1.5VP
PJ7
+VSB
JUMP_43X79
(1.5A,60mils, Via NO.= 3)
+2.5VS
@
+VDDNBP
PJ12
1
+VDDNB
JUMP_43X79
(4A,160mils ,Via NO.= 8)
PJ11
1
PJ9
(1A,40mils ,Via NO.= 2)
+1.5V
OCP(min) = 8.7A
@
@
JUMP_43X118
JUMP_43X39
+3VL
JUMP_43X39
(120mA,40mils, Via NO.= 1)
+0.75VSP
(9.5A,380mils ,Via NO.= 20)

1
OCP(min) = 18.7A
+5VALW
OCP(min) = 8.33A
+VSBP
JUMP_43X118
(5A,200mils, Via NO.= 10)

PJ8
PJ3
JUMP_43X39
(16A,640mils, Via NO.= 32)

1
(100mA,40mils ,Via NO.= 2)
JUMP_43X118
+1.8VSP
+0.75VS
PJ10
1
+1.8VS
+1.05VSP
JUMP_43X79
(2.5A,100mils, Via NO.= 5)
PJ13
1
+1.05VS
JUMP_43X79
(1.75A,80mils, Via NO.= 4)
Precharge detector
15.97V/14.84V FOR
ADAPTOR
Issued Date
Compal Secret Data
2010-08-25
Deciphered Date
2010-08-25
Title
Size
Date:
SCHEMATICS,MB A6843
Document Number
Rev
B
401982
D
Sheet
32
of
40
PH1 under CPU botten side :

CPU thermal protection at 95 degree C
Recovery at 56 degree C
Rset = 3 * Rtmh
Rhyst = (Rset* Rtml) / (3*Rtml - Rset)
VMB
PF2
10A_125V_451010MRL
1
2
BATT_S1
BATT_P3
BATT_P4
BATT_P5
EC_SMDA
EC_SMCA
BATT+
Rtmh at 95C = 6.64K, Rtml at 57C = 25.1K

Rset = 3 * 6.64K = 19.92K ==> 20K
Rhyst = (20K * 25.1K) / (3 * 25.1K - 20K) = 9.078K ==> 9.09K
+3VLP
PC14
1000P_0402_50V7K
1
2
3
4
5
6
7
8
9
GND
GND
GND
GND
1
2
3
4
5
6
7
8
9
PC15
0.01U_0402_25V7K
10
11
12
13
PJP2
SUYIN_200045MR009G171ZR
VL
PR32
1K_0402_1%
PL2
SMB3025500YA_2P
1
2
PD6
PJSOT24C_SOT23-3
PD8
2
1
1
PR31
23.2K_0402_1%
PU3
1
VCC TMSNS1
GND RHYST1
OT1 TMSNS2
OT2 RHYST2
+3VLP
PR39
100_0402_1%
<35>
VS_ON
PR33
10.7K_0402_1%
1
PR40
1K_0402_1%
G718TM1U_SOT23-8
BATT_TEMPA <28>
EC_SMB_DA1 <28>
PH1
100K_0402_1%_NCP15WF104F03RC
PR38
100_0402_1%
PC16
0.1U_0402_16V4Z
PR37
6.49K_0402_1%
2
1
PJSOT24C_SOT23-3
EC_SMB_CK1 <28>
PQ6
BSS84_SOT23-3
PR45
1
PR48
0_0402_5%
1
2
POK
1
2
PC20
0.1U_0603_25V7K
22K_0402_1%
PQ7
SSM3K7002FU_SC70-3
2
G
<35,36>
PC22
.1U_0402_16V7K
PR47
100K_0402_1%
VL
2
1
PR43
100K_0402_1%
+VSBP
@ PC19
0.22U_0603_25V7K
B+
Issued Date
Compal Secret Data
2010-08-25
Deciphered Date
2010-08-25
Title
Size
Date:
SCHEMATICS,MB A6843
Document Number
Rev
B
401982
D
Sheet
33
of
40
B+
@
2
PJ22
CSIN
JUMP_43X79
2
1 1
1
3
PR238
100K_0402_1%
DCIN
24
ACSET ACPRN
23
EN
CSON
22
CELLS
CSOP
21
ICOMP
CSIN
20
VCOMP
CSIP
19
ICM
PHASE
18
LX_CHG
VREF
UGATE
17
DH_CHG
CHLIM
BOOT
16
PR70
2.2_0603_5%
BST_CHG
1
2
10
ACLIM
VDDP
15
6251VDDP
DL_CHG
PC32
2200P_0402_25V7K
1
1
PQ16
DTC115EUA_SC70-3
PC217
1000P_0402_25V8J
2
1
VDD
BATT_ON
0.1U_0603_25V7K
ACPRN
20_0603_5%
2
CSON
PC30
0.047U_0603_16V7K
1
2
PR62
20_0603_5%
PC34
0.1U_0603_25V7K
1
PR65
2
G
PQ18
SSM3K7002FU_SC70-3
CSOP
1
PR63
20_0603_5%
2
2.2_0603_5%
PQ19
AO4466L_SO8
BATT+
PL4
PR67
10UH_MSCDRI-104A-100M-E_4.6A_20%
0.02_1206_1%
1
2 CHG 1
4
11
VADJ
LGATE
14
12
GND
PGND
13
2
G
<28> 75W_65W
PQ39
SSM3K7002FU_SC70-3
26251VDD
PC48
10U_1206_25V6M
2
1
PC41
680P_0603_50V7K
PC40
10U_1206_25V6M
2
1
1 2
PD14
RB751V-40_SOD323-2
1
PQ21
AO4466L_SO8
2
2
PR69
4.7_1206_5%
3
2
1
6251aclim
PC38
0.1U_0603_25V7K
BST_CHGA
2
1
PR73
120K_0402_1%
PR72
24K_0402_1%
6251VREF 1
2
6251VREF
2
1
PR75
20K_0402_1%
IREF
PC37
.1U_0402_16V7K
1
PR193
12.4K_0402_1%
<28>
PR71
154K_0402_1%
2
1
PC39
10U_1206_25V6M
2
1
5
6
7
8
3
2
1
ACPRN <35>
PR61
PQ22
DTC115EUA_SC70-3
PR66
47K_0402_1%
1
2
1 2
ACOFF
ACOFF
ADP_I
2
1
PC42
0.01U_0402_25V7K
2
1
<28,32>
PR64
6.81K_0402_1%
ACSETIN
PC29
DCIN 2
1
<28>
PACIN
0.01U_0402_25V7K
2 6800P_0402_25V7K
PU4
PR68
47K_0402_5%
1
2
6251_EN
PC33 1
D
PC35
1
2
PQ20B
DMN66D0LDW-7_SOT363-6
5
G
PQ20A
ACSETIN
PR60
100K_0402_1%
PR59
150K_0402_1%
2
G
PR227
10_1206_5%
PR56
10K_0402_1%
PR228
14.3K_0402_1%
<28> FSTCHG
2.2U_0603_6.3V6K
PR57
10K_0402_1%
2
1
PC27
1
PQ15
DTC115EUA_SC70-3
3
2
1 1
6251VDD
BATT_ON
PR226
191K_0402_1%
PD201
RB751V-40_SOD323-2
VIN
PR54
47K_0402_1%
5
6
7
8
1
2
PC25
5600P_0402_25V7K
PR50
200K_0402_1%
2
PR52
200K_0402_1%
PC26
0.1U_0603_25V7K
PQ13
DTA144EUA_SC70-3
PC28
4.7U_0805_25V6-K
2
1
PreCHG
VIN
PC24
4.7U_0805_25V6-K
2
1
PC23
4.7U_0805_25V6-K
2
1
1
CSIP
PR49
0.02_1206_1%
4
8
7
6
5
1
2
3
CHG_B+
P3
VIN
PQ10
SI4483ADY-T1-GE3_SO8
1
8
2
7
3
6
5
1
2
3
PQ8
AO4435_SO8
PC132
10U_1206_25V6M
2
1
P2
PQ9
AO4435_SO8
8
7
6
5
PC130
10U_1206_25V6M
2
1
PC31
10U_1206_25V6M
2
1
PR74
4.7_0603_5%
PC43
4.7U_0805_6.3V6K
ISL6251AHAZ-T_QSOP24
6251VDD
PR240
47K_0402_1%
PR242
10K_0402_1%
VIN
PR241
10K_0402_1%
1
2
ACIN
<20,28,29>
PR77
31.6K_0402_1%
<28> CHGVADJ
VADJ
PR76
15.4K_0402_1%
1
2
@ PR78
309K_0402_1%
PACIN
@ PR79
10K_0402_1%
1
2
PQ214
DTC115EUA_SC70-3
CC=0.25A~3.6A
ADP_V <28>
High
Low 17.44V
@ PR80
47K_0402_1%
CHGVADJ
18.089V
@ PC44
.1U_0402_16V7K
Vcell
PR243
14.3K_0402_1%
2
CHGVADJ=(Vcell-4)*9.445
ACPRN
Vin Detector
4V
0V
IREF=0.9133*Icharge
4.2V
1.882V
IREF=0.228V~3.29V
4.35V
3.2935V
VCHLIM need over 95mV
UMA
(UMA) Iin = 2.512 ADP_I

Vin = 7.57 ADP_V
Iada=0~3.421A(65W)
CP=3.15A
PR49=0.02, PR72=24k, PR75=20k, PR35=11.5K, 75W_65W=high
Iada=0~3.947A(75W)
CP=3.63A
PR49=0.02, PR72=24k, PR75=20k, PR35=11.5K, 75W_65W=low
CP= 92%*Iada
Issued Date
Compal Secret Data
2010-08-25
Deciphered Date
2010-08-25
Title
Date:
SCHEMATICS,MB A6843
Rev
B
401982

D
Sheet
34
of
40
PC45
1U_0603_10V6K
2VREF_6182
UP6182_B+
PR82
30K_0402_1%
1
2
PR83
20K_0402_1%
1
2
PR84
19.1K_0402_1%
1
2
UP6182_B+
PC47
10U_1206_25V6M
2
1
5
6
7
8
Ipeak=8.61A
Imax=6.03A
F=245K
AO4466L_SO8
3
2
1
DRVH1
21
LX_3V
11
LL2
LL1
20
LX_5V
LG_3V
12
DRVL1
19
LG_5V
PQ27B
AO4712L_SO8
3
2
1
PQ26
TPS51125ARGER_QFN24_4X4
1
+
1 2
VCLK
18
VREG5
VIN
PR90
4.7_1206_5%
PC56
330U_6.3V_M
PC58
680P_0603_50V7K
Total capacitor 220uF

ESR = 15mohm
VL
PC60
4.7U_0805_10V6K
2VREF_6182
17
16
13
1
GND
DRVL2
+5VALWP
DRVH2
PL7
4.7UH_SIL1045R-4R7PF_6.3A_30%
1
2
5
6
7
8
10
PC54
0.1U_0603_25V7K
1
2
6
1
2
VL
PQ23
<33,36>
5
G
PC46
2200P_0402_50V7K
2
1
ENTRIP1
UG_3V
BST_5V 1 PR88
2
0_0603_5%
UG_5V
UP6182_B+
22
EN0
ENTRIP2
ENTRIP1
23
VBST1
PC59
1U_0402_6.3V6K
2
1
ENTRIP1
PQ27A
PGOOD
VBST2
PR91
499K_0402_1%
1
2
B+

ESR = 15mohm
VFB1
VREF
4
TONSEL
VREG3
AO4712L_SO8
PR92
100K_0402_1%
VO1
24
PQ25
1
2
3
PC57
680P_0603_50V7K
POK
1 2
BST_3V
15
1
PR89
4.7_1206_5%
VO2
SKIPSEL
PC53
0.1U_0603_25V7K
1
2
1 PR87
2
0_0603_5%
8
7
6
5
AO4466L_SO8
14
1
2
3
PQ24
PL6
4.7UH_SIL1045R-4R7PF_6.3A_30%
1
2
+3VALWP
VFB2
P PAD
ENTRIP2
25
PC55
330U_6.3V_M
PR86
150K_0402_1%
2
PU5
PC52
4.7U_0805_10V6K
Ipeak = 7.65A
Imax = 5.36A
F = 305K
8
7
6
5
PC51
10U_1206_25V6M
2
1
PC50
10U_1206_25V6M
2
1
PR85
150K_0402_1%
1
2
ENTRIP2
+3VLP
PC49
2200P_0402_50V7K
2
1
B+
PL3
HCB2012KF-121T50_0805
2
1
PR81
13K_0402_1%
1
2
PC61
0.1U_0603_25V7K
PR94
100K_0402_1%
VS_ON
2
G
PR373
1
2
200K_0402_1%
1
ACPRN
<34>
A
2
PC370
2.2U_0603_10V6K
PR95
100K_0402_1%
PR96
42.2K_0402_1%
VS
PQ362
SSM3K7002FU_SC70-3
2
1
<33>
PQ29
DTC115EUA_SC70-3
<28,29,31> EC_ON
2010-08-25
Issued Date
DTC115EUA_SC70-3
Compal Secret Data
PQ363
Deciphered Date
2010-08-25
Title
SCHEMATICS,MB A6843
Custom
Date:
Rev
B
401982
Sheet
1
35
of
40
PL151
HCB2012KF-121T50_0805
1
2
1
2
11
VDD
10
3
2
1
DL_1.1V
DL
4
1
PGND
AGND
7
PC67
4.7U_0603_6.3V6K
PGOOD
+5VALW
2
PR102
9.1K_0402_1%
FB
LX_1.1V
1
G5603RU1U_TQFN14_3P5X3P5
PC69
4.7U_0805_10V6K
PR100
4.7_1206_5%
12
ILIM
+1.1VALWP
(+1.1VALW, +1.1VS, NB_CORE)

1
+
2
PC68
680P_0603_50V7K
LX
VCC
0.1U_0603_25V7K
OUT
DH_1.1V
13
15
14
BST
DH
Ipeak = 16.1A
Imax = 11.3A
F = 315K
PL9
1UH_FDUE1040D-1R0M-P3_21.3A_20%
1
2
PC65
BST_1.1V 1
2
PQ31
MDU2653RH_POWERDFN56-8-5
PR99
0_0603_5%
TP
TON
3
2
1
PR101
100_0603_1%
1
2
EN_SKIP
2
+5VALW
PU6
+
2
PQ30
TPCA8030-H_SOP-ADV8-5
@ PC64
.1U_0402_16V7K
B+
1
PR98
0_0402_5%
1
2
POK
<33,35>
PC91
2200P_0402_50V7K
PC133
10U_1206_25V6M
PC63
4.7U_0805_25V6-K
1
2
PC62
4.7U_0805_25V6-K
1.1V_B+
PR97
255K_0402_1%
1
2
PC127
68U_25V_M_R0.36
PC66
330U_6.3V_M

ESR = 7.5mohm
PR103
4.75K_0402_1%
1
2
PR104
10K_0402_1%
PL152
HCB2012KF-121T50_0805
1
2
DH_1.5V
12
LX_1.5V
VCC
ILIM
11
FB
VDD
10
2
PR110
20K_0402_1%
PGOOD
DL_1.5V
G5603RU1U_TQFN14_3P5X3P5
PC79
2200P_0402_50V7K
PC72
4.7U_0805_25V6-K
1
2
PR108
4.7_1206_5%
4
PC78
4.7U_0805_10V6K
PQ33

ESR = 15mohm
+5VALW
PGND
8
AGND
7
PC76
4.7U_0603_6.3V6K
DL
0.1U_0603_25V7K
+1.5VP
13
LX
DH
OUT
TON
PC74
1
2
BST
Ipeak = 9.5A
Imax = 6.65A
F = 315K
PL11
1.8UH_SIL104R-1R8PF_9.5A_30%
1
2
5
6
7
8
14
15
TP
BST_1.5V
+5VALW
AO4466L_SO8
PR107
0_0603_5%
3
2
1
PR109
100_0603_1%
1
2
PU7
@PC73
@
PC73
.1U_0402_16V7K
EN_SKIP
PQ32
2
3
2
1
B+
SYSON
<28,31>
PR105
255K_0402_1%
1
2
PR106
0_0402_5%
1
2
PC71
4.7U_0805_25V6-K
5
6
7
8
1.5V_B+
PC75
330U_6.3V_M
PC77
680P_0603_50V7K
AO4712L_SO8
PR111
10K_0402_1%
1
2
PR112
10K_0402_1%
Compal Secret Data
2010-08-25
Issued Date
2010-08-25
Deciphered Date
Title
Size
Date:

SCHEMATICS,MB A6843
Document Number
Rev
B
401982
Sheet
1
36
of
40
+1.5V
VDDR_SW
HIGH
1.05V
LOW
0.9V
+3VS
+5VALW
PJ16
@ JUMP_43X79
1
PU10
APL5930KAI-TRG_SO8
PR166
2.4K_0402_1%
1
2
FB
PC89
22U_0805_6.3V6M
@ PC83
0.01U_0402_25V7K
PC88
0.01U_0402_25V7K
SUSP#
+1.8VSP
PR165
3K_0402_1%
2
EN
POK
3
4
TP
8
7
VOUT
VOUT
1
PR117
10.5K_0402_1%
NC
2
2
VOUT
VCNTL
VIN
VIN
GND
NC
6
5
9
VREF
PR195
0_0402_5%
1
2
+5VALW
1
PC82
1U_0603_6.3V6M
NC
GND
PC181
1U_0603_6.3V6M
+1.05VSP
PQ4
2
G
PR113
6.98K_0402_1%
PC86
.1U_0402_16V7K
@ PC90
.1U_0402_16V7K
VR_ON#
<31>
PR115
0_0402_5%
1
2
@ PR153
10K_0402_1%
SSM3K7002FU_SC70-3
PC85
4.7U_0805_6.3V6K
PU9
APL5331KAC-TRL_SO8~N
VIN
VCNTL 6
PQ11
2
G
<34> VDDR_SW
SSM3K7002FU_SC70-3
@ PR167
10K_0402_1%
1 2
@ PR148
12.4K_0402_1%
+5VALW
PC84
4.7U_0805_6.3V6K
PJ15
@ JUMP_43X79
VDDR
PC87
10U_0805_6.3V6M
@ PJ17
JUMP_43X79
OUT
JUMP_43X39
NC
VREF
NC
VOUT
NC
TP
+3VALW
PR119
1K_0402_1%
+2.5VSP
PC93
1U_0603_6.3V6M
B
PR120
1K_0402_1%
S
PQ34
SSM3K7002FU_SC70-3
2
3
2
@ PC96
.1U_0402_16V7K
2
G
+0.75VSP
1
PR121
0_0402_5%
1
2
SUSP
<31>
PC81
4.7U_0805_6.3V6K
PC94
.1U_0402_16V7K
GND
PC80
1U_0603_10V6K
GND
IN
PC92
4.7U_0805_6.3V6K
PJ14
PU8
APL5508-25DC-TRL_SOT89-3
@
+3VS
PU11
APL5331KAC-TRL_SO8~N
VIN
VCNTL 6
+1.5V
PC95
10U_0805_6.3V6M
Compal Secret Data
2010-08-25
Issued Date
2010-08-25
Deciphered Date
Title
Size
Date:

SCHEMATICS,MB A6843
Document Number
Rev
B
401982
Sheet
1
37
of
40
+VDDNB
LGATE_NB
29
PGND1
28
LGATE1
11
COMP0
UGATE1
26
UGATE1
12
VW0
BOOT1
25
BOOT1
24
ISN1
PR149
0_0603_5%
BOOT1 1
2 1
COMP0
PC121
1000P_0402_50V7K
PR158
1
PC125
2
1
PR159
6.81K_0402_1%
2
1
54.9K_0402_1% 1200P_0402_50V7K
@ PR161
1
PC109
4.7U_0805_25V6-K
2
1
PC129
4.7U_0805_25V6-K
2
1
2
1
COMP1
1
PC117
680P_0603_50V7K
PC118
2
1
0.1U_0603_16V7K
PC124
@PC124
@
1000P_0402_50V7K
4
PR162
@PR162
@
6.81K_0402_1%
2
1
@ PC126
2
1
54.9K_0402_1% 1200P_0402_50V7K
@ PR164
36.5K_0402_1%
Compal Secret Data
2010-08-25
Issued Date
2010-08-25
Deciphered Date
Title
Date:
PR154
4.02K_0402_1%
A
+CPU_CORE
PR152
16.5K_0402_1%
@ PC123
180P_0402_50V8J
@ PR163
36.5K_0402_1%
2
3
2
1
FB_1
@ PR160
1K_0402_5%
PR157
1K_0402_5%
PQ41
VW1
@ PC122
4700P_0402_25V7K
PL15
0.36UH_PCMC104T-R36MN1R17_30A_20%
PQ40
PR151
4.7_1206_5%
LGATE1
+1.5V
@ PR156
@PR156
255_0402_1%
2
1 2
PC116
0.22U_0603_10V7K
DIFF_1
PC120
180P_0402_50V8J
ISP1
FB_0
PC119
4700P_0402_25V7K
3
2
1
5
TP
49
23
UGATE1
PHASE1
VW0
PR145
4.02K_0402_1%
CPU_B+
PR150
1K_0402_1%
1
2
PC219
1000P_0402_50V7K
1 2
RTN0
PC113
1U_0603_10V6K
VSEN0
ISP1
VW1
22
21
FB1
20
19
VSEN1
18
RTN1
RTN0
17
13
ISP0
ISN0
PC371
330P_0402_25V8J
ISN1
PHASE1
ISP1
27
COMP1
PHASE1
VDIFF1
FB0
VSEN0
10
PC112
2
1
0.1U_0603_16V7K
ISN0
LGATE1
VDIFF0
PC111
680P_0603_50V7K
ISP0
OCSET
LGATE0
30
PR141
16.5K_0402_1%
PC131
4.7U_0805_25V6-K
2
1
31
PVCC
PC115
4.7U_0805_25V6-K
2
1
LGATE0
ISL6265CHRTZ-T_TQFN48_6X6
PC114
4.7U_0805_25V6-K
2
1
RBIAS
PQ38
3
2
1
ENABLE
32
LGATE0
3
2
1
PGND0
+CPU_CORE
SVC
PR139
4.7_1206_5%
+5VALW
PHASE0
UGATE0
33
34
PHASE0
1 2
UGATE0
SVD
PC110
0.22U_0603_10V7K
PL14
0.36UH_PCMC104T-R36MN1R17_30A_20%
DIFF_0
PC108
4.7U_0805_25V6-K
2
1
5
PWROK
PQ37
PR137
0_0603_5%
BOOT0 1
2 1
VSEN0
PR155
255_0402_1%
2
1 2
3
2
1
37
UGATE_NB
39
38
PHASE_NB
40
PGND_NB
LGATE_NB
41
42
RTN_NB
OCSET_NB
44
45
43
VSEN_NB
FSET_NB
BOOT0
PR147
0_0402_5%
PR190
10_0402_1%
2
1
46
35
<7> CPU_VDD0_RUN_FB_L
FB_NB
36
BOOT0
PR146
0_0402_5%
2
COMP_NB
BOOT_NB
PGOOD
ISP0
2
<7> CPU_VDD0_RUN_FB_H
47
OFS/VFIXEN
PC218
2200P_0402_25V7K
2
1
1
PR189
10_0402_1%
VCC
2
3
+CPU_CORE
<7>
PHASE0
PR142
0_0402_5%
PR144
95.3K_0402_1%
2
1
Ipeak = 36A
Imax = 25.2A
F = 300K
ESR = 1.5mohm
<28,31> VR_ON
PR143
21.5K_0402_1%
2
1
48
VIN
ISL6265_PWROK
1
PR140
0_0402_5%2
PC105
330U_6.3V_M
CPU_B+
CPU_VDDNB_RUN_FB_L
BOOT_NB
16
CPU_SVC
AO4712L_SO8
UGATE0
PU12
15
CPU_SVD
<7>
2
PR138 0_0402_5%
5
6
7
8
3
2
1
1
PR133
0_0402_5%
ISN0
<7>
14
<18> H_PWRGD_L
2
PR136 0_0402_5%
PC106
680P_0603_50V7K
<7>
+VDDNBP
UGATE_NB
@ PR135
@PR135
105K_0402_1%
1
@
PR192
10_0402_1%
1
2
PHASE_NB
@ PR131
@PR131
105K_0402_1%
VGATE
<7,18> H_PWRGD
PR125
4.7_1206_5%
PHASE_NB
1
<28,31>
PQ36
LGATE_NB
PC104
0.22U_0603_10V7K
4
CPU_VDDNB_RUN_FB_H
PR129
11K_0402_1%
2
1
1
1
@ PR134
10K_0402_1%
PR132
105K_0402_1%
PR130
0_0402_5%
+
2
PL13
4.7UH_SIL1045R-4R7PF_6.3A_30%
1
2
AO4466L_SO8
1 2
PR191
10_0402_1%
1
2
PC107
0.1U_0603_25V7K
+
2
PR127
2_0603_5%
+3VS
PR124
2.2_0603_1%
BOOT_NB 1
2 1
PR128
0_0402_5%
2
1
+5VS
PHASE_NB
PR126
22K_0402_1%
2
1
2
CPU_B+
+3VS
+
2
B+
PQ35
PC103
0.1U_0603_16V7K
UGATE_NB
PC102
1000P_0402_50V7K
2
1
1
+5VALW
PC100
1000P_0402_50V7K
PC128
68U_25V_M_R0.36
PR123
2_0603_5%
1
2
5
6
7
8
PC99
68U_25V_M_R0.36
PR122
44.2K_0402_1%
PL12
HCB4532KF-800T90_1812
1
2
PC98
68U_25V_M_R0.36
PC101
10U_1206_25V6M
2
1
CPU_B+
PC97
33P_0402_50V8J
2
1
ISN1
SCHEMATICS,MB A6843
Rev
B
401982
Sheet

E
38
of
40
PIR (Product Improve Record)

PWWAE LA-6843P SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.1 TO 0.2
NO
DATE
PAGE
MODIFICATION LIST
PURPOSE
--------------------------------------------------------------------------------------------------------------------------------------------------------------------1
2010/07/20
28
Reserve C1199,Y5,C1200
For design change
2
2010/07/20
28
Reserve R436 for only KB926E0
For design change
2010/07/20
29
Del R875
For SERIRQ direct connect to H7.7
2010/07/20
29
Del C588/C589/Y4/R368
For design change
3
2010/07/21
11~15
Change U8 R1 P/N from A12(SA000032WI40) to A13(SA000032WA0)
For SB820 A13 version
2010/07/21
30
Change U8 R3 P/N from A12(SA000032WI50) to A13(SA000032WB0)
For SB820 A13 version
4
2010/07/23
18
Change D8 from DAN202U to CHN202UPT
For design change
5
2010/07/23
24
Chagne UL4 from LF-H1201P-2 to LFE8456E-R for use 5mA type
For design change
6
2010/07/23
30
Change R768/R773 from 120 to 510 ohm for use 5mA type
For design change
Change R768.1 pull up from +3VALW to +5VALW for use 5mA type
For design change
Change R773.1 pull up from +3VALW to +5VALW for use 5mA type
For design change
7
2010/07/23
27
Change JLINE/JEXMIC to FOX_JA6331-B39S4-7F
For DFX request
8
2010/07/26
23
Reserve DM2
For +3V_WLAN is +3VS
9
2010/07/26
Add R50
For Intel Rainbow Peak module
2010/07/26
24
Reserve CL39
For EMI request
10
2010/07/27
28
Change R867 pull up from +3VALW to +3VL
For design change
REVISION CHANGE: 0.2 TO 1.0

NO
DATE
PAGE
MODIFICATION LIST
PURPOSE
--------------------------------------------------------------------------------------------------------------------------------------------------------------------1
2010/08/06
29
Change U13 footprint to M25P10-AVMN6T-SOP
For design change
2
2010/08/06
25
Change Net name form V1_8 to +V1_8
For customer request
2010/08/06
29
Add R774 link to BATT_CHG_LOW_LED#
2010/08/06
29
Change R773 link to BATT_FULL_LED#
3
2010/08/06
30
Reserve SW6 Del SW5
For debug phase
2010/08/09
30
Chagne UL4 from NS681680 to NS681610
For design change
4
2010/08/09
08
Mount C26/C89,Reserve C24,C90
For design change
5
2010/08/16
18
Del R42/C94
For EMI request
2010/08/16
18
Reserve CC9/RC7
For EMI request
6
2010/08/16
24
Add CL3/CL7 link to +3V_LAN
For EMI request
Reserve CL38
For EMI request
Change CL37 from 0.1uF to 120 pF
For EMI request
Add D13 link to LANGND
For EMI request
Issued Date
Compal Secret Data
2010-08-25
Deciphered Date
2010-08-25
Title
Size
Date:
SCHEMATICS,MB A6843
Document Number
Rev
B
401982
Sheet
1
39
of
40
Version Change List ( P. I. R. List ) for Power Circuit

Rev.
NO DATE
PAGE
MODIFICATION LIST
PURPOSE
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
2010 . 06 . 21 Release
2010 . 07.25 modification list
P 33
PC16 change to SE070104Z80
Defore material EOL
PVT
P 38
PU12 change to SA000022M80
Before material MP schedule will impact PWWAE MP schedule
PVT
P 33
Remove PD6 , PD8 @
ESD test fail
PVT
P 34
Add PC132 , remove PC130 , PC131 , PR69 , PC41 @
For EMI fail
PVT
P 35
Add PC51 , remove PC49 , PC46 , PC57 , PC58 , PR89 , PR90 @
For EMI fail
PVT
P 36
Add PC79 , PC91 , PC133 , remove PR100 , PR108 , PC68 , PC77 @
For EMI fail
PVT
P 38
Remove PR125 , PR139 , PR151 , PC106 , PC111 , PC117 @
For EMI fail
PVT
P 37
Change PU9 , PU11 to SA053310110
UP7711 stop using from now on
Pre-MP
P 38
Add PC218 , PC219 , PC371
For VCORE Ripple
Pre-MP
P 32
Add PR8
For Precharge rising current
Pre-MP
P 32 , P 33
PQ1 , PQ2 , PQ6 change to SB900840003
SB906100210 material delivery had problem
Pre-MP
P 35
Change PU5 to SA000020C80
UPI product stop using
Pre-MP
P 34
Change PU4 to SA00001EP80
SA00003TK00 stop using
Pre-MP
P 38
Remove PR127 @
To solve +1.1VALW noise
Pre-MP
P 34
Remove PR193 , PQ39 @
For PWWAE MP use 25W CPU
Pre-MP
Compal Secret Data
2010-08-25
Issued Date
2010-08-25
Deciphered Date
Title
Date:
SCHEMATICS,MB A6843
Rev
B
401982
Sheet

E
40
of
40

Compal Confidential Schematics for AMD S1G4/RS880M/SB820M Mobile Platform

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Compal Confidential Schematics for AMD S1G4/RS880M/SB820M Mobile Platform

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A

PWWAE LA-6843P Schematics Document

2010-08-16 Rev. 1.0

Compal Secret Data

Compal Electronics, Inc.

Wednesday, September 01, 2010

Model Name : PWWAA

AMD S1G4 CPU

1.5V DDRIII 1066/1333MHZ

File Name : LA-6843P

Hyper Transport Link 2.6GHz

IO/B-- USB Right

USB port 0,1

Power On/Off CKT.

DC/DC Interface CKT.

Power Circuit DC/DC

Compal Secret Data

Compal Electronics, Inc.

Wednesday, September 01, 2010

DESIGN CURRENT 0.1A

DESIGN CURRENT 0.1A

DESIGN CURRENT 3.5A

DESIGN CURRENT 330mA

DESIGN CURRENT 1.5A

DESIGN CURRENT 300mA

DESIGN CURRENT 2.5A

DESIGN CURRENT 0.3A

DESIGN CURRENT 3.5A

DESIGN CURRENT 18A

DESIGN CURRENT 18A

DESIGN CURRENT 1.5A

Compal Secret Data

Compal Electronics, Inc.

Wednesday, September 01, 2010

@ : just reserve , no build

S5 S4/ Battery only

S5 S4/AC & Battery

SMBUS Control Table

I2C / SMBUS ADDRESSING

EMC1032-1 CPU 98H

Compal Secret Data

Compal Electronics, Inc.

Wednesday, September 01, 2010

Near CPU Socket

< From NB >

< VLDT_A & VLDT_B : HyperTransport I/O ring power >

< FAN Control Circuit : Vout = 1.6 x Vset >

Compal Secret Data

Compal Electronics, Inc.

Wednesday, September 01, 2010

< Processor DDR3 Memory Interface >

< DDR2 VREF is 0.5 ratio >

< Close to CPU >

< From/To SO_DIMMB >

Place them close to CPU within 1"

< To SO_DIMMA > <9> DDR_A_ODT1

< To SO_DIMMA >

< To SO_DIMMA > <9> DDR_CKE1_DIMMA

< To SO_DIMMA > <9> DDR_A_BS#1

< To SO_DIMMA >

< VTT regulator voltage >

< To SO_DIMMA >