8257 PROGRAMMABLE DMA CONTROLLER

DIRECT MEMORY ACCESS:

The ability of an I/O sub system is to transfer data to and from a memory subsystem,
which is used for high speed data transfer.
EX. Data transfer between a floppy disk and memory.
DMA CONTROLLER:
It is a device that can control data transfer between an I/O subsystem and a memory
subsystem without the help of CPU.
DMA OPERATION SEQUENCE:
1.
2.
3.
4.

Once interface is ready to receive data, DMA request is made.

Bus request is made by the DMA.
Bus grant is returned by the processor.
DMA request is acknowledged

FEATURES:

Enable/Disable control of individual DMA requests.

Four independent DMA channels-CH0, CH1, CH2 and CH3.
Memory to memory transfer.
Memory blocks initialization.
High speed performance- transfers up to 1.6 M bytes/second

BLOCK DIAGRAM OF 8257

D7-D0

- Data bus

A0-A7

- Address Bus

IOR

- I/O Read

IOW

- I/O write

MEMR

- Memory read

MEMW

-Memory write

CLK
RESET
READY
HRQ

- clock input
- Reset input
- Ready
- Hold request

HLDA

- Hold acknowledge

AEN

- Address enable

ADSTB
TC
MARK

- Address strobe
- Terminal Count
- Modulo 128 Mask

DRQ 3 DRQ 0 - DMA request input

DACK 3 DACK 0 - DMA Acknowledge OUT
CS

- Chip select

Vcc

- +5 volts

GND

- Ground

1. DATA BUS BUFFER:

It is a tri-state, Bidirectional, 8 bit buffer which interfaces the 8257

to the system data bus. In the slave mode, it is used to transfer data between microprocessor and
internal registers of 8257. In master mode, it is used to send higher byte address (A8-A15) on the
data bus.
2. READ/WRITE LOGIC:
When the microprocessor is programming or reading one of the internal registers
of 8257 (ie, slave mode), the Read/Write logic accepts the I/O Read (IOR) or IOW signal,
decodes the least significance four address bits (A0-A3) and either writes the contents of the data
bus into the addressed register (if IOW = 0) or places the contents of the addressed register onto
the data bus (if IOR=0)
During DMA cycles ( i .e, Master mode) the Read/ write logic generates the I/O
read and memory write (DMA write cycle) or I/o Write and Memory read (DMA read cycle)
signals which control the data transfer between peripheral and memory device.
3. DMA CHANNELS:
The 8257 provides four identical channels labeled CH0, CH1, CH2 and CH3.
Each channel has two 16 bit registers
i)
DMA address register
ii)
Terminal Count register
a) DMA ADDRESS REGISTER:
It specifies the address of the first memory location to be accessed.
b) TERMINAL COUNT REGISTER:
TCR specifies the number of DMA cycles minus one (N-1) before TC output is activated.
CONTROL WORD FORMAT:

MODE SET REGISTER:

D7

D6

D5

D4

D3

D2

D1

D0

Enables
Enables TC stop
Enables Extended
Enables Rotating