EXPERIMENT - 8

AIM: Compare inverters using DTMOS, Floating Gate and Quasi- floating gate technique.
SOFTWARE USED: ORCAD PSPICE 16.6
THEORY:
DTMOS: There are many ways a DTMOS can be implemented in Very Large Scale Integrated
(VLSI) circuits. One and foremost of those is by tying substrate of the transistor to its gate. As
the substrate bias increases (VSUB), along with the gate bias (VGS), bulk charge in silicon is
compensated. This reduction in bulk charge lowers VT of the device and consequently leads to a
higher drive current (ION) due to increased available gate overdrive VGT (=VGSVT). DTMOS
threshold voltage drops as gate voltage is raised, resulting in a much higher current drive than
regular MOSFET at low Vdd. On the other hand, Vt is high at V,, = 0, thus the leakage current is
low. However, such an implementation cannot be used for supply voltages above the cut-in
voltages of the S/D junctions. More importantly, the bulk capacitance of transistor adds to total
parasitic capacitance at the input (CIN), which must be charged by the input signal. Thus, this
simple DTMOS implementation achieves higher ION while increasing the CIN, with the overall
result that there is degradation in the circuit speed.
FGMOS: The gate in FG-MOST is fabricated using the poly1 layer and is left floating, since it is
surrounded by insulator layers (SiO2). Two or more control gates (Gin, Gbias) are formed using
the second poly layer and capacitively coupled to the floating gate.. Since floating gate is
surrounded by high-quality isolation any electrical charge injected onto this gate is retained for
several years, causing DC offsets. However, this charge can be eliminated by several ways such
as cleaning with ultraviolet (UV) light, hot electron injection [Fowler-Nordheim (FN) tunneling ,
forcing an initial condition with a switch or by fabrication process solution which is based on a
novel layout technique that takes advantage of the fabrication process itself.
QFGMOS: The QFGMOST appears as a developed version of the FG-MOST to overcome some
of its drawbacks. It has been discussed previously that the relatively high bias capacitance value
of the FG-MOST leads to an increase in the silicon area and a reduction of the effective
transconductance and GBW. Besides, FG-MOST has uncertain residual charge trapped at the
floating gate. Using the QFG-MOST, the occupied chip area is minimized and the initial charge
is no longer an issue . Since the floating gate is tied through a large value resistor to a proper bias
voltage, depending on the transistor type. Practically, a leakage resistance of a reverse biased PN junction of a diode connected MOS transistor MR is implemented rather than a typical resistor.
QFG-MOST may have a multiple input terminals like the FG-MOST. Besides, it can be
fabricated in any MOS technology, nevertheless, the double poly technology is recommended to
obtain better results. The input terminal is capacitively connected to the floating gate as FGMOST case.

CIRCUIT DIAGRAM:
DTMOS INVERTER:

0.6V

VDD

mp1

V1
0.6Vdc
mn1

FGMOS INVERTER:
V1
1 .8 V d c

0
C in 1
R in 1
Vin

M 2

C in 2
R in 2

M 1

QFGMOS INVERTER:

1 .8 V d c

1 .8 V d c

0
1 .8 V d c

M 3

M 4

0
C in 1
R in 1

M 2

C in 2

Vin

R in 2

M 1

COMPARISION TABLE:
Parameter

FGMOS Inverter

Vth
Lower noise margin
Higher noise margin
Rise time
Fall time

1.0861 V
.6786 V
.1715 V
.039 ns
.399 ns

Quasi floating gate

inverter
1.0861 V
.8025 V
.0571 V
.04 ns
.364 ns

DTMOS Inverter
0.2955 V
.2572 V
.267 V
.287 ns
.495 ns

RESULT: Compared inverters based on DTMOS, FGMOS and QFGMOS techniques.