Condition code suffixes

MOV and MVN

Syntax
MOV{S}
Rd,Rm
MOVS Rd, #imm
MVNS Rd, Rm
where:
S is an optional suffix. If S is specified, the condition code flags are updated
on the result of the operation
Rd is the destination register
Rm is a source register
imm is any value in the range 0-255.

ADC, ADD, RSB, SBC, and SUB

Syntax
ADCS
ADD{S}
RSBS {Rd,}
SBCS
SUB{S}

{Rd,} Rn, Rm
{Rd,} Rn, <Rm|#imm>
Rn, Rm, #0
{Rd,} Rn, Rm
{Rd,} Rn, <Rm|#imm>

AND, ORR, EOR, and BIC

Logical AND, OR, Exclusive OR, and Bit Clear.
Syntax
ANDS {Rd,} Rn, Rm
ORRS {Rd,} Rn, Rm
EORS {Rd,} Rn, Rm
BICS {Rd,} Rn, Rm

CMP and CMN

Compare and Compare Negative.
Syntax
CMN Rn, Rm
CMP Rn, #imm
CMP Rn, Rm
Where:
Rn is the register holding the first operand.
Rm is the register to compare with.
imm is the immediate value to compare with
Restrictions
CMN instruction Rn, and Rm must only specify R0-R7.
CMP instruction:
--Rn and Rm can specify R0-R14
--Immediate must be in the range 0-255.
Condition flags
Update the N, Z, C and V flags according to the result

TST
Test bits.
Syntax TST Rn, Rm

Where:
Rn is the register holding the first operand
Rm the register to test against
Restrictions
Rn and Rm must only specify R0-R7
Condition flags
Updates the N and Z flags according to the result
Does not affect the C or V flags.

ASR, LSL, LSR, and ROR

Arithmetic Shift Right, Logical Shift Left, Logical Shift Right, and Rotate Right.
Syntax
ASRS {Rd,} Rm, Rs
ASRS {Rd,} Rm, #imm
LSLS {Rd,} Rm, Rs
LSLS {Rd,} Rm, #imm
LSRS {Rd,} Rm, Rs
LSRS {Rd,} Rm, #imm
RORS {Rd,} Rm, Rs
Restrictions
Rd, Rm, and Rs must only specify R0-R7.
For non-immediate instructions, Rd and Rm must specify the same register.
Condition flags
Update the N and Z flags according to the result.
C flag is updated to the last bit shifted out, except when the shift length is 0
V flag is left unmodified.

REV, REV16, and REVSH

Reverse bytes.
Syntax
REV Rd, Rn
REV16
Rd, Rn
REVSH
Rd, Rn
Where:
Rd is the destination register.
Rn is the source register

SXT and UXT

Sign extend and Zero extend.
Syntax
SXTB Rd, Rm
SXTH Rd, Rm
UXTB Rd, Rm
UXTH Rd, Rm
Where:
Rd is the destination register.
Rm is the register holding the value to be extended