Programmers Model

Table 3-1 Cortex-M0+ instruction summary (continued)

Operation

Description

Assembler

Cycles

Logical

AND

ANDS Rd, Rd, Rm

Exclusive OR

EORS Rd, Rd, Rm

OR

ORRS Rd, Rd, Rm

Bit clear

BICS Rd, Rd, Rm

Move NOT

MVNS Rd, Rm

AND test

TST Rn, Rm

Logical shift left by immediate

LSLS Rd, Rm, #<shift>

Logical shift left by register

LSLS Rd, Rd, Rs

Logical shift right by immediate

LSRS Rd, Rm, #<shift>

Logical shift right by register

LSRS Rd, Rd, Rs

Arithmetic shift right

ASRS Rd, Rm, #<shift>

Arithmetic shift right by register

ASRS Rd, Rd, Rs

Rotate

Rotate right by register

RORS Rd, Rd, Rs

Load

Word, immediate offset

LDR Rd, [Rn, #<imm>]

2 or 1b

Halfword, immediate offset

LDRH Rd, [Rn, #<imm>]

2 or 1b

Byte, immediate offset

LDRB Rd, [Rn, #<imm>]

2 or 1b

Word, register offset

LDR Rd, [Rn, Rm]

2 or 1b

Halfword, register offset

LDRH Rd, [Rn, Rm]

2 or 1b

Signed halfword, register offset

LDRSH Rd, [Rn, Rm]

2 or 1b

Byte, register offset

LDRB Rd, [Rn, Rm]

2 or 1b

Signed byte, register offset

LDRSB Rd, [Rn, Rm]

2 or 1b

PC-relative

LDR Rd, <label>

2 or 1b

SP-relative

LDR Rd, [SP, #<imm>]

2 or 1b

Multiple, excluding base

LDM Rn!, {<loreglist>}

1+Nc

Multiple, including base

LDM Rn, {<loreglist>}

1+Nc

Shift

ARM DDI 0484C

ID011713

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