Programmers Model

Table 3-1 Cortex-M0+ instruction summary (continued)

Operation

Description

Assembler

Cycles

Store

Word, immediate offset

STR Rd, [Rn, #<imm>]

2 or 1b

Halfword, immediate offset

STRH Rd, [Rn, #<imm>]

2 or 1b

Byte, immediate offset

STRB Rd, [Rn, #<imm>]

2 or 1b

Word, register offset

STR Rd, [Rn, Rm]

2 or 1b

Halfword, register offset

STRH Rd, [Rn, Rm]

2 or 1b

Byte, register offset

STRB Rd, [Rn, Rm]

2 or 1b

SP-relative

STR Rd, [SP, #<imm>]

2 or 1b

Multiple

STM Rn!, {<loreglist>}

1+Nc

Push

PUSH {<loreglist>}

1+Nc

Push with link register

PUSH {<loreglist>, LR}

1+Nd

Pop

POP {<loreglist>}

1+Nc

Pop and return

POP {<loreglist>, PC}

3+Nd

Conditional

B<cc> <label>

1 or 2e

Unconditional

B <label>

With link

BL <label>

With exchange

BX Rm

With link and exchange

BLX Rm

Signed halfword to word

SXTH Rd, Rm

Signed byte to word

SXTB Rd, Rm

Unsigned halfword

UXTH Rd, Rm

Unsigned byte

UXTB Rd, Rm

Bytes in word

REV Rd, Rm

Bytes in both halfwords

REV16 Rd, Rm

Signed bottom half word

REVSH Rd, Rm

Supervisor Call

SVC #<imm>

-f

Disable interrupts

CPSID i

Enable interrupts

CPSIE i

Read special register

MRS Rd, <specreg>

Write special register

MSR <specreg>, Rn

Breakpoint

BKPT #<imm>

-f

Push

Pop

Branch

Extend

Reverse

State change

ARM DDI 0484C

ID011713

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