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An Introduction to
Electromigration-Aware Physical Design
Jens Lienig
Dresden University of Technology
Dresden, Germany
Contents
1 Introduction
2 Electromigration Issues
3 Electromigration-Dependent Design Parameters
4 Physical Design Methodologies Addressing Electromigration
Current-Driven Routing
Current-Density Verification
Current-Driven Decompaction
5 Summary
J. Lienig: An Introduction to Electromigration-Aware Physical Design, ISPD 2006, pp. 39-46
Contents
1 Introduction
5 Summary
Introduction: Electromigration
Electromigration (EM):
Electromigration is the forced movement of metal ions due to an
electric field
Ftotal = Fdirect + Fwind
Direct action of
electric field on
metal ions
Anode
+
Force on metal ions resulting from

momentum transfer from the
conduction electrons
<<
Al
Al+
Cathode
-
Note: For simplicity, the term electron wind force often refers to the net effect of these
two electrical forces
Introduction: Electromigration
=> Metal atoms (ions) travel toward the positive end of the conductor
while vacancies move toward the negative end
Effects of electromigration in metal interconnects:

Depletion of atoms (Voids):
Slow reduction of connectivity
Interconnect failure
Voids
Deposition of atoms
(Hillocks, Whisker):
Short cuts
Hillocks
http://ap.polyu.edu.hk/apavclo/public/gallery.htm
http://www.usenix.org/events/sec01/full_papers/gutmann/gutmann_html
http://www.usenix.org/events/sec01/full_papers/gutmann/gutmann_html
Common Failure Mechanisms in Integrated Circuits
A) Line Depletion
Metal2 Cu
Ta/TaN
Liner Layer
SiN, NSiC
Cap Layer
Metal1 Cu
Void
Low
Dielectric
B) Via Depletion
Metal2 Cu
Metal1 Cu
Ta/TaN
Liner Layer
SiN, NSiC
Cap Layer
e
Void
Low
Dielectric
9
www.lamel.bo.cnr.it/research/ elettronica/em/rel_res.htm
10
Electromigration and Current Density
Blacks Equation [1]:

Mean time to failure of a single wire due to electromigration
Cross-section-areadependent constant
MTTF =
A
Ea
exp
n
J
k T
Current density
Scaling factor
(usually set to 2)
Activation energy
for electromigration
Temperature
Boltzmann constant
-> Current density is the major parameter in addressing electromigration

during physical design
11
Why is Electromigration Becoming a Problem?
J=
I
A
J
Jref
1
I
Iref
A
Aref
1996 (ref)
2006
12
Why is Electromigration Becoming a Problem? (contd.)
Imax(Time) / Imax (1996)
Industry Example (Robert Bosch GmbH):

Maximum tolerable current in minimum line width interconnect
(Metal1, Al) due to technology scaling
Reduction 1996 - 2006: 95 %
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1996
2000
2001
2002
2003
2004
2005
2006
13
Why is Electromigration Becoming a Problem? (contd.)
# Nets
# Nets(ref)
Industry Example (Robert Bosch GmbH):

Critical nets: Nets with currents near or above
maximum tolerable current value
100
-> Manual consideration of

electromigration problem
no longer feasible
10
c
Un
e
ln
a
c
riti
ts
Critical nets
1996 (ref)
2006
14
Maximum Tolerable Current Densities

Conventional metal wires (house wiring, etc.)
19,100 A/cm2
30,400 A/cm2
Al
Cu
reaching melting temperature due to Joule heating
Melting temperature limits maximum current densities

Thin film interconnect on integrated circuits can sustain current densities
up to 1010 A/cm2 before reaching melting temperature, however, at
Al
Cu
(Jmax(Cu) 5* Jmax(Al) )
200,000 A/cm2
1,000,000 A/cm2
it reaches its maximum value due to the occurance of electromigration
Electromigration limits maximum current densities

15
Contents
1 Introduction
5 Summary
16
History of Electromigration Research
1861
Discovery of electromigration by M. Gerardin
1950s
First systematic studies of electromigration by

W. Seith and H. Wever (Correlation between the direction of
the current flow and the material transport)
1960s
Electromigration is recognized as one of the main reasons

for IC failure
1967
J. R. Black: Relationship between MTTF (mean time to failure)

and current density and temperature (Blacks law [1])
1975
I. A. Blech: Discovery of immortal wires by considering the

product of current density and wire length (Blech length [2])
17
Migration in Solid State Materials
Migration in Solid State Materials
Stress Migration
Electromigration
Thermomigration
due to
mechanical stress
due to
electric field
due to
thermal gradient
Electrolytic electromigration
Solid state electromigration
18
Diffusion Processes and Activation Energies EA
Grain: homogeneous
lattice of metal atoms
Grain boundary:
shift in the orientation
of the lattice
Triple Point
19
Diffusion Processes and Activation Energies EA
Al
Al
Grain Boundary
Diffusion
Triple Point
EA_GRAIN= 0.7 eV (Al)

EA_GRAIN= 1.2 eV (Cu)
Grain
Al
Al
Al
Al
Bulk Diffusion
Al
Al
Al
Al
Al
Al
EA_BULK= 1.2 eV (Al)

EA_BULK= 2.3 eV (Cu)
Al
Surface Diffusion
EA_SURF.= 0.8 eV (Al)
Aluminum:
Copper:
Grain Boundary Diffusion

+ Surface Diffusion
Surface Diffusion
EA_SURF.= 0.8 eV (Cu)
20
Special Effects (1): Bamboo Wires
MTTF [h]
Diffusion
I = constant
T = constant
w
Grain Boundary
w < Grains
(Bamboo Wires)
w = Grains
wMTTF_min
Wire Width w [m]

21
Special Effects (2): Immortal Wires

FN1
FN2
FN3
FN4
FN5
Electromigration (EM)
Stress Migration (SM)
Al+Al+
Al+ Al+
Al+
Al+
+
FN1
Al+
FN2
FN3
FN4
Al+ Al+
Al+ Al+
Al+ Al+
FN1
Equilibrium between EM and SM
if lsegment < Blech length
FN5
Al+
FN2
Al+
FN3
Al+ Al+
FN4
FN5
Al+ Al+
22
Maximum Current Density With Regard to Temperature
Blacks Equation [1]:

Mean time to failure of a single wire due to electromigration
Cross-section-areadependent constant
MTTF =
A
Ea
exp
n
J
k T
Current density
Scaling factor
(usually set to 2)
Activation energy
Temperature
Boltzmann constant
23
Maximum Current Density With Regard to Temperature
Jmax(T) compared to Jmax(Tref = 25 C) [Black1969]
Jmax(T) / Jmax(T = 25 C)
100
10
1
-40
25
60
80
100
125
150
175
0,1
Consumer Electronics
0,01
MTTF(T) = MTTF(TRef)
Temperature T [Celsius]
Automotive Electronics
Example: A temperature rise of 100 K in an Al metallization reduces the

permissible current density by about 90 %.
24
Contents
1 Introduction
5 Summary
25
Which Physical Design Parameters Effect Electromigration?
Local current density
! Wire widths and via sizes

(number of vias)
Homogeneity of the current flow
! Wire shapes, corner bends,

via arrangements, etc.
Current distribution within

device pins
! Current-density-correct pin
connections
Temperature-dependency of
the maximum current density
! Temperature of the
chip/interconnect
Immortal wires
! Segment length below Blech

length
26
(a) Wire Widths

Minimal wire width wmin:
Jmax/peak Layer- and current-type

dependent maximum
permissible current density
at reference temperature Tref
dLayer
I
IRMS/AVG Current (rms, avg, peak)

Ipeak
wmin
I RMS / AVG f ( w)
d Layer J max (Tref ) f (T )
wmin = max
Working temperature
Tref
Reference temperature
f(w)
Grain-size-dependent
width scaling factor
wmin_process Process-dependent
minimum wire width
I peak f ( w)
d Layer J peak (Tref ) f (T )
wmin_process
Scaling factor (n = 2 [1])
EA
Activation energy
Boltzmann constant
Temperature scaling f(T), if T Tref :
EA
f (T ) = exp
n k T
ref
Tref
1
T
Blacks law with MTTF(T) = MTTF(Tref)
27
(a) Via Sizes

Minimal number of single vias Nmin per via array:
Imax_via,
Ipeak_via
N min = max
I RMS / AVG s
ceil
I max _ via (Tref ) f (T )
I peak s
ceil
I peak _ via (Tref ) f (T )
Maximum permissible
via current at reference
temperature Tref
IRMS/AVG Via current (rms, avg, peak)

Ipeak
s
Safety factor (1.1 1.2)
Working temperature
Tref
Reference temperature
Scaling factor (n = 2 [1])
EA
Activation energy
Boltzmann constant
Temperature scaling f(T), if T Tref :
EA
f (T ) = exp
n k T
ref
Tref
1
T
Blacks law with MTTF(T) = MTTF(Tref)
28
(b) Homogeneity of the Current Flow: Wire Shapes, Corner Bends
I2
min
I1
I1 + I2
max
Inhomogeneous current flow
-> Avoiding of 90-degree corners, rapid width changes, etc.

29
(b) Homogeneity of the Current Flow: Via Arrangements
Metal1
I
Metal2
min
Metal1
I
Metal2
max
30
(c) Current-Density-Correct Pin Connections
Pin of a DMOS transistor

31
?
?
32
2 mA
1 mA
0.5 mA
1 mA
0.5 mA
3 mA
2 mA
33
Contents
1 Introduction
5 Summary
34
Electromigration-Aware (Analog) Physical Design Flow

Circuit Simulation
Start
Physical
Design
Schematic
Partitioning + Floorplanning
Placement
EM
Violations
Yes
Current-Driven Layout
Decompaction
No
ElectromigrationRobust Design
39
Electromigration-Aware (Analog) Physical Design Flow

Circuit Simulation
Start
Physical
Design
Schematic
Placement
EM
Violations
Yes
Decompaction
No
40
Goals:
Routing with current-correct wire widths and via sizes
Minimization of wire area
Major steps:
1. Concurrent wire planning and segment current determination
2. Calculation of wire widths and via sizes
3. Two-point detailed routing with provided wire widths and via sizes
41
Cyclic Conflict in Topology and Current Flow Determination

-2 mA
Complete net
topology...
1 mA
4 mA
T1
T4
3 mA
T2
1 mA
requires
T3
requires
-3 mA
-2 mA
2 mA
4 mA
T1
T4
Current flow within

net segments
2 mA
T2
1 mA
-> (1) Wire planning

(2) Detailed routing
T3
-3 mA
42
Current-Driven Routing: Algorithm
Schematics
Floorplanning
Placement
Routing Routing
Current-Driven
Current-Density
Verification
Violations
Current Characterization
Wire Planning
Topology Planning (Area
Minimization)
Pin Connections Check
Calculation of Wire Widths
and Via Sizes
Routing Tree
Path Widths
DRC & LVS
Detailed Routing of TwoPoint Connections
Fabrication
44
Circuit Simulation
Start
Physical
Design
Schematic
Placement
EM
Violations
Yes
Decompaction
No
50
Goal:
Automatic verification of actual current densities within arbitrarily

shaped layout structures: JWire/Via (T, Layer) JMax (T, Layer)
Major steps:
1. Determination of maximum current densities in each layer
2. Calculation of actual current densities within layout structures
3. If actual current density exceeds maximum value:
mark violating areas and violation degrees
51
Current-Density Verification: Algorithm
Schematics
Floorplanning
Placement
Current Characterization
Pin and port verification

Selection of critical
nets
Current-Density
Verification
Violations
Detailed FEM analysis

of critical nets
DRC & LVS
Visualization of errors
Fabrication
53
Detailed FEM Analysis of Critical Nets
1. Assignment of current values

at device pins and net ports
2. Layout segmentation into
finite elements (triangles)
3. Calculation of the electric
potential field (x,y) using FEM
4. Calculation of current density J

out of potential field gradient
J=-1/ grad((x,y))
5. Comparison of calculated
current density in every finite
element with its maximum
permissible value
3
1
6. Visualization of the violating

areas
54
Current-density violations
within via array
Current-density violations
within interconnect
55
DRC errors:
Current density violation
in Metal_1 (>=20%, <50%)
56
Current-Density Visualization
I
min
max
58
Current-Driven Layout Decompaction

Circuit Simulation
Start
Physical
Design
Schematic
Placement
EM
Violations
Yes
Decompaction
No
60
Current-Driven Layout Decompaction
Goals:
Post-routing adjustment of layout segments according to
their actual current density
Homogenization of the current flow
Major steps:
1. Current-density verification
2. Calculation of wire widths and via sizes according to actual currents
in violating net segments
3. Addition of support polygons
4. Layout decompaction
61
Current-Driven Layout Decompaction: Algorithm
Schematics
Floorplanning
Placement
Current-Density
Verification
Violations?
Current-Driven
Layout
Decompaction
No
DRC & LVS
Layout Decomposition
Wire and Via Array
Sizing
Addition of Support
Polygons
Layout Decompaction
Fabrication
63
Current-Driven Layout Decompaction: Example

(1) Routed net
64

(2) Current-density verification
65

(3) Calculation of currents within violating net segments
Actual current in
net segment?
66

(4) Calculation of wire widths and via sizes according to actual currents
Width calculation
67

(5) After layout decompaction
Extended
wires and vias
Support polygons
68
Contents
1 Introduction
5 Summary
69
Summary
Electromigration: migration of atoms due to momentum transfer from

conduction electrons
Al: grain boundary diffusion, Cu: surface diffusion
! Electromigration is becoming a design problem due to increased

current densities related to IC down-scaling
Technology solutions:
(1) Cu instead of Al -> Jmax(Cu) 5* Jmax(Al)

(2) Bamboo structures, Blech length,
Physical design solutions: (1) Current density

(2) Temperature
! Model: Blacks law [1] (MTTF of interconnect and its relationship to
current density and temperature)
70
Summary (2)
Two methodologies for current-density correct interconnect generation:

- Current-driven routing
Solving the cyclic topology/current problem via two-step approach:

wire planning and subsequent two-point detailed routing
- Current-driven layout decompaction
All currents are known (no cyclic topology/current problem)

Requires current-density verification and decompaction tool
Current-density verification
Verification of arbitrarily shaped custom circuit layouts

Incorporates thermal simulation data
! Current-density verification must be an integral part of any future

design flow
71
References
[1]
Black, J.R. : Electromigration - A brief survey and some recent results;

Proc. of IEEE Reliability Physics Symposium, Washington D.C., 1968.
[2]
Blech, I.A. : Electromigration in thin film aluminium films on titanium nitride;

Journal of Applied Physics, Vol. 47, No. 4, 1976.
[3]
Maiz, J.A.: Characterization of electromigration under bi-directional (BC) and

pulsed unidirectional (PDC) currents; Proc. of IEEE-International Reliability
Physics Symposium, pp. 220-223, 1989.
[4]
Lienig, J., Jerke, G., Adler, Th.: Electromigration avoidance in analog circuits: two
methodologies for current-driven routing; Proc. of the 7th Asia and South Pacific
Design Automation Conference, IEEE Press, Bangalore, India, January 2002.
[5]
Lienig, J., Jerke, G.: Current-driven wire planning for electromigration avoidance
in analog circuits; Proc. of the 8th Asia and South Pacific Design
Automation Conference (ASP-DAC), Kitakyushu, Japan, pp. 783-788, 2003.
[6]
Jerke, G., Lienig, J.: Hierarchical current density verification in arbitrarily shaped
metallization patterns of analog circuits; IEEE Transactions on Computer-Aided
Design of Integrated Circuits and Systems, vol. 23, no.1, pp. 80-90, Jan. 2004.
[7]
Jerke, G., Lienig, J., Scheible, J.: Reliability-driven layout decompaction for
electromigration failure avoidance in complex mixed-signal IC designs;
Proc. of the 41st Design Automation Conference, San Diego, CA, pp. 181-184, 2004.
[8]
Adler, T., Barke, E.: Single step current driven routing of multiterminal signal nets
for analog applications; Proc. of Design, Automation and Test in Europe (DATE),
pp. 446-450, 2000.
72

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An Introduction to

Electromigration-Aware Physical Design

J. Lienig: An Introduction to Electromigration-Aware Physical Design, ISPD 2006, pp. 39-46

J. Lienig: An Introduction to Electromigration-Aware Physical Design, ISPD 2006, pp. 39-46

Force on metal ions resulting from

Effects of electromigration in metal interconnects:

J. Lienig: An Introduction to Electromigration-Aware Physical Design, ISPD 2006, pp. 39-46

Common Failure Mechanisms in Integrated Circuits

J. Lienig: An Introduction to Electromigration-Aware Physical Design, ISPD 2006, pp. 39-46

J. Lienig: An Introduction to Electromigration-Aware Physical Design, ISPD 2006, pp. 39-46

Electromigration and Current Density

Blacks Equation [1]:

-> Current density is the major parameter in addressing electromigration

Why is Electromigration Becoming a Problem?

Why is Electromigration Becoming a Problem? (contd.)

Imax(Time) / Imax (1996)

Industry Example (Robert Bosch GmbH):

Reduction 1996 - 2006: 95 %

J. Lienig: An Introduction to Electromigration-Aware Physical Design, ISPD 2006, pp. 39-46

Why is Electromigration Becoming a Problem? (contd.)

Industry Example (Robert Bosch GmbH):

-> Manual consideration of

Maximum Tolerable Current Densities

reaching melting temperature due to Joule heating

Melting temperature limits maximum current densities

it reaches its maximum value due to the occurance of electromigration

Electromigration limits maximum current densities

J. Lienig: An Introduction to Electromigration-Aware Physical Design, ISPD 2006, pp. 39-46

History of Electromigration Research

Discovery of electromigration by M. Gerardin

First systematic studies of electromigration by

Electromigration is recognized as one of the main reasons

J. R. Black: Relationship between MTTF (mean time to failure)

I. A. Blech: Discovery of immortal wires by considering the

J. Lienig: An Introduction to Electromigration-Aware Physical Design, ISPD 2006, pp. 39-46

Migration in Solid State Materials

Migration in Solid State Materials

Solid state electromigration

J. Lienig: An Introduction to Electromigration-Aware Physical Design, ISPD 2006, pp. 39-46

Diffusion Processes and Activation Energies EA

J. Lienig: An Introduction to Electromigration-Aware Physical Design, ISPD 2006, pp. 39-46

Diffusion Processes and Activation Energies EA

EA_GRAIN= 0.7 eV (Al)

EA_BULK= 1.2 eV (Al)

Grain Boundary Diffusion

J. Lienig: An Introduction to Electromigration-Aware Physical Design, ISPD 2006, pp. 39-46

EA_SURF.= 0.8 eV (Cu)

Special Effects (1): Bamboo Wires

Wire Width w [m]

Special Effects (2): Immortal Wires

J. Lienig: An Introduction to Electromigration-Aware Physical Design, ISPD 2006, pp. 39-46

Maximum Current Density With Regard to Temperature

Blacks Equation [1]:

J. Lienig: An Introduction to Electromigration-Aware Physical Design, ISPD 2006, pp. 39-46

Maximum Current Density With Regard to Temperature

Jmax(T) compared to Jmax(Tref = 25 C) [Black1969]

Example: A temperature rise of 100 K in an Al metallization reduces the

J. Lienig: An Introduction to Electromigration-Aware Physical Design, ISPD 2006, pp. 39-46

Which Physical Design Parameters Effect Electromigration?

Local current density

! Wire widths and via sizes

Homogeneity of the current flow

! Wire shapes, corner bends,