Evolution of Microelectronics

(from discrete devices to modern Integrated Circuits - a brief review)

Gourab Dutta
Department of Electronics and Electrical Comm. Engg.
IIT Kharagpur
gdutta@ece.iitkgp.ac.in

1
 Electronics
Electronics: “The branch of physics and technology concerned with the design of circuits
using transistors and microchips, and with the behaviour and movement of electrons in a
semiconductor, conductor, vacuum, or gas.”*
Electrons:
Two kinds of charges: when glass is rubbed with resin
Cathode Rays: If an evacuated glass tube is equipped with two
electrodes and a voltage is applied, the glass opposite the negative
electrode is observed to glow from electrons emitted from the cathode
Edison Effect (1885): Thomas Edison observed that a current flowed
between the filament of an incandescent lamp and a plate kept in
vacuum near it when the plate was connected to the positive end of the
filament; but no current when the plate was connected to the negative
terminal.
In 1891, G. Johnstone Stoney coined the word "electron"
(the word had been used to denote the unit of charge found in experiments that passed
electric current through chemicals)
2
*en.oxforddictionaries.com https://royalsocietypublishing.org/doi/pdf/10.1098/rspl.1884.0093
 Electrons
• In 1899, J. J. Thomson showed that the current was due to a
stream of negatively-charged particles, electrons, that could
be guided by electric and magnetic fields. He indicated that
cathode rays are charged particles (which he called
"corpuscles") which are constituents of the atom. He also
showed that their charge-to-mass ratio (e/m) was
independent of cathode material.
• de Broglie hypothesis (1924) - wave-like phenomena
exhibited by particles of matter
• In 1927, G. P. Thomson (son of J.J. Thomson) performed
experiments on electron scattering through celluloids that
revealed diffraction effects characteristic of wave nature J.J. Thomson G.P. Thomson
1906 1937
‘It has been quipped that J.J. Thomson got the Nobel prize for discovering that electrons are
particles, and G.P. Thomson got it for discovering that they aren't.’
3
https://history.aip.org/history/exhibits/electron/ American Institute of Physics (AIP)
 Vacuum Tubes
Vacuum tube is a device that controls electric current Glass tube

flow in a high vacuum between electrodes to which an

electric potential difference has been applied. Most a
tubes have glass envelopes with a glass-to-metal seal
base
k

Vacuum tube Diode Vacuum tube Triode

4
https://mysite.du.edu/~etuttle/electron/elect27.htm
 Vacuum Tubes
as Rectifier:

Audio amplifier
using Vacuum tubes
as Amplifier: Vacuum tube with
metal envelope

Around 1935, the metal envelope was developed

First Transatlantic phone call in 1956 using TAT-1 cable system;

TransAtlantic Telephone (TAT-1) cable system used vacuum tubes The New York Times, Front page
Sep. 26, 1956
as repeater
5
http://atlantic-cable.com/Cables/1956TAT-1/
 Vacuum Tubes - Disadvantages
• Bulky, hence less suitable for portable products.
• Generally requires higher operating voltage.
• High power consumption; (needs heater supply that
generates waste heat and yields lower efficiency)
• shorter lifetimes
• Usually higher cost than equivalent transistors

6
The Era of Semiconductor Devices

7
Advancement in data processing & storage

5 MB Hard Disk
ENIAC 1942
(18000 valves, 1800 sq. ft.)
(IBM, 1956)

30 TB Solid State Drive

(Samsung, 2018)

Volta chip (Nvidia, 2017) 8

 Pre-Transistor Era
In 1833, Michael Faraday observed that electrical conduction increases
with temperature in silver sulfide crystals which he described as the
"extraordinary case" as this is the opposite to that observed in copper and
other metals. (First Semiconductor Effect is Recorded)

In 1874, Semiconductor point-contact rectifier effect is discovered by Michael Faraday

Ferdinand Braun (Contact of metal and lead sulphide)

In 1901, Jagadish Chandra Bose filed a U.S patent for a point-contact

semiconductor (PbS) rectifier for detecting radio signals
J. C. Bose
In 1926, Lilienfield proposed the concept of Field Effect Semiconductor
Devices

9
 Point contact transistors (1947-48)
Material: Germanium
Type: contact type
Inventors: Bardeen1 and Brattain2
(Bardeen, Brattain and Shockley3 - Nobel Prize in Physics 1956)* 1 2
These devices are not very reliable 3
Transistor action was not properly understood
(surface / bulk phenomenon?)

It is easy to make a device

which shows the transistor
action, but difficult to make
a device with specific
characteristics!

10
* see next slide for details PROCEEDINGS OF THE IEEE, VOL. 86, NO. 1, 1998
 Bipolar Junction Transistors (1948)
BJT theory proposed by Shockley
Theory and operation of the bipolar junction transistors
were developed before physical demonstration of BJT
Junction transistors patent filed on 1948*
Shockley's famous book ‘Electrons and Holes in
Semiconductors’ published in 1950.
AT&T licensed the transistor technology to other William Shockley (1910-1989)
companies (1952) and the first product was hearing aid

The first grown junction transistor (Ge)

11
* US patent 2569347A
Alloy Junction Transistors

12
Semiconductor Heterostructures & Heterojunction Bipolar Transistors
In 2000, H. Kroemer and Z. I. Alferov was awarded the Nobel Prize in
Physics "for developing semiconductor heterostructures used in high-
speed- and opto-electronics“ [idea developed in 60’s]

Their contributions has lead to the development of HBTs, lasers, solar Zhores I. Alferov Herbert Kroemer
cells, LEDs (heterojunction electronics)

Heterojunction bipolar transistor (HBT) is a type of BJT which uses

different semiconductor materials for the emitter and base regions,
creating a heterojunction. As a result, HBT can handle signals of very
high frequencies (up to several hundred GHz).

The idea is to limit the injection of holes from the base into the
emitter region, since the potential barrier in the valence band is Band diagram of a HBT
higher than in the conduction band.
Example: SiGe HBTs 13
 Junction Field Effect Transistors (1951)
Junction Field Effect Transistors (JFETs)
• In 1951, Shockley reinvented the field effect transistor
• Shockley proposed to use the space-charge region of a reverse-
biased p-n junction to modulate the area (channel) of a
semiconductor material in which charge carriers could flow.
n-Ge
• Since these devices only use the majority carriers for
conduction, he called these devices “unipolar” transistor.
• In 1952, alloy type JFETs have been demonstrated physically
• However, fabricated devices did not showed appreciable
JFET
advantages compared to existing bipolar transistors and were
difficult to fabricate. So, the field-effect transistor went back
into obscurity!!
Compare JFET and MOSFET!!
14
I. M. Ross, Proceedings of IEEE, vol. 86, pp. 7-28, 1998
 Birth of Fairchild
Shockley established the Shockley Semiconductor Lab (SSL)
in 1956 and recruited brightest graduates.
Initial objective: to develop ‘4-layer diode’ that would have better
performance than existing transistors.
in Sept 1957, “Traitorous eight” left SSL and formed Fairchild
semiconductor [funded by Sherman Fairchild] *see next slide
Fairchild semiconductor focused on Silicon instead of Germanium for
making Transistors
In October 1957, first man made satellite - Sputnik
Space Race Began
Strong need of airborne electronics to be small and reliable
‘The Fairchild Eight’
In 1958, Fairchild sold its first transistors ($150/piece) for B-70 bomber
(material is cheap but the fabrication process is costly!)
15
http://www.computerhistory.org/siliconengine/silicon-mesa-transistors-enter-commercial-production/
 Historic Moment!

A symbolic contract signed by the Fairchild founders and bankers on September 19, 1957

16
http://www.computerhistory.org
 Mesa / Planar Transistors?
Before 1959, all transistors* were of mesa type (including Bell Lab’s)
Mesa transistors have exposed p-n junctions which resulted in long term performance
instability (exposed p-n junctions are highly sensitive to contamination and moisture)
Jean Hoerni proposed to protect the p-n junctions by keeping the silicon dioxide layer in
place which was used for diffusion process. Invention of Planar Transistors. [At that
time, the standard practice was to etch that oxide layer away, baring the junctions]
Planar Transistors showed better performance and reliability compared to mesa type.
Fairchild started production of Planner transistors, others followed soon.
Planner
process
n p p
n made the
n p
Integrated
Moore @ Fairchild Hoerni @ Fairchild Circuit a
Jean Hoerni reality
17
“The Silicon Dioxide Solution”- IEEE Spectrum, December 2007
 Integrated Circuits (ICs)

Discrete components

Integrated circuit
Integrated Circuits (ICs)
Integrated circuit is a set of electronic circuit on a small piece of
semiconducting material primarily silicon. Integration of large number of
electronic components (both active and passive) on a single chip results
Circuit using discrete components
in reduction in size, cost and power consumption, and increase in
operational speed and reliability. 18
 Invention of Integrated Circuits (ICs)
Jack Kilby in 1958 demonstrated that it was possible to make
transistors, diodes, capacitors, and resistors in a single piece of
semiconductor and interconnect them to create functioning
circuits. Kilby used wire bonding to interconnect the components
within the chip.
However, this method has several challenges: difficulty in Jack Kilby
manufacturing and limitation in number of components per chip.

Robert Noyce proposed replacing the wires with the batch

deposition of aluminum on the planar structure. (the practical
approach!!)
Contribution of Jean Hoerni
Kilby was awarded the Nobel Prize in 2000. Robert Noyce

(Noyce was no more at that time and missed the Nobel)

19
“The Invention of the Transistor”- PROCEEDINGS OF THE IEEE, 86, 1998
 Integrated Circuits (ICs)
https://en.wikipedia.org/wiki/Invention_of_the_integrated_circuit

Logical NOR IC from the computer that

controlled the Apollo Spacecraft

Compare!

IC
Year: 1960 Year: 1990
4 BJTs + 1 resistor more than million MOSFETs
20
 Moore’s Law
Gordon Moore, Ph.D. in Chemistry from Caltech
SSL → Fairchild → Intel (Scientific Carrier of Moore)
Moore’s Observation: Density of electronic components in a IC
doubles in every year (1965). (based on only few data points)
Later in 1975, this was changed to density doubles in every two
years

This prediction has become a target

for miniaturization in the semiconductor
industry.

A. Ostendorf et al., 2015 21

 Fairchild, Fairchildren and Silicon Valley
San Francisco Bay Area was not an easy place for the first
computer chip entrepreneurs.
A few ambitious entrepreneurs can make a great change!!
In Silicon Valley “70 percent of these firms can be traced directly back to
the founders and employees of Fairchild. The 92 public companies that
can be traced to Fairchild are now worth about $2.1 trillion, which is
more than the annual GDP of Canada, India, or Spain.” Endeavor, 2014 Fairchild Semiconductor, 1961

Robert Norton Noyce (1927 – 1990), nicknamed "the

Mayor of Silicon Valley"
“Fairchild Semiconductor was like a ripe dandelion, you
blow on it and the seeds of entrepreneurship spread on the
wind” – Steve Jobs
New Endeavor Insight Report Analyzes the Source of Silicon Valley's Development 2014, endeavor.org Steve and Noyce
22
‘Jobs and Intel’s Noyce Forged Early Bond’-The Wall Street Journal, 2011
 Birth of MOSFETs
Theory of FETs patented by Lilienfield in 1926.
Dielectric/semiconductor interface plays the most crucial role in
MOS devices and realizing a good interface is really challenging
Julius Edgar Lilienfeld
First demonstration in 1960 at Bell Lab by Atalla and Kahng
(thermally grown SiO2/Si interface – interface states!!)
It was found that MOSFETs can be easily scaled than BJTs
However, have to face many difficulties mostly due to
oxide/semiconductor interface and Na+ ions Martin Atalla Dawon Kahng
Frank Wanlass of Fairchild invented the CMOS (1963). But
Fairchild showed little interest in CMOS. Frank joined the General
Microelectronics as the director of research and engineering
Today > 90% of all semiconductor revenue comes from MOS
based devices
Frank Wanlass23
 MOSFET technology
MOSFETs fabrication started with Al as a gate metal.

In 1968, polycrystalline-Si (poly-Si) gate technology

was invented and this technology showed many
advantages.

Why Poly-Si gate?

• Can withstand high temperature process
• Self-aligned source and drain can be formed
• Lowering the threshold voltage (VT)

* poly-Si gate must be doped heavily 24

 CMOS technology

MOSFET Complementary MOSFET (CMOS)

Advantages of CMOS:
• Very low static power dissipation
• Compact size
• High noise margin

CMOS inverter 25
 Birth of Intel
Founded by Gordon Moore and Robert Noyce (1968)

In 1971, the first commercially available Microprocessor Intel 4004

It runs at 108 kHz, has 2250 transistors, and is created using 10 µm technology

26
 Scaling: Dennard’s approach

In 1974, Robert H. Dennard described

how transistors can be scaled reliably
to smaller dimensions. (essence of
Moore’s Law).

The Dennard scaling shows how to

reduce the transistor’s major
parameters, including the operating
voltage, capacitance, and power, as
the transistors become smaller.

*** Robert H. Dennard has also invented the DRAM in 1966***

27
 Scaling and Technology Node
‘The technology node (also process node, process technology or simply node) refers to a specific
semiconductor manufacturing process and its design rules. Different nodes often imply different circuit
generations and architectures. Generally, the smaller the technology node means the smaller the feature
size, producing smaller transistors which are both faster and more power-efficient. Historically, the process
node name referred to a number of different features of a transistor including the gate length as well as M1
half-pitch. Most recently, due to various marketing and discrepancies among foundries, the number itself
has lost the exact meaning it once held. Recent technology nodes such as 22 nm, 16 nm, 14 nm, and 10 nm
refer purely to a specific generation of chips made in a particular technology. It does not correspond to any
gate length or half pitch. Nevertheless, the name convention has stuck and it's what the leading foundries
call their nodes.’

0.7x CPP ⋅ 0.7x MMP ≈ ½ area

28
https://en.wikichip.org/wiki/technology_node
Scale of Integration

29
 Classification of ICs
Based on the substrate used

https://www.electricaltechnology.org/2015/04/types-of-ics-classification-of-integrated-circuits-and-their-limitation.html
http://www.circuitstoday.com/integrated-circuits 30
 Transistors at different technology node (from 2003)

Source: Intel 31
 Strained Silicon Transistors (2003)

Selective SiGe source/drain has

two benefits in PMOS:
1. Increased boron dopant
activation (reduce contact resistance)
2. Uniaxial compressive strain
increases the hole mobility

In NMOS, high stress Si3N4 film

creates uniaxial strain which
enhances electron mobility
Year: 2003, tox = 1.2 nm, Vd = 1.2 V
Intel 90 nm PMOS (left) and NMOS (right) Strained Silicon Transistors How many atomic layers?
32
Image Source: Intel tox = oxide thickness
 Need for High-K gate dielectric

Gate leakage current (Jg) for 30 nm OFF-state leakage current with

transistors with tSiO2 = 0.8 nm technology node
𝜖𝐻𝑖𝑔ℎ−𝐾
𝑡𝐻𝑖𝑔ℎ−𝐾 = 𝑡𝑆𝑖𝑂2
𝜖𝑆𝑖𝑂2 EOT – Equivalent
Oxide Thickness
(For HfO2, 𝜖𝐻𝑖𝑔ℎ−𝐾 = 25, 𝜖𝑆𝑖𝑂2 = 3.9)

If 𝑡𝑆𝑖𝑂2 = 1 nm then 𝑡𝐻𝑖𝑔ℎ−𝐾 ~ 6 nm

Higher physical thickness of gate dielectric without
compromising the gate control (gate capacitance)
But, lower gate leakage current 33
 High-K Metal Gate (HKMG) – Intel 45 nm (2007)
High-K, I understand!! Because, poly-gate has the issues..
But, why metal gate again? - poly-Si depletion
- Poly-gate resistance

“this is the biggest change in transistor technology in 40 years” - Gordon Moore

34
Intel Technology Journal, Volume 12, Issue 2, 2008
 Fact sheet – FAB 32, Intel’s 45 nm Fabrication Facility*
• Intel Corporation opened its first high-volume 45 nm
manufacturing factory (FAB 32) in 2007 at Chandler, Arizona
• Fab 32 is a $3 billion investment and construction began in 2005.
• Fab 32 is a 300 mm facility (wafer diameter). This 300 mm facility
uses 40% less energy and water per chip than a 200 mm factory.
• Fab 32 is roughly the size of 17 U.S. football fields, of which the
clean room space is approximately equal to the size of three
football fields.
• Fab 32 is a ‘Class 10’ clean room. (what does this mean?)
Class 10 clean room means in that room there are no more than 10
particles measuring 0.5 micron or larger per 1 cubic foot of air.
How is this comparable with outside air and the hospital operating
room?
Outside air ~ “Class 3 million” and hospital operating room ~“Class
10,000,” 35
www.intel.com
 SOI MOSFETs
Why SOI ?
• Ideal for radiation hard devices
• CMOS circuits on SOI has several advantages resulting
in lower power and higher speed
• Ideal for radiation hard devices
• SOI CMOS technology is simpler (no wells or trenches) Bulk MOSFET
• Better dielectric isolation in both vertical and
horizontal directions and no latch up

Simplified SOI MOSFET

SOI-CMOS
Process flow SOI->Silicon On Insulator
36
 Common types of SOI MOSFETs

GLOBAL FOUNDRIES 22 nm FD SOI

* SOI wafers are more expensive than bulk Si-wafers 37
 Planar/Tri-gate transistors

Planar 2D transistors Tri-gate 3D transistors

Intel’s 22 nm, 2011

Conventional planar transistors form a conducting channel in the silicon region under the
gate electrode when in ON state.
Tri-Gate transistors form a conducting channels on three sides of the vertical Fin
structure. It provides “fully depleted” operation.

Source: Intel Identify the gate length and width!! 38

 Planar/Tri-gate transistors

The “fully depleted” characteristics of Tri-Gate transistors provide a steeper sub-threshold

slope that reduces leakage current. The steeper sub-threshold slope can also be used to
target a lower threshold voltage, allowing the transistors to operate at lower voltage to
reduce power.
37% performance increase at low voltage
Source: Intel 39
 Tri-gate transistors with multiple fins

Tri-gate transistors with multiple fins

Multiple fins connected together increases the drive current

Source: Intel 40
 Planar & Tri-gate transistors

Source: Intel
Gate Fin 41
 Transistors at different technology node

Source: Intel 42
 Copper Interconnects
In 1997, IBM announced Copper as the interconnect
material for integrated circuit. “The IBM Shock!”
Before that Al was the primary choice.
IBM’s Microprocessor chips with copper interconnect
became faster, smaller and less expensive than chips
made with aluminum interconnects
‘Copper wires conduct electricity with about 40 percent
less resistance than aluminum wires, which results in
an additional 15 percent burst in microprocessor
speed. Copper wires are also significantly more durable
and 100 times more reliable over time, and can be
shrunk to smaller sizes than aluminum.’

https://www.ibm.com/ibm/history/ibm100/us/en/icons/copperchip/ 43
 14 nm and 10 nm Technology
Intel’s 14 nm technology provides good dimensional scaling from 22 nm. At 22 nm
node fins are taller, thinner, and more closely spaced for improved density and lower
capacitance. Improved transistors require fewer fins, further improving density, and
the SRAM cell size is almost half the area of that in 22 nm.

Intel’s 10 nm 3rD generation

process technology FinFET

Source: Intel 44
 So…….what next ?? 5 nm node

“Nanosheets: IBM’s Path to 5-Nanometer Transistors”

https://spectrum.ieee.org/nanoclast/semiconductors/devices/nanosheets-ibms-path-to-5nanometer-transistors 45
 Wafer size
• Wafer size refers to the diameter of a wafer
• Larger wafer size enables the fabrication of
more dies (chips) per wafer which translates
into cost reduction in high-volume
semiconductor manufacturing.
450 mm

With increase in wafer size, the wafer thickness also increases 46

 Foundries with Cutting Edge Logic Fab

https://en.wikichip.org/wiki/technology_node 47
 Semiconductor Industry: Global Picture

Vendors
Sectors

Semiconductor sales revenue worldwide from 1987 to 2019

(in billion U.S. dollars)

Semiconductor industry billings worldwide from 2013 to 2019, 48

by application (in billion U.S. dollars) [Source: statista]
 20

Semiconductor
Industry:
Market Share

49
Semiconductor industry is extremely competitive
50