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Vlsi Question Papers

This document contains information about the mid-term examination for the VLSI Design subject for the Electronics and Communication Engineering department. It provides three different exam question paper sets (Set A, B and C) with four questions each to choose two questions from. The exam duration is 1 hour and the total marks are 10. The questions cover various topics related to VLSI design including ripple carry adder, SRAM cell operation, FPGA principles and applications, standard cell operation, fault testing concepts, ROM decoder design, zero/one detector design and BIST implementation issues.

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1K views1 page

Vlsi Question Papers

This document contains information about the mid-term examination for the VLSI Design subject for the Electronics and Communication Engineering department. It provides three different exam question paper sets (Set A, B and C) with four questions each to choose two questions from. The exam duration is 1 hour and the total marks are 10. The questions cover various topics related to VLSI design including ripple carry adder, SRAM cell operation, FPGA principles and applications, standard cell operation, fault testing concepts, ROM decoder design, zero/one detector design and BIST implementation issues.

Uploaded by

jahnavi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
  • VLSI Design (B.Tech ECE-B): Exam paper for VLSI Design, detailing the questions and marks allocation for the exam.
  • VLSI Design (ECE-C): Another exam paper for VLSI Design specifically for ECE-C with a different set of questions and instructions.

MAHAVEER INSTITUTE OF SCIENCE AND TECHNOLOGY

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING


IV B.TECH

I-SEM I-MID EXAMINATIONS

ECE- C

SUBJECT: VLSI DESIGN


MAX MARKS: 10 M TIMES: 1 hr
Answer any 2 out of 4 Questions, each Question carries 5 Marks.

SET-A DATE OF EXAM:

1. Implement and explain the working principles of a ripple carry adder using
transmission gates.
2. (a) Draw and explain the Read/Write operation of 4T SRAM cell.
(b) Explain the principle of DRAM cell
3. Explain the operation of FPGA and write the applications of FPGA.
4. Write short notes on
(1)DFT (2) BIST (3) boundary scan testing
MAHAVEER INSTITUTE OF SCIENCE AND TECHNOLOGY
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
IV B.TECH

I-SEM I-MID EXAMINATIONS

ECE- C

SUBJECT: VLSI DESIGN


MAX MARKS: 10 M TIME: 1 hr
Answer any 2 out of 4 Questions, each Question carries 5 Marks.

SET-B

DATE OF EXAM:

1. With the help of block diagram explain the operation of standard cells.
2. (a) Explain the terms controllability observability and fault coverage
(b) What is a fault simulation?
3. Design and explain row &column decoder for NAND ROM array
4. Design and implement a tree based zero/one detector circuit.

MAHAVEER INSTITUTE OF SCIENCE AND TECHNOLOGY


DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
IV B.TECH

I-SEM I-MID EXAMINATIONS

ECE- C

SUBJECT: VLSI DESIGN


MAX MARKS: 10 M TIME: 1 hr SET-C DATE OF EXAM:
Answer any 2 out of 4 Questions, each Question carries 5 Marks.
1(a) Draw the circuit for 6 transistor SRAM &explain its working.
(b) Write the advantage of 4T SRAM cell over 6T SRAM
2. Explain antifuse based FPGA. Mention different advantages of antifuse technology.
3. Design and explain 4bit synchronous and asynchronous counter using transmission
gates
explain its working.
4. What are the issues to be considered while implementing BIST? Explain

MAHAVEER INSTITUTE OF SCIENCE AND TECHNOLOGY DEPARTMENT OF ELECTRONICS AND COMMUNICATI

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