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26 March 2018 1439 ‫ رجب‬9

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IC Layout

Lecture 05
Layout Design Examples

Dr. Hesham A. Omran

Integrated Circuits Lab (ICL)
Electronics and Communications Eng. Dept.
Faculty of Engineering
Ain Shams University
 Example #1

5T OTA

This example is mainly based on “IC Mask Design” by C. Saint and J. Saint, 2002
 Circuit Schematic
 Relatively high current ~ 5mA

05: Layout Examples 3

 Pinout and Floorplanning

05: Layout Examples 4

 Multi-finger Transistors

05: Layout Examples 5

 Floorplan (1st Trial)
 What is good/bad about this floorplan?

05: Layout Examples 6

 Layout (1st Trial)
 Plan for NAC (Net Area Check) diodes
early to avoid antenna DRC errors
 What is good/bad about this layout?

05: Layout Examples 7

 Layout (1st Trial)
 VDD connection and N-well contacts
 What is good/bad about this layout?

05: Layout Examples 8

 Layout (1st Trial)
 PMOS load drain connections
 What is good/bad about this layout?

05: Layout Examples 9

 Layout (1st Trial)
 Output connections
 What is good/bad about this layout?

05: Layout Examples 10

 Layout (1st Trial)
 Shared source connection
 What is good/bad about this layout?

05: Layout Examples 11

 Layout (1st Trial)
 Tail current source connection
 What is good/bad about this layout?

05: Layout Examples 12

 Layout (1st Trial)
 Output connections revisited
 What is good/bad about this layout?

05: Layout Examples 13

 Layout (1st Trial)
 Shared source connection revisited
 What is good/bad about this layout?

05: Layout Examples 14

 Layout (1st Trial)
 Ground connection
 What is good/bad about this layout?

05: Layout Examples 15

 Layout (1st Trial)
 Subs contacts
 What is good/bad about this layout?

05: Layout Examples 16

 Layout (1st Trial)
 Complete layout
 What is good/bad about this layout?

05: Layout Examples 17

 Current Flow

05: Layout Examples 18

 Floorplan (2nd Trial)
 Devices rotated to allow better current spreading

05: Layout Examples 19

 Floorplan (2nd Trial)
 Input pair cross-quaded (common-centroid layout)

05: Layout Examples 20

 Layout (2nd Trial)
 Shared source connection
 What is good/bad about this layout?

05: Layout Examples 21

 Layout (2nd Trial)
 Differential input connections (find the mistake)
 What is good/bad about this layout?

05: Layout Examples 22

 Layout (2nd Trial)
 Poly for cross-under and Metal 2 for cross-over
 What is good/bad about this layout?

05: Layout Examples 23

 Layout (2nd Trial)
 NAC diodes added to avoid Antenna DRC errors

05: Layout Examples 24

 Layout (2nd Trial)
 Input pair drain connections in Metal 2
 What is good/bad about this layout?

05: Layout Examples 25

 Layout (2nd Trial)
 Substrate contacts added in the middle

05: Layout Examples 26

 Layout (2nd Trial)
 Tail current source added
– Split into two to avoid
trapping subs contacts
 What is good/bad about this
layout?

05: Layout Examples 27

 Layout (2nd Trial)
 Ground connection
 What is good/bad about this
layout?

05: Layout Examples 28

 Layout (2nd Trial)
 PMOS load
 NAC diodes connected

05: Layout Examples 29

 Layout (2nd Trial)
 Complete layout
 Good, but never perfect
 What is good/bad about this
layout?

05: Layout Examples 30

 ESD Diodes
 Check the manuals or the diode layers to know which terminal is
anode (the terminal connected to p-diffusion is anode)

05: Layout Examples 31

 IO Pad Floorplan and Layout
 Are the two drawings similar?

05: Layout Examples 32

 Input and Output Differential Wiring
 Wires run alongside each other and split symmetrically

05: Layout Examples 33

 Complete Chip Layout

05: Layout Examples 34

 Ground Wiring

05: Layout Examples 35

 Bonding Diagram
 There must a good reference to avoid wrong orientation

05: Layout Examples 36

 Example #2

Two-stage OTA

This example is mainly based on F. Maloberti Lecture Slides “Layout of Analog CMOS IC”
 Circuit Schematic
 Compensation and biasing not shown

05: Layout Examples 38

 Stacked Layout
 Stack multi-finger transistors systematically
– Same width (per finger)
– Length may be different
 Procedure
1. Identify transistors to be placed in the same stack
• Possibly change the sizing of non-critical transistors
2. The overall width of each stack should be similar
• Choose appropriate finger width
3. Place stacks and connect

05: Layout Examples 39

 Multi-finger Options

05: Layout Examples 40

 Multi-transistor Stack

05: Layout Examples 41

 Layout Oriented Design

05: Layout Examples 42

 Stack Design

05: Layout Examples 43

 Interconnections
 Short poly connections are not a problem (usually)
 But better to always use metal for wires carrying current

05: Layout Examples 44

 Analog Cell Floorplanning

05: Layout Examples 45

 Analog Cell Checklist

05: Layout Examples 46

 Example #3

5T OTA (again)

This example is mainly based on S. Palermo Lecture Slides, ECEN474, TAMU

 Circuit Schematic

05: Layout Examples 48

 Complete Layout
 Industrial quality
layout
 Guard rings around
every stack
 N-well all around
 Directional layer
technique
 Two vias per jump
 Inputs run
differentially
 VDD and GND rails
over top and
bottom stacks

05: Layout Examples 49

 Bias Current Mirror
 Interdigitated + two dummies + matched routing
 Good GND connection

05: Layout Examples 50

 Input Pair
 Interdigitated + two dummies + matched routing
 Directional routing + two vias per jump

05: Layout Examples 51

 PMOS Load
 Interdigitated + dummies + matched routing
 Good VDD connection

05: Layout Examples 52

 Thank you!

05: Layout Examples 53