1

EE 560
MOS TRANSISTOR THEORY
PART 1

Kenneth R. Laker, University of Pennsylvania

TWO TERMINAL MOS STRUCTURE

VG (GATE VOLTAGE)
GATE
OXIDE
SiO2
SUBSTRATE
p-type doped Si
(NA = 1015 to 1016 cm-3)

tox

VB (SUBSTRATE VOLTAGE)
EQUILIBRIUM: n p = ni2 (ni 1.45 x 1010 cm-3)
Let SUBSTRATE be uniformy doped @ NA
n i2
and pp0 = NA
np 0
NA
Kenneth R. Laker, University of Pennsylvania

(BULK concentrations)

ENERGY BAND DIAGRAM FOR p - TYPE SUBSTRATE

q = electron affinity of Si

F =

E F Ei
q

Work Function
q S = q + (E c E F )

kT N D
kT n i (N >> n )
F n =
ln
(ND >> ni)
Fp =
ln
A
i
q
ni
q NA
ni = 1.45 x 10-10 cm-3 @ room temp,
k = 1.38 x 10-23 J/oK,
=> kT/q = 26 mV @ room temp
-19
q = 1.6 x 10 C
Kenneth R. Laker, University of Pennsylvania

ENERGY BAND DIAGRAMS FOR

COMPONENTS OF MOS STRUCTURE
Eo
EFm

METAL (Al)
SEMICONDUCTOR (Si)
OXIDE
qM =
qox= 0.95 eV
qS qSi = 4.15 eV
qm = 4.1 eV Ec
Ec
band-gap:
Eg = 8 eV

Ei
EFp
Ev

Ev
S > M => p-type Si
M > S => n-type Si
Kenneth R. Laker, University of Pennsylvania

band-gap: Eg = 1.1 eV
qFp

VG = 0

Equilibrium

Oxide
p-type Si Substrate
VB = 0

Flat-band voltage:
VFB = M - S volts

Equilibrium

Built-in potential:
qS

qM
EFm

qs

s = surface potential
METAL (Al)
Kenneth R. Laker, University of Pennsylvania

Ec

OXIDE

qF

Ei
EFp
Ev

SEMICONDUCTOR (Si)

MOS SYSTEM WITH EXTERNAL BIAS

VG < 0
Accumulation Region
EOX

EOX Oxide

p-type Si Substrate

holes
ACCUMULATED
on the Si surface

VB = 0
VG = 0
Equilibrium
Oxide
p-type Si Substrate
VB = 0
Kenneth R. Laker, University of Pennsylvania

MOS SYSTEM WITH EXTERNAL BIAS

VG > 0 (small)
Depletion Region
EOX

EOX Oxide

p-type Si Substrate

DEPLETION
Region

VB = 0

Ec

EFm

Ei
EFp
Ev

qVG
METAL (Al)

Kenneth R. Laker, University of Pennsylvania

OXIDE

SEMICONDUCTOR (Si)

MOS SYSTEM BIASED IN DEPLETION REGION

VG > 0 (small)
0 x
xd d
x

EOX

EOX Oxide

p-type Si Substrate

DEPLETION
Region

VB = 0
Mobile charge in thin layer
parallel to Si surface
Change in surface potential
to displace dQ

Depletion Region Charge

Kenneth R. Laker, University of Pennsylvania

MOS SYSTEM WITH EXTERNAL BIAS

VG > 0 (large)
Inversion Region
EOX

xdm

EOX Oxide

p-type Si Substrate
Inversion Condition
s = -F
x dm

Electrons
attracted to Si
surface

VB = 0

2 Si | 2F |
= x d s = F =
qN A
EFm

10

Ec

qVG

s = -F

METAL (Al)

OXIDE

Kenneth R. Laker, University of Pennsylvania

Ei
EFp
Ev
SEMICONDUCTOR (Si)

G
D

S S

IDS

G
D S

DS
B

B
B
n-channel enhancement
I DS

B
p-channel enhancement
I DS

IDS

-V
-VTp
Tp

11

VGS
V
GS

VGS
V
GS

+VTn
+V
Tn

n-channel depletion
G
I

I DS

IDS

DS
DS

+V
+V
TpTp

p-channel depletion
VGS
V
GS

B
-V
-VTn

Tn

VGS
V
GS
Kenneth R. Laker, University of Pennsylvania

12

L
oxide
n+

n+
conducting
channel

substrate
or bulk B

depletion layer

N-CHANNEL ENHANCEMENT-TYPE MOSFET

nMOS Layout
polysilicon gate
active area
metal

contact area
Kenneth R. Laker, University of Pennsylvania

S
p+

p+

n+

13

n+

n-well
p -substrate

CUT-OFF REGION

VGS < VTn

DEPLETION REGION
0 < VGS < VTn
B (G2)

VGS

VDS
G

oxide

C
CGC

GC

CBC

nn++

CBC

nn++

depletion region
depletion region
substrate
substrate
or or
bulk
B B
bulk

p
p
Kenneth R. Laker, University of Pennsylvania

VGS > VTn

INVERSION REGION

14

VGS
B (G2 )

C
CGC

VDS
oxide
D

GC

CBC

nn++

nn++

CBC

substrate
substrate
or
orbulk
bulkBB

pp

conducting
channel
depletion region
or
or
inversion
inversionregion
region

Ec

Underneath Gate
VG = VTn
EFm

qVTn
METAL (Al)

Kenneth R. Laker, University of Pennsylvania

2F

F
-F

OXIDE

Ei
EFp
Ev

SEMICONDUCTOR (Si)

MOS Capacitance C = WLC , C = ox

GC
ox
ox
t ox

15

[tox -> TOX in SPICE]

[Cox -> COX in SPICE]

tox = 50 nm, ox = 0.34 pF/cm => Cox = 6.8 x 10-8 F/cm2

W x L = 50 m x 50 m => CGC = 170 fF
Depletion Capacitance C BC = WLC j , C j = Si
xd
[NSUB -> NSUB in SPICE]
NSUB (p - substrate)
kT n i
ln
q NA
NA = 3 x 1017 cm-3, ni = 1.45 x 1010 cm-3 => F = -0.438 V
Fp =

(recall that at room temp or 27oC kT/q = 26 mV)

VSB = 0 V, Si = 1.06 pF/cm, q = 1.6 x 10-19 C, NA, F => xd = 6.22 m
Si, xd => Cj = 0.17 x 10-8 F/cm2
W x L = 50 m x 50 m => CBC = 42.5 fF

Kenneth R. Laker, University of Pennsylvania

Threshold Voltage for MOS Transistors

16

n-channel enhancement
[VT0 -> VT0 in SPICE]
For VSB = 0, the threshold voltage is denoted as VT0 or VT0n,p

QB 0 Q ox
VT 0 = GC 2F

C ox C ox
(+ for nMOS and - for pMOS)

Threshold Voltage factors:

[2 F = PHI in SPICE]

-> Gate conductor material;

-> Gate oxide material &

[N A = NSUB in SPICE]

thickness;
-> Channel doping;
-> Impurities in Si-oxide
interface;
-> Source-bulk voltage Vsb;

metal gate
GC = F(substrate) -M
GC = F(substrate) -F (gate) polysilicon gate

-> Temperature.

Kenneth R. Laker, University of Pennsylvania

[Qox = qNSS in SPICE]

Threshold Voltage for MOS Transistors

n-channel enhancement
For
: the threshold voltage is denoted as VT or VTn,p
QB Q ox

C ox C ox
Q B 0 Q ox Q B Q B0
2F

C ox C ox
C ox
VT0

VT = GC 2F
= GC
where

( = Body-effect coefficient) [ = GAMMA in SPICE]

+

Kenneth R. Laker, University of Pennsylvania

17

Threshold Voltage for MOS Transistors

n-channel -> p-channel
****BE CAREFULL*** WITH SIGNS

F is negative in nMOS, positive in pMOS

QB0, QB are negtive in nMOS, positive in pMOS
is positive in nMOS, negative in pMOS
VSB is negative in nMOS, positive in pMOS
C BC
NOTE:
C GC

Kenneth R. Laker, University of Pennsylvania

18

Threshold Voltage for MOS Transistors

VT0
3V

nMOS

NBULK = NA
N
NABULK

16

14

10

10

pMOS

NBULK = ND

-3V
VT
3V

16

(nMOS 10 /cm 3 )
14

(nMOS 3 x10 /cm 3 )

0

3
16

(pMOS 10 /cm3 )
-3V
Kenneth R. Laker, University of Pennsylvania

V
VBS
SB

19

EXAMPLE 3.2 Calculate the threshold voltage VT0 at VBS = 0, for

a polysilicon gate n-channel MOS transistor with the following
parameters:
substrate doping density NA = 1016 cm-3,
polysilicon doping density ND = 2 x 1020 cm-3,
gate oxide thickness tox = 500 Angstroms,
oxide-interface fixed charge density Nox = 4 x 1010 cm-2.
QB 0 Q ox
VT 0 = GC 2F(sub)

C ox C ox
F(sub), GC: GC = F(sub) F(gate)
F(sub)

1.45x1010
kT n i
=
ln
= 0.026Vln
= 0.35V
16
10

q NA

F( gate)

2 x10 20
kT N D
=
ln
= 0.026 Vln
10 = 0.60 V
1.45x10
q
ni

GC = F(sub) F(gate) = -0.35 V - 0.60 V = -0.95 V

Kenneth R. Laker, University of Pennsylvania

20

EXAMPLE 3-2 CONT.

QB0:

Cox:

Qox:

QB 0 Q ox
VT 0 = GC 2F(sub)

C ox C ox

21

= 2(1.6x10 19 C)(1016 cm 3 )(1.06 x10 12 Fcm 1 ) | 2 x 0.35V|

F = C/V
-8
2
= - 4.87 x 10 C/cm
ox 0.34 x10 12 Fcm 1
8
2
C ox =
=
=
6.8x10
F/cm
t ox
500 x10 8 cm
Q ox = qNox = (1.6x10 19 C)(4 x1010 cm 2 ) = 6.4 x10 9 C/cm 2
8

Q B 0 4.87x10 C/cm
=
= 0.716 V
8
2
C ox
6.8x10 F/cm
2

Q ox 6.4 x10 9 C/cm 2

=
8
2 = 0.094 V
Cox 6.8x10 F/cm

VT 0 = 0.95V (0.70 V) (0.72 V) (0.09V) = 0.38V

Kenneth R. Laker, University of Pennsylvania

EXAMPLE 3.3 Consider the n-channel MOS transistor with the 22

following process parameters:
substrate doping density NA = 1016 cm-3,
polysilicon doping density ND = 2 x 1020 cm-3,
gate oxide thickness tox = 500 Angstroms,
oxide-interface fixed charge density Nox = 4 x 1010 cm-2.
In digital circuit design, the condition VSB = 0 can not always be
quaranteed for all transistors. Plot the threshold voltage VT as a
function of VSB.
- Body-effect coefficient:

F = C/V
2 qN A e Si
2(1.6 x10 19 C)(1016 cm 3 )(1.06 x10 12 Fcm 1 )
=
=
C ox
6.8x108 F/cm 2
5.824 x10 8 C/V 1/ 2 cm 2
1/ 2
=
=
0.85V
6.8x108 C/Vcm 2

Kenneth R. Laker, University of Pennsylvania

23

EXAMPLE 3-3 CONT.

where

1.60
1.40

VT 0 = 0.38V (from EX 3-2)

= 0.85V1 /2
VT(Volts)

1.20
1.00
0.80
0.60
0.40
0.20
-1

Kenneth R. Laker, University of Pennsylvania

VSB(Volts)