Ir2110 PDF

Data Sheet No. PD60147 rev.
IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF
HIGH AND LOW SIDE DRIVER
Features
Floating channel designed for bootstrap operation
Fully operational to +500V or +600V

Tolerant to negative transient voltage
dV/dt immune
Gate drive supply range from 10 to 20V
Undervoltage lockout for both channels
3.3V logic compatible
Separate logic supply range from 3.3V to 20V
Logic and power ground 5V offset
CMOS Schmitt-triggered inputs with pull-down
Cycle by cycle edge-triggered shutdown logic
Matched propagation delay for both channels
Outputs in phase with inputs
Product Summary
VOFFSET (IR2110)
(IR2113)
500V max.
600V max.
IO+/-
2A / 2A
VOUT
10 - 20V
ton/off (typ.)
120 & 94 ns
Delay Matching (IR2110) 10 ns max.

(IR2113) 20ns max.
Packages
Description
The IR2110/IR2113 are high voltage, high speed power MOSFET and
IGBT drivers with independent high and low side referenced output chan16-Lead SOIC
nels. Proprietary HVIC and latch immune CMOS technologies enable
14-Lead PDIP
IR2110S/IR2113S
ruggedized monolithic construction. Logic inputs are compatible with
IR2110/IR2113
standard CMOS or LSTTL output, down to 3.3V logic. The output
drivers feature a high pulse current buffer stage designed for minimum
driver cross-conduction. Propagation delays are matched to simplify use in high frequency applications. The
floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration which
operates up to 500 or 600 volts.
Typical Connection

(Refer to Lead Assignments for correct pin configuration). This/These diagram(s) show electrical
connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout.
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IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions. Additional information is shown in Figures 28 through 35.
Symbol
Definition
Min.
Max.
-0.3
525
Units
VB
High side floating supply voltage (IR2110)
-0.3
625
VS
High side floating supply offset voltage
VB - 25
VB + 0.3
VHO
High side floating output voltage
VS - 0.3
VB + 0.3
VCC
Low side fixed supply voltage
-0.3
25
VLO
Low side output voltage
-0.3
VCC + 0.3
VDD
Logic supply voltage
-0.3
VSS + 25
VSS
Logic supply offset voltage
VCC - 25
VCC + 0.3
VIN
Logic input voltage (HIN, LIN & SD)
VSS - 0.3
VDD + 0.3
(IR2113)
dVs/dt
PD
RTHJA
Allowable offset supply voltage transient (figure 2)
50
Package power dissipation @ TA +25C
(14 lead DIP)
1.6
(16 lead SOIC)
1.25
Thermal resistance, junction to ambient
(14 lead DIP)
75
(16 lead SOIC)
100
150
TJ
Junction temperature
TS
Storage temperature
-55
150
TL
Lead temperature (soldering, 10 seconds)
300
V/ns
W
C/W
Recommended Operating Conditions

The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the
recommended conditions. The VS and VSS offset ratings are tested with all supplies biased at 15V differential. Typical
ratings at other bias conditions are shown in figures 36 and 37.
Symbol
Definition
VB
High side floating supply absolute voltage
VS
High side floating supply offset voltage
Min.
Max.
VS + 10
VS + 20
(IR2110)
Note 1
500
(IR2113)
Note 1
600
VHO
High side floating output voltage
VS
VB
VCC
Low side fixed supply voltage
10
20
VLO
Low side output voltage
VCC
VDD
Logic supply voltage
VSS
Logic supply offset voltage
VIN
TA
Units
VSS + 3
VSS + 20
-5 (Note 2)
Logic input voltage (HIN, LIN & SD)
VSS
VDD
Ambient temperature
-40
125
Note 1: Logic operational for VS of -4 to +500V. Logic state held for VS of -4V to -VBS. (Please refer to the Design Tip
DT97-3 for more details).
Note 2: When VDD < 5V, the minimum VSS offset is limited to -VDD.
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IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF
Dynamic Electrical Characteristics
VBIAS (VCC, VBS, VDD) = 15V, CL = 1000 pF, TA = 25C and VSS = COM unless otherwise specified. The dynamic
electrical characteristics are measured using the test circuit shown in Figure 3.
Symbol
Definition
Figure Min. Typ. Max. Units Test Conditions
ton
Turn-on propagation delay
120
150
VS = 0V
toff
Turn-off propagation delay
94
125
VS = 500V/600V
tsd
Shutdown propagation delay
110
140
tr
Turn-on rise time
10
25
35
tf
Turn-off fall time
11
17
25
10
20
MT
Delay matching, HS & LS

turn-on/off
(IR2110)
(IR2113)
ns
VS = 500V/600V
Static Electrical Characteristics

VBIAS (VCC, VBS, VDD) = 15V, TA = 25C and VSS = COM unless otherwise specified. The VIN, VTH and IIN parameters
are referenced to VSS and are applicable to all three logic input leads: HIN, LIN and SD. The VO and IO parameters are
referenced to COM and are applicable to the respective output leads: HO or LO.
Symbol
Definition
Figure Min. Typ. Max. Units Test Conditions
VIH
Logic 1 input voltage
12
9.5
VIL
Logic 0 input voltage
13
6.0
VOH
High level output voltage, VBIAS - VO
14
1.2
VOL
Low level output voltage, VO
15
0.1
IO = 0A
ILK
Offset supply leakage current
16
50
VB=VS = 500V/600V
IQBS
Quiescent VBS supply current
17
125
230
VIN = 0V or VDD
IQCC
Quiescent VCC supply current
18
180
340
IQDD
Quiescent VDD supply current
19
15
30
VIN = 0V or VDD
IIN+
Logic 1 input bias current
20
20
40
VIN = VDD
IIN-
21
22
7.5
8.6
1.0
9.7
VIN = 0V
23
7.0
8.2
9.4
24
7.4
8.5
9.6
25
7.0
8.2
9.4
IO+
Logic 0 input bias current

VBS supply undervoltage positive going
threshold
VBS supply undervoltage negative going
threshold
VCC supply undervoltage positive going
threshold
VCC supply undervoltage negative going
threshold
Output high short circuit pulsed current
26
2.0
2.5
IO-
Output low short circuit pulsed current
27
2.0
2.5
VBSUV+
VBSUVVCCUV+
VCCUV-
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IO = 0A
VIN = 0V or VDD
VO = 0V, VIN = VDD

PW 10 s
VO = 15V, VIN = 0V
PW 10 s
IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF
Functional Block Diagram

Lead Definitions
Symbol Description
VDD
HIN
SD
LIN
VSS
VB
HO
VS
VCC
LO
COM
Logic supply
Logic input for high side gate driver output (HO), in phase
Logic input for shutdown
Logic input for low side gate driver output (LO), in phase
Logic ground
High side floating supply
High side gate drive output
High side floating supply return
Low side supply
Low side gate drive output
Low side return
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IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF
Lead Assignments
14 Lead PDIP
16 Lead SOIC (Wide Body)
IR2110/IR2113
IR2110S/IR2113S
14 Lead PDIP w/o lead 4
14 Lead PDIP w/o leads 4 & 5
IR2110-1/IR2113-1
IR2110-2/IR2113-2
Part Number
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IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF
HV = 10 to 500V/600V
Vcc =15V
10KF6
10
F
0.1
F
10
5
7
11
12
13
200
H
0.1
F
10KF6
HO
100F
dVS
>50 V/ns
dt
OUTPUT 10KF6
MONITOR
2
IRF820
Figure 1. Input/Output Timing Diagram
Figure 2. Floating Supply Voltage Transient Test Circuit
Vcc =15V
10
F
HIN
SD
LIN
0.1
F
0.1
F
10
5
7
11
12
CL
HO
LO
VB
+
10
15V
F
V
S
(0 to 500V/600V)
!
Figure 3. Switching Time Test Circuit
""

$
#
10
F
CL
13

"
$
#
%
#
%
#
Figure 4. Switching Time Waveform Definition

'*

%
#
$
#

$
#

Figure 5. Shutdown Waveform Definitions

Figure 6. Delay Matching Waveform Definitions
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250
250
200
200
Turn-On Delay Time (ns)
IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF
150
Max.
100
Typ.
50
150
Max.
Typ.
100
50
0
-50
-25
25
50
75
100
125
10
12
14
Temperature (C)
Figure 7A. Turn-On Time vs. Temperature
250
20
250
Max.
200
Typ.
150
Turn-Off Delay Time (ns)
18
Figure 7B. Turn-On Time vs. VCC/VBS Supply Voltage
200
100
50
150
100
Max.
Typ.
50
0
0
10 12 14 16 18 20
-50
-25
25
50
75
100
125
Temperature (C)
VDD Supply Voltage (V)
Figure 8A. Turn-Off Time vs. Temperature
Figure 7C. Turn-On Time vs. VDD Supply Voltage

250
250
200
200
16
VCC/VBS Supply Voltage (V)
Max.
150
Typ.
100
50
Max.
150
100
Typ
50
0
0
10
12
14
16
18
20
Figure 8B. Turn-Off Time vs. VCC/VBS Supply Voltage
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10 12 14 16 18 20
Figure 8C. Turn-Off Time vs. VDD Supply Voltage
250
250
200
200
Max.
Shutdown Delay time (ns)
Shutdown Delay Time (ns)
IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF
150
Max.
100
Typ.
150
Typ.
100
50
50
0
-50
-25
25
50
75
100
125
10
12
Temperature (C)
16
18
20
Figure 9B. Shutdown Time vs. VCC/VBS Supply Voltage
Figure 9A. Shutdown Time vs. Temperature

250
100
200
80
Max .
Turn-On Rise Time (ns)
Shutdown Delay Time (ns)
14
150
100
Typ
50
60
40
M ax.
Typ.
20
0
0
6
8 10 12 14 16
18
20
-50
25
50
75
100
125
Figure 10A. Turn-On Rise Time vs. Temperature

50
80
40
Turn-Off Fall Time (ns)
100
Turn-On Rise Time (ns)
Temperature (C)
Figure 9C. Shutdown Time vs. VDD Supply Voltage
60
Max.
40
Typ.
20
30
Max.
20
Typ.
10
0
10
12
14
16
18
VBIAS Supply Voltage (V)
Figure 10B. Turn-On Rise Time vs. Voltage
-25
20
-50
-25
25
50
75
100
125
Temperature (C)
Figure 11A. Turn-Off Fall Time vs. Temperature
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IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF
50
15.0
12.0
Logic "1" Input Threshold (V)
Turn-Off Fall Time (ns)
40
30
20
Max.
Typ.
10
Max
Min.
9.0
6.0
3.0
0
10
12
14
16
18
0.0
20
-50
-25
25
Figure 11B. Turn-Off Fall Time vs. Voltage
100
125
15.0
12
12.0
Max.
Logic " 1" Input Threshold (V)
75
Figure 12A. Logic 1 Input Threshold vs. Temperature
15
9
6
3
9.0
6.0
Max.
Min.
3.0
0
0
10 12
14
16
18
0.0
20
-50
-25
VDD Logic Supply Voltage (V)
50
75
100
125
Figure 13A. Logic 0 Input Threshold vs. Temperature

5.00
12
4.00
High Level Output Voltage (V)
15
9
Min.
25
Temperature (C)
Figure 12B. Logic 1 Input Threshold vs. Voltage
50
Temperature (C)
3.00
2.00
Max.
1.00
0
0
10 12
14
16
18
20
Figure 13B. Logic 0 Input Threshold vs. Voltage
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0.00
-50
-25
25
50
75
100
125
Temperature (C)
Figure 14A. High Level Output vs. Temperature
5.00
1.00
4.00
0.80
Low Level Output Voltage (V)
High Level Output Voltage (V)
IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF
3.00
2.00
M ax.
1.00
0.60
0.40
0.20
Max.
0.00
0.00
10
12
14
16
18
20
-50
-25
Figure 14B. High Level Output vs. Voltage
50
75
100
125
Figure 15A. Low Level Output vs. Temperature
1.00
500
0.80
400
Offset Supply Leakage Current (A)
Low Level Output Voltage (V)
25
Temperature (C)
0.60
0.40
0.20
300
200
100
M ax.
Max.
0.00
10
12
14
16
18
20
-50
-25
50
75
100
125
Figure 16A. Offset Supply Current vs. Temperature
Figure 15B. Low Level Output vs. Voltage

500
500
400
400
VBS Supply Current (A)
Offset Supply Leakage Current (A)
25
Temperature (C)
300
200
300
Max.
200
Typ.
100
Max.
100
0
0
100
200
300
400
V B Boost Voltage (V)
500
IR2110
600
IR2113
Figure 16B. Offset Supply Current vs. Voltage
10
0
-50
-25
25
50
75
100
125
Temperature (C)
Figure 17A. VBS Supply Current vs. Temperature
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500
625
400
500
VCC Supply Current (A)
VBS Supply Current (A)
IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF
300
200
Max.
375
Max.
250
Typ.
100
125
Typ.
0
10
12
14
16
18
-50
20
-25
100
500
80
VDD Supply Current (A)
VCC Supply Current (A)
625
375
250
Max.
75
100
125
60
40
Max.
20
Typ.
Typ.
0
10
12
14
16
18
20
-50
-25
VCC Fixed Supply Voltage (V)
Figure 18B. VCC Supply Current vs. Voltage
25
50
75
100
125
Temperature (C)
Figure 19A. VDD Supply Current vs. Temperature
60
100
Logic "1" Input Bias Current (A)
50
VDD Supply Current (A)
50
Figure 18A. VCC Supply Current vs. Temperature
Figure 17B. VBS Supply Current vs. Voltage
125
25
Temperature (C)
VBS Floating Supply Voltage (V)
40
30
20
10
80
60
40
Max.
20
Typ.
0
0
10 12 14 16 18 20
Figure 19B. VDD Supply Current vs. VDD Voltage
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0
-50
-25
25
50
75
100
125
Temperature (C)
Figure 20A. Logic 1 Input Current vs. Temperature
11
IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF
Logic 1 Input Bias Current (A)
60
5.00
Logic "0" Input Bias Current (A)
50
40
30
20
10
4.00
3.00
2.00
Max.
1.00
0
0
10 12
14
16
18
0.00
20
-50
-25
Figure 20B. Logic 1 Input Current vs. VDD Voltage
50
75
100
125
Figure 21A. Logic 0 Input Current vs. Temperature
11.0
10.0
VBS Undervoltage Lockout + (V)
Logic 0 Input Bias Current (A)
25
Temperature (C)
3
2
1
Max.
9.0
Typ.
8.0
Min.
7.0
0
0
10 12
14 16
18 20
6.0
-50
VCC Undervoltage Lockout + (V)
VBS Undervoltage Lockout - (V)
50
75
100
125
11.0
10.0
Max.
9.0
Typ.
Min.
10.0
Max.
9.0
Typ.
8.0
Min.
7.0
6.0
6.0
-50
-25
25
50
75
100
125
Temperature (C)
Figure 23. VBS Undervoltage (-) vs. Temperature
12
25
Figure 22. VBS Undervoltage (+) vs. Temperature
11.0
7.0
Temperature (C)
Figure 21B. Logic 0 Input Current vs. VDD Voltage
8.0
-25
-50
-25
25
50
75
100
125
Temperature (C)
Figure 24. VCC Undervoltage (+) vs. Temperature
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IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF
11.0
5.00
4.00
Output Source Current (A)
VCC Undervoltage Lockout - (V)
10.0
Max.
9.0
Typ.
8.0
7.0
Typ.
Min.
2.00
1.00
Min.
0.00
-50
6.0
-50
3.00
-25
25
50
75
100
125
-25
5.00
5.00
4.00
4.00
3.00
2.00
Typ.
0.00
3.00
12
14
16
18
125
Min.
2.00
0.00
-50
20
-25
25
50
75
100
125
Temperature (C)
Figure 26B. Output Source Current vs. Voltage
Figure 27A. Output Sink Current vs. Temperature
5.00
150
4.00
125
Junction Temperature (C)
Output Sink Current (A)
100
Typ.
3.00
2.00
Typ.
1.00
75
1.00
Min.
10
50
Figure 26A. Output Source Current vs. Temperature
Output Sink Current (A)
Output Source Current (A)
Figure 25. VCC Undervoltage (-) vs. Temperature
1.00
25
Temperature (C)
Temperature (C)
Min.
320V
140V
100
75
10V
50
25
0.00
0
10
12
14
16
18
Figure 27B. Output Sink Current vs. Voltage
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20
1E+2
1E+3
1E+4
1E+5
1E+6
Frequency (Hz)
Figure 28. IR2110/IR2113 TJ vs. Frequency

, VCC = 15V
(IRFBC20) RGATE = 33
13
IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF
320V
150
320V
150
125
140V
125
100
75
10V
50
140V
100
10V
75
50
25
25
0
1E+2
1E+3
1E+4
1E+5
0
1E+2
1E+6
1E+3
Frequency (Hz)
Figure 29. IR2110/IT2113 TJ vs. Frequency

, VCC = 15V
140V
50
75
100
25
10V
75
50
25
1E+3
1E+4
1E+5
0
1E+2
1E+6
1E+3
Frequency (Hz)
1E+4
1E+5
1E+6
Frequency (Hz)

, VCC = 15V
(IRFPE50) RGATE = 10
Figure 32. IR2110S/IR2113S TJ vs. Frequency

, VCC = 15V
140V
320V
150
320V 140V
150
125
100
10V
75
50
25
125
140V
125
10V
100
10V
100
75
50
25
1E+3
1E+4
1E+5
1E+6
Frequency (Hz)

, VCC = 15V
14
1E+6
320V
150
125
0
1E+2
1E+5

, VCC = 15V
320V
150
0
1E+2
1E+4
Frequency (Hz)
0
1E+2
1E+3
1E+4
1E+5
1E+6
Frequency (Hz)

, VCC = 15V
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IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF
320V 140V 10V
150
0.0
-2.0
VS Offset Supply Voltage (V)
125
100
75
50
Typ.
-4.0
-6.0
-8.0
25
-10.0
0
1E+2
1E+3
1E+4
1E+5
1E+6
10
12
14
16
18
20
VBS Floating Supply Voltage (V)
Frequency (Hz)

, VCC = 15V
(IRFPE50) RGATE = 10
Figure 36. Maximum VS Negative Offset vs.

VBS Supply Voltage
VSS Logic Supply Offset Voltage (V)
20.0
16.0
12.0
8.0
Typ.
4.0
0.0
10
12
14
16
18
20
VCC Fixed Supply Voltage (V)
Figure 37. Maximum VSS Positive Offset vs.

VCC Supply Voltage
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15
IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF
Case Outlines
14-Lead PDIP
14-Lead PDIP w/o Lead 4

16
01-6010
01-3002 03 (MS-001AC)
01-6010
01-3008 02 (MS-001AC)
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IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF
16 Lead PDIP w/o Leads 4 & 5
16-Lead SOIC (wide body)

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01-6015
01-3010 02
01 6015
01-3014 03 (MS-013AA)
17
IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF
LEADFREE PART MARKING INFORMATION
IRxxxxxx
Part number
YWW?
Date code
Pin 1
Identifier
?
P
MARKING CODE
Lead Free Released
Non-Lead Free
Released
IR logo
?XXXX
Lot Code
(Prod mode - 4 digit SPN code)
Assembly site code
ORDER INFORMATION
Part only available Lead Free
14-Lead
14-Lead
14-Lead
14-Lead
14-Lead
14-Lead
16-Lead
16-Lead
PDIP IR2110 order IR2110PbF

PDIP IR2110-1 order IR2110-1PbF
PDIP IR2113 order IR2113PbF
SOIC IR2110S order IR2110SPbF
SOIC IR2113S order IR2113SPbF
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105
This product has been qualified per industrial level
Data and specifications subject to change without notice 3/23/2005
18
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Data Sheet No. PD60147 rev.

Floating channel designed for bootstrap operation

Fully operational to +500V or +600V

Delay Matching (IR2110) 10 ns max.

High side floating supply voltage (IR2110)

High side floating supply offset voltage

High side floating output voltage

Low side fixed supply voltage

Low side output voltage

Logic supply voltage

Logic supply offset voltage

Logic input voltage (HIN, LIN & SD)

Allowable offset supply voltage transient (figure 2)

Package power dissipation @ TA +25C

(14 lead DIP)

(16 lead SOIC)

Thermal resistance, junction to ambient

(14 lead DIP)

(16 lead SOIC)

Lead temperature (soldering, 10 seconds)

Recommended Operating Conditions

High side floating supply absolute voltage

High side floating supply offset voltage

High side floating output voltage

Low side fixed supply voltage

Low side output voltage

Logic supply voltage

Logic supply offset voltage

Logic input voltage (HIN, LIN & SD)

Figure Min. Typ. Max. Units Test Conditions

Turn-on propagation delay

Turn-off propagation delay

Shutdown propagation delay

Turn-on rise time

Turn-off fall time

Delay matching, HS & LS

Static Electrical Characteristics

Figure Min. Typ. Max. Units Test Conditions

Logic 1 input voltage

Logic 0 input voltage

High level output voltage, VBIAS - VO

Low level output voltage, VO

Offset supply leakage current

Quiescent VBS supply current

Quiescent VCC supply current

Quiescent VDD supply current

Logic 1 input bias current

Logic 0 input bias current

Output low short circuit pulsed current

VO = 0V, VIN = VDD

Functional Block Diagram

16 Lead SOIC (Wide Body)

14 Lead PDIP w/o lead 4

14 Lead PDIP w/o leads 4 & 5

Figure 1. Input/Output Timing Diagram

Figure 2. Floating Supply Voltage Transient Test Circuit

Figure 3. Switching Time Test Circuit

Figure 4. Switching Time Waveform Definition

Figure 6. Delay Matching Waveform Definitions

Turn-On Delay Time (ns)

Figure 7A. Turn-On Time vs. Temperature

Turn-Off Delay Time (ns)

Turn-On Delay Time (ns)