a PRINCIPLES OF CMOS VLSI li DESIGN A Systems Perspec} Neil H. E. Weste ‘ATRT Bell LaboratoriesPRINCIPLES OF IL | CMOS VLSI DESIGN IL | L lal i ee oe OO TlMG. Vatley, Sponsoring Editor s Hugh Ceawiord, Manufacturing Supervisor Maty Critendan, Project Supervisor FRichatd Hannus, Cover Designer i ‘oureen Langer. Text Designee L lydia P. Siegel, Production Editor “This book is inthe Addison Wesley VEST Systems Seis To Avril, Melissa, and Tamara Typ Conway and Ghats Seitz, Consling Etre and Deidre, Michelle, and Kylie ‘trary of Congress Cataloging in Pblieaton Dat Wat, Nei cli of CMOS VES desis ‘logan: p Include inet Tatra Sects Very ae scale ntation i _—batietind consucion. "2 Meloxdesemionducton, Gompleoenny. L Exhraphle, Kame, HT SP'Tide Panels of CMOS. VIS. doi ‘So o-2o1-ogaat-s Reprned with comets Jae, 1988 Copyrieh © 1085 by ATAT Bell abostaies, ncrporated, Sou Ean Sabrepan| [ligt ese No pat ofthis publication may be coprocessor Ce ee Pnamtd to any form ot By any ens, ere. aaa eascopying ecarding or she, without the par wren ae Pe eblsor Fated in he United States of Ae Filabe smeliancusl in Cams‘The VLSI Systems Series Lynn Conway Consulting Charles Seitz VLSI Signal Processing ‘A Bit-Serial Approach ‘The Design and Analysis of VLSI Circuits ‘The VLSI Designer's Library Structured VLSI Design Principles of CMOS VLSI Design: ‘A Systems Perspective Editors Peter Denver and David Renshaw. 1985 Lance A. Glasser and Daniel W. Dobberpubl 1985 John Newkirk and Robert Mathews, 1983, Ccharles Seitz, 1985 Neil Weste and Kamran Eshroghian, 1985pene perros FOREWORD ‘The subject of VLSI systems spans a broad range of disciplines, Including semiconductor devices and processing, integrated electronic, ‘Crculls, digital logic. design disciplines and tools fr resting complex. Systems, and the architecture, algorithms, and applications of complete VLSI systems. The Addison-Wesley VLSI Systems Series is being organized as a set of textbooks and research references that present the best current work across this exciting and diverse field, with teach book providing for its subject a perspective tht tes it to related disciplines. Principles of CMOS VLSI Design: A Systems Perspective by Neil ‘Weste and Kamran Eshraghian provides both students and practicing System designers with a solid introduction to custom VLSI design in the complementary MOS (CMOS) technologies. The past seve:al years bave seen a rapid shift inthe technology of choice fo high- Complexity digital microelectronics from nMOS to CMOS. This shift fas occurred because CMOS offers high performance at low power, fand scales extremely well to small feature size. In spite of its ad~ vantages, and is extensive use in semi-custom gate-rrays and custom Commodity parts, CMOS has yet to be exploited to is full potential by the VLSI system design community. CMOS design and layout presents soveral intimidating completes that Weste and Eshraghian fave effectively put to ret by the way in which they have adopted hierarchical, stuctured design methods and layout abstrection to ‘CMOS technology. ‘The presentation ofa coherent design style together vith manyx FOREWORD practical design examples allows this book to be used either as @ | text or as a reference. Those readers already skilled in VLSI design re bs median wl fd that tok ed amos tnt PREFACE Int aM med bout CMOS cngn an many stig pnts TEGuGS USF Sem design, The tok cies he sins re Gitrencs unum be HOS poe vata enlace aes ge Te symbol yout spac devoped inthe aoe ee dort sep bck fon he real Souls wh ean We lew tat dostgnos. serchary. and Sn eer al nis oktober tornce Se ny explore th ones Of MOS VES ei, Lynn Conway’ ‘Ann Atbor, Michigan Chuck Seitz Pasadena, California Recently there has been an interest in expanding the set of people engaged in the design and specification of integrated circuits. This hhas occurred in two main thrusts. The text Introduction to VLSI Systems by Mead end Conway advocated what is now commonly called “structured hierarchical design,” accompanied by a reduced fad simplified geometric and electrical rule set. That text was based tipon a nMOS depletion load technology. Design responsibility txtonded down to layout details. An alternative movement. largely Supported by industry (as opposed to academia), has placed custom {)1C. design capability atthe logic level atthe disposal of many HE, system designers. This has largely been in the form of CMOS gate EE arrays and, more recently, CMOS standard cells. ‘This text has been written to assist those who wish to go beyond the standard cell and gate array approaches and realize fully custom ‘Sesigns that Completely utilize the potential ofthe silicon surface, "The material in this book is divided into several parts. The fist past deals with CMOS circuit design and CMOS processing tech- ology. The second part deals with design issues and sub-system design, The last partis devoted toa rich set of examples of custom- designed CMOS circuits from which the reader may draw on the experience of other VLSI system designers, “A centalized theme in the book is the adoption of a symbolic layout approach to CMOS design. Most layout examples are given in this form with some mask level layouts for atypical bulk CMOSig warnce — psec Coed process, However, the symbolic designs are provided where necassary to provide layouts with some lifetime. "This text originated with a course that Weste taught atthe Uni- ‘versity of North Carolina (Chapel Hill) and Duke University im the {pring of 1982. An expanded course was taught by Eshraghian at Duke in the spring of 1983 and at the University of Adelaide in 1983/84. Dr. Kishor Trivedi taught the Duke course in the spring of 1964. A similar course was also taught at ATAT Bell Labs (Holmdel) in 1983, "The authors would like to acknowledge the support and help of many people during the preparation of the text. Bryan Ackland provided outstanding contributions to the outcome of the text, in- Ehuding key rewrites to Chapters 2 and 4. Kishor Trivedi was kind fenough to debug a draft form of the text in his CMOS class. Steven HF. Law, Gershon Kedem, Dave Ditzel, Don MacLennan, Maleolin Haskard, Alan Mariage, Marcus Patridge, Jim Cherry. Richard Lyon, ‘Mike Maul, Randy Katz, Jonathan Allan, and colleagues inthe Com- puter Systems Research Laboratory of AT&T Bell Labs provided much needed comments and criticisms of the fist draft. Jay Borris provided a great resource in the assembly of the fist drat. The Eupport of RL. Andersson, S. C. Knauer, j. H. O'Neill, A. Huang, Joba W. Poulton, Henry Fuchs, Alen Paeth, R. H. Krambeck, and N-S. Vesanthavada is appreciated for their contributions to Chapter 9, Alex Dickinson, Charles Poirier, and Martin Levy provided support inthe later stages of the book. Furthermore the authors would like to acknowledge AT&T Bell Labs menagement, especially Bll Ninke, and staff for providing the ‘experience, the atmosphere, and the resources without which this book would riever have been completed. Additionally, The Mi- crooloctronics Cenze of North Carolina and the associated universities, particularly Duke and UNC (Chapel Hill), provided the ecademic fnvironment where work on this text was started. The University of Adelaide and Symbolics Inc. provided ongoing support for the ‘work on the book. Cambridge, Massachusetts NW. ‘Adelaide, South Australia KE ABOUT THE AUTHORS Neil Weste is the Director of VLSI Systems at Symbolies Inc. in addition to holding a postion as an Adjunct Professor in Computer Seionce at Duke University. Prior to joining Symbolics Inc. Weste Spent six years at AT&T Bell Labs in Holmdel, New Jersey. He Wworked one year at the Microelectronics Center of North Caroline vwith teaching duties at Duke University and the University of North Carolina (Chapel Hill, Weste received his BS. B.E., and Ph.D. from the University of Adelaide, South Australia ‘Kamran Eshroghian isa senior lecturer in Electrical Engineering ot the University of Adelaide, South Australia. In addition to CMOS ‘VLSI Design, his research interests include Signal Processing. Esh- Tghian received his B.S., BE, and Ph.D. from the University of ‘Adelaide, South Australia, Eshraghian spent one year atthe Micro ‘lectzonics Center of North Carolina and Duke University. Prior to teaching, Eshraghian was with Philips Lid. as an IC designe.CONTENTS oar 1 INTRODUCTION TO CMOS TECHNOLOGY INTRODUCTION TO CMOS CIRCUITS 1.4 Introduction 1.2 MOS transistors 1.3 MOS transistor switches 1a CMOS logic La The inverter 14.2 Combinational logic 143. The NAND gate 1a The NOR 143 Compound gates 148 Multiplexers 147 Memory 1.5. Allernate circult representations 1.5.1 Behavioral representation 1152 Structural representation 15. _ Physical represent 1.6 CMOS-nMOS comparison 17 Summary 18 Exercises2 ‘CONTENTS: 2 MOS TRANSISTOR THEORY 22 23 Invoduetion 21.1 nMOS enhancement transistor 21.2 nMOS transistor 2.13 Threshold voltage 2.14 Threshold voltage adjustment 21.3 Body effect MOS device design equations 22:1 Vel characteristics ‘The complementary CMOS invert characteristics 2.3.1 Influence of 4/8, ratio on transfer characteristic 232 Noise margin Alternate CMOS inverters ‘Transmission gate—DC cha Latch-up Exercises Dc ‘CMOS PROCESSING TECHNOLOGY a1 32 33 34 Silicon semiconductor technology: an overview 3.4.1 Wafer processing 34.2 Oxidation 3.1.3 Selective diffusion 3.1.4 The silicon gate process CMOS technologies 3.21 The p-well process 3.22 The n-well process 3.2.3 The twin tub process 3.2 Silicon on insulator 32.5 CMOS process enhancements Layout design rules 331 Layer representations 33.2 Lambda based p-well rules 33.3 Lambda based SOI rules 23.4 Double metal design rules 33.5. Design rules—summary Process parameterization 341 Abstract layers 34.2 Spacing rules 34.3 Construction rules 3 2 n a a 8 38 39 2 2 Summary Exercises CIRCUIT CHARACTERIZATION AND PERFORMANCE ESTIMATION 4a 42 43 44 45 46 48 49 4.0 an 412 5 Introduction Resistance estimation 42.1 Resistance of non-rectangular regions Capacitance estimation 43:1 MOS capacitor characteristics 43.2 MOS device capacitances 43.3 Diffusion capacitance 43.4 Routing capacttance 335 Distributed RC effects $36 Capacitance design guide 33.7 Wire length design guide Switching characteristics S41 Fall time determination 442. Rise time 442 Delay time 25 CMOS gate transistor sizing 45.1 Similar stage loads 45.2 Switching performance of the Pseudo ‘AMOS inverter 45.3 Cascaded stage loads Determination of conductor size Power consumption 47.1 Static dissipation 4.7.2 Dynamic dissipation (Charge sharing Scaling of MOS transistor dimensions 4.91 Scaling principles 4.9.2 Interconnect layer scaling Yield Summary Exercises CMOS CIRCUIT AND LOGIC DESIGN 8. 52 Introduction CMOS logic structures 5.2.1 CMOS complementary logic 19 v0 120 2 m2 wa 15 129 at 131 nb 1a? 0 M1 ut rr 15 7 19 150 150 154 136 157 157 159 160 160 160 CONTENTS xviiwill CONTENTS: 33 55 52.2 Peeudo-nMOS logic 5.2.3 Dynamic CMOS logic 5.2.4 Clocked CMOS logic (C*MOS) 523 CMOS domino logic 5.2.6 Cascade voltage switch logic (CVSL) 52.7 Madilied domino logic 5.2.8 Pass transistor logic Electrical and physical design of logic gates 53.1 The invertor 5.3.2 NAND and NOR gates 5.3.3 Series and parallel transistor connection 5.34 Body effect 5.33 Souree-drain capecitance 5.2.6 Charge redistribution (ch: 5.3.7 Logie style comparison 5.3.8 Physical layout of logic gates 5.3.9 CMOS standard coll design 5.3.10 General logic gate layout guidelines 5.2.11, Gate optimization 53.12 Transmission gate layout considerations 5.3.13 2-input multiplexer Clocking strategies Sat Pseudo 2-phase clocking 542 Pseudo 2-phase memory structures 5.4.3 Preudo 2-phase logic structures 544 2phase clocking 548 2phase memory structures 54.6 2-phase logic structures 54.7 4-phase clocking 5.48 4-phase memory structures 54.9 4-phase logic structures 54.10 Pseudo 4-phace clocking 54.11 Recommended approaches Input-output (LO) structures 551 Overall organization 55.2 Vop and Ves pods 55.3 Output pads 55.4 Input pads 55.5 Tristate pads 55.6 Bidirectional pads Summary Exercises re sharing) 162 163, 168, 168 159 1 m 175 vs 179 20 184 185 188, 88 189 193 195 196 201 203 203 203 208, an au 22 ns zat m2 23 2a 24 224 225 225 227 229 230 230 230 PART. SYSTEMS DESIGN AND DESIGN METHODS 6 STRUCTURED DESIGN AND TESTING 6.1 Introduction 6.2 Design styles 62.1 Introduction 6.2.2 Structured design strategies 62.3 Hand-crafted mask layout 6.24 Gate aray design 6.2.5 Standard coll design 6.2.6 Symbolic layout methods 6.3 Automated synthesis 63.1. Procedural module definition 6.3.2 Silicon compilers 6.4 The custom design tool box 64.1 Introduction 64.2 Chreuit level simulation 643 Timing simulation 6.4.4 Logic level simulation 64.5 Switch level simulation 64.8 Timing verifies 64.7 Schematic editors 64.8 Netlist comparison 64.9 Layout editors 64.10 Design rule checkers 8.4.12. Cireult extractors 65 Testing 65.1 Intoduction 65.2 Fault models 65.3 Design for testability 65.4 Ad hoc testing 6.5.5 Structured design for testability 6.5.6 Selftest and builtin test 6.5.7 Layout for improved testability 6.5.8 Summery—testing Summary Exercises 6 6 ‘SYMBOLIC LAYOUT SYSTEMS 7. Introduction 72 Coarse grid symbolic layout 233 25 236 236 236 238 aa aan a7 249 237 287 238 258 259 259 259 260 262 263 268 266 268 268 269 269 an a are CONTENTS aeGate-matrix layout Sticks layout Virtual grid symbolic layout 75.1 Language 752 Devices 733 Contacts 734 Wires 733° Pins 736 Instances 7.57 _ Representations 7.6 Symbolic design tools 7.6.1 Overall organization 762 762 Software organization 7.8.4 Chip design process 763 Cell design process 7.66 Interactive graphics editor 7.67 Circuit interpreter 7.68 Virtual grid compaction 7.69. Graph-based compaction 7.6.10 Mask generation 7.6.11 Call verification 7.6.12 Module assembly 7.7 Future directions 77.1 Flexicells 77.2. Expert systems 7.8 Summary 79 Exercises 8 ‘CMOS SUBSYSTEM DESIGN 8.1 Introduction 82 Adders and related functions 8.2.1 Combinational adder 82.2 Dynamic combinational adder 82.3 Transmission gate adder 824 Cary lookaboad adders 82.5 Manchester carry adder 82.6 Binary lookahead carry adder 82.7 Cary select adder 82.8 Parity generators 82.9 Comparators 83 Binary counters 23.1 Asynchronous counters 83.2 Synchronous counters 309 0 310 an au 317 320 322 225 at a2 33 335 335, 335 84 Multipliers 84.1 Serial multiplier 84.2 Serial'parallel multipliers 442 Parallel multiplier 844 Other multiplier structures 85 Random access memory 85.1. Static RAM calls 85.2 CMOS static RAM cell design 85.3 Dynamic RAM cells, 54 ROM cells 83.5 Row decoders 85.8 Column decodors 85.7 Readiwrite circuitry 8.5.8 Last in, st out stack 8.6 Data paths 86.1 Registers 86.2 Arithmetic logic units 8.6.3 Barrel shifters 8.7 Programmable logic arrays 87.1 Introduction 87.2. Electrical and physical design of CMOS PLAS 87.9 Pseudo-mMOS NOR gate 874 Dynamic CMOS~2-phase clocking 875 Dynamic CMOS—+-phase 876 Detailed PLA layout 8.7.7 PLA else clause implementation 87.8 PLA design points 7.9 Programmable path logic (PPLs) 8.8 Exercises var D (CMOS SYSTEM CASE STUDIES 9 SYSTEM CASE STUDIES 9.1 Introduction 9.2 Dynamic time warp processor 9.2.1 Introduction 92.2 The problem 9.2.3 The algorithm 924 A functional overview 92.5 Detailed functional specification 92.6 Structural floor plan a9 340 340 a8 381 383 am 364 384 305 386 388 303 ‘300 ‘CONTENTS:as 94 28 97 INDEX 9.2.7 Physical design 92.8 Febrication Real time video moment generator chip 9.3.1 Introduction 9.3.2 Review: video formatting 93.3 Chip architecture 934 Floor planning 935 Component cell examples 9.38 Chip assembly 9.3.7 Optimization 9.3.8 Design testing 9.3.9 Physical chip testing 93.10 Conclusions Self routing switching network 94.1 Introduction 9.42 Partitioning the sorting and expander networks 943° Chip layout 8.44 Chip circuit simulation 945 Chip testing to isolate functions 946 Summary Pixel-planes graphic engine 951 Introduction 952. Raster-sean graphic fundamentals 95.3 Pixel-planes system overview 954 Chip electrical design 95.5 Chip organization and layout 9.36 Clock distribution Hierarchical layout and design of a single chip 32-bit CPU 9.6.1 Introduction 962 Design methodology 963 Technology updatability and layout verification 964 Results 965 Conclusion Conclusion APPENDIX COMPUTING NOISE MARGINS FOR CMOS AND NMOS INVERTERS REFERENCES BIBLIOGRAPHY 505 sit set 525 PRINCIPLES OF CMOS VLSI DESIGN| | INTRODUCTION PART 1 TO CMOS | TECHNOLOGY This Part orients the system designer toward CMOS technology. | Chapter 1 gives a brief overview of CMOS circuit design. Chapter 2 deals with basic MOS transistor theory. Chapter 3 summarizes some CMOS processing technologies and also introduces typical ‘geometric design rules, Chapter 4 introduces techniques to estimate petformance of CMOS circuits. Chapter 5 covers at some depth the Yerious alternatives available fo the CMOS circuit designe.Shei INTRODUCTION TO CMOS CIRCUITSGHAPTER 1 INTRODUCTION TO GMOS CIRCUITS ‘Over the past few yeer, Complementary Metal Oxide silicon (CMOS for short) technology hes played an increasingly important role in the world integrated circult industry. Not that CMOS technology is thet new. In fact the basic principle behind the MOS fold effect thanstator was proposed by [Lilienfeld as early a 1925 and a similar ‘tructure closely resembling a modern MOS transistor was proposed. by 0. Hell in 1935, Material problems foiled these early attempts, Experiments with carly feld effect transistors led to the invention Ei the bipolar transistor. The success of the latter device led t0 2 dlecline in interest in the MOS transistor. MOS devices remained se oddity until the invention of the silicon planar process in the arly 1960s. Material end quality control problems dogged the in- duction of the MOS device into commercial uses until around Yoo? [Cobb79}. Even then, single polarity p-ype transistors oF n- transistors wete favored. The use of both polarity devices on the ‘rane substrate was initially weed for very low power applications snch as watches, As the processing technology required inthe fab Fication of CMOS circuits was more complex than that for single ‘olarty transistors, CMOS was sparingly applied to general system Resigns. As nMOS production processes became more complicated, the additional complexity of the basic CMOS process decreased in Importance. Additionally, system designers were being faced with vg large chip sizes and power consumptions. For thls, and other Teosons that will become evident during the course of this book. GaOS technology has increased in its level of importance os a VLST technology. "The purpose ofthis book i to provide the designers of hardware or software systems with an understanding of CMOS technology, Circuit design, layout, and systom design sufficient to feel confident saith the technology. The text deals with the technology down to the layout level of detail, thereby providing a bridge from a circut toa form that may be processed. At the present time, relatively ‘Sutomated design approaches can take a logic schematic end au omatically convert these toa chip layout. However, these approaches Hovnot really capitalize on the fundamental objects available in an JG tansisiors, Hopefully, with texts such 2s this, software sys toms may be constructed that capture an expert's knowledge so that Mbitrarily structured and architected silicon systems of enormous Complexity can be built rapidly and eccurately. ‘Fhe book is divided into three main sections. Chapters 1-5 ossentilly provide @ circuit view of CMOS IC design. In the frst CRapter, a rather idealized view of CMOS technology will be taken Ghat some basic forms of logic and memory willbe introduced. This Is aimed at providing an unencumbered picture of the technology ‘without delving into unnecessary detail. Chapter 2 deals ata greater depth with the operation of the MOS transistor and the DC operation of the CMOS inverter and a fer other basic circuits of interest. The phenomenon commonly known as latch-up is also discussed. Some background to CMOS processing technology is presented in Chapter 3, The besic processes in current use are described along with some {Interesting process enhancements. Some representative design rules are also presented in this chapter, Chapter 4 treats the important Subject of performance estimation and characterization of circuit ‘operation. This cavers speed and power dissipation. A section su ‘marizing some frst order scaling effets is also included. A summary Of basic CMOS circuit forms is provided in Chapter 5. Various locking schemes are discussed with the emphasis being placed on ‘Greuit design and layout, The second section comprises Chapters 5-8. These chapters present a sub-system view of CMOS design. Chapter 6 focusses on a range of current design methods, identifying ‘where appropriate the factors {n common with CMOS. A section tn testing is also included. Symbolic layout techniques are discussed in Chapter 7, with particular emphasis placed on a design system implemented by one of the authors. Tis is included to give an ides ff some of the components required in a custom CMOS design System. Chapter 8 is'a tather hefty chapter on sub-system design, ‘bing the cieuits discussed in Chapter 5. Discussion is commenced ‘with a variety of adder designs. RAMs, ROMs, and PLAS are then covered. The final section is contained in Chapter 9, It consists of five examples of CMOS ICs of varying complexity. The purpose of these chapters isto illustrate the architectural decisions that lead to full custom chip design. Where appropriate the specific rela. tionships to CMOS technology are noted 1,2 MOS transistors ‘An MOS (Meta Oxide Sicon structure is ceted by superimposing Several layers of condvctng. sulting nd vanitor forming m tel, After a series of processing sop, a typialstuctre might Connie of levels called illusion, polyelicon, and metal That a Spero by Insulting layers, CMOS technology provides two types ‘Fount ao called vies in ths txt} an ype Wensitor {eMOS) and & piype transistor (pMOS). These ate foeistd In Seon ty using other negavely doped son th ich in elctrons {negatively charged) ot postive doped lion that sich in hoes {ise dul of elecons and postvely charged), Typical physical 42 MOS TRANSISTORS 5@ CHAPTER T INTRODUCTION TO GMOS CIRCUITS: 1.3 MOS TRANSISTOR SWITCHES 7 1.3 MOS transistor switches ‘The gate controls the passage of current between the drain and Source. Simplifying this to the extzome allows the MOS transisiors {a be viewed as simple on/off switches. Inthe following discussion. wwe will assume that aI" is @ high voltage that is normally set to 5 5 volts and called POWER or Vio. The symbol '0" will be assumed tobe low voltage that is normally set to 0 volts and called GROUND or Vs. The strength ofthe 1" and: signals can vary, The “strength” fof a signal is measured by its ability to sink or souree current. In 5) {general te stronger a signal, the more current it an source or sink. Where the tern output and input are used. the output will be the source of stronger t's and ‘0's than the input. The potser supplios (Woo und Vas} are the source of the stoongost “T's and "0s “The nMOS switch (N-SWITCH) is shown in Fig. 12a. The sche: matic representation is shown along with a switch representation ‘The gate has been labeled with signals, the drain a, and the source b, In an N-SWITGH, the switch is closed or ‘ON’ ifthe drain and S source ate connected. This occurs when there is 2°1' on the GATE, ‘The switch is open or OFF’ Ifthe drain and source are disconnected. ‘AD on the GATE ensures this condition. These conditions are ‘summarized in Fig. 1.25. An N-SWITCH is almost a petfect switch ‘when a0" is to be passed from an output to an input (say a to bl erm crogrsmeo. FIGURE 1.1. MOS transistor physleat structures seuctues forthe wo types of MOS transtorse shown a i 1 Farth rns be stuctur consi of ection of PVE Tee ee cing tr difsed srw of asbpe icon. The wet an eons s copped witha sandwich coasting af cae neds conductog secre called he GATE Simla ran oe ie stele const oa seton of YP tee easing two pope difused ren, The panatr eso econ a clecuode. Frthe purpose of invoduton, wel ase aa eaasserre hav tr adloelconnucons, which ade raat le DRAIN andthe SOURCE thee ing formed by te (hace fe pave) ifsed gions. The pt «contol {Pt oats fom of lara cent bated ho drain SE ce Int ho Gain aaa mayb seed wo ra eer ale They obj egulen and the eame cena donende om ibe dbseton of caren Ho. For ao We ‘ill regard them a5 interchangeable FIGURE 12, MOS trancistors viewed as switchesi L FIGURE 1.2. A comple: 1 tary swt CHAPTER 1 WTRODUGTION TO CNOS CIRCUS toy oT However, the N-SWITCH isan imperfect switch when passing a1! In doing this the voltage level s reduced lie (Ths explained in Section 2-5.) These cases ara shown in Fig. 1.2c. The pMOS Switch (P-SWITGH) is shown in Fig. 12d. [thas different properties thon the N-SWITCH, The P-SWITCH is closed or ‘ON’ when there {s.a"0 on the gate. The switch is open or ‘OFF’ when there is @ ‘on the gate. Fig. 1.2e depicts these conditions. Notice that the PMOS and aMOS switches are ON and OFF for complementary ‘Values ofthe gate signal. We denote this difference for 9 P-SWITCH ty including the inversion bubble in the notation. A P-SWTTGH is llinost pertect for passing “I” signals but is an_imperfect switch ‘ohm pessing ‘” signals. This is illustrated in Fig. 12 ‘By combining an NSWITCH snd a P-SWITCH in parallel (Fig, 1.3), we obtain a switch in which ae passed io an acceptable ‘erm this @ complemeniary switch or C- SwwFRCH ta creat where only a0" or” has to be assed the Sppropriatesub-switch [N or 2) may be deleted, reverting to SWITCH! or N-SWITCH. Note that a double cll logi is implied land its complement are routed to all al is aplied to the 1.4 CMOS logic 1.4.1 The inverter ‘Table 1.1 outlines the necessary stats to implement a logical inverter, If we examine this table we find thet when there 1s ¢‘O' on the eae veer Le ourr 4 FIGURE 1.4. Construction of a CMOS inverter input there isa 1’ a the output. Tis suggests a P-SWITGH connocted from aI" soutce (Voo] to the output as shown in Fig. 14a, When there is 4 t"on the input a0" has to be connected to the output ‘This suggests the addition of an N-SWITCH between the outpot and 270" source (Va). The completed circut is shown in Fig. 1b, Note that as the lower switch anly has to pass 20" [the Vsg source of ‘o's is stronger than the output of the inverter), only an N-SWITCH is needed. By similar reasoning, the upper switch, which only has to pass a1", needs only a P-SWITCH, The transistor schematic and ‘schematic icon forms for this are shown in Fig. 14. In general. 3 fully complementary CMOS gate always bas an N-SWITCH (pull own) array to com i is) and a P'SWITCH {pull-up) artay to connect the output to“ (Voo} a 1.4.2 Combinational logic If two N-SWITCHES are placed in series, as shown in Fig. 1.53 on pege 10, then the composite switch constructed by this action is Elosed (or ON) if both switches are closed (or ON) as illustrated in Fig, 15e This yields an “AND” function. The corresponding structure for P-switches is shown in Fig. 1.5b. The composite switch is closed if both inputs are set 100: ‘When two N-SWITCHES are placed in parallel (Fig. 1.9), the composite switch is closed if either switch is closed (ether input is a1). Thus an ‘OR’ function is creatod. The switch shown in Fig. 15d is composed of two P-SWITCHES placed in parallel. in tontrst to the previous case, if either input is a ‘0° the switch is closed, By using combinations of these constructions, CMOS combi- national gotes may be constructed. 14 (eMOs Losie 90 GHAPTER 1 INTRODUCTION TO CMOS CIRCUITS: Jd Hid gi 4 zg 4 ) adidi 4h $04 ae bag FIGURE 1.5. Series and parallel CMOS switch combinations pe ON bm ol J “ 1.4.3. The NAND gate Fig. 1.6 outlines the construction of a 2-input NAND gate using the constructions introduced in Fig. 15a and Fig, 1.5d. These structures are derived by examining the Karnaugh map in Fig. 1.62. The ‘0! term (pull-down to 0) dictates an AND structure (A.B). Grouping the '1’s together reeults in a structure to perform 4 + B. This is realized by the parellel p OR structure. The complemented signals 14 CMostosic 11 FIGURE 15. A CMOS NAND gateCHAPTER 1 INTRODUCTION TO CMOS CIRCUITS: TABLE 1.2._NAND gate truth table DonpuT BINPUT ANGSWITCH BNSWICH APSWICH BPSWITCN OUTPUT |v 7 ‘OFF ‘OFF ON ON 7 bog 1 OFF oN on OFF 1 1 ° oN. ore oN OFF 1 L 1 Ox. ON. ore OFF ° ae obtained automaticaly by the operation ofthe p-levice, The p- structure is the logical dual ofthe nstructure. This property is used. {in most complementary CMOS logic gates but not aecessarly Ta ‘ynamic gates or static gates that dissipate sialic powet). The roth table and SWITCH Hates ate shown tn Table TZ. BY inspection, ‘one may see that this implements the NAND function Some further points may be noted fom this example. Firstly ote that forall inputs there is always a path from the “1 or “0 (oo oF Vgy supplies) to the output and the full supply volages appear at the output, The lier feature Teads to a “fully restored" ogi family. This simplifies the circuit design considerably. In com parison to nMOS, where the load and driver transistors have to be {atioed, the ransistrs in the CMOS gate do-not have tobe ratioed for ti pte Ts function corey, Secondly, there iz sever «path irom the tte the" supplies fr any combination of iat sah ir contest io aMOS) Ase wil eam in ssequent chaps is iS the bess Toro Taw static power dissipation InCMOS. Tecreuit Sh ogi schomatis fora Tiaput NAND gate as shown in Fig. {oben Fig 16 Note that ager input NAND gates ae constructed By placing one N-SWTTCH in series onthe n side and one PSWITCH, in paralel for cach addtional input tothe gate 1.44 The NOR gate |A Zinput NOR gate is shown in Fig. 1.72. It is composed from Sections introduced in Fig. 1.5b and Fig. 15. according to the Kamaugh map. Note that the N and P switch combinations are the dual or complement of that for the NAND gate. The truth table is shown in Table 1.. This implements 8 logical NOR operation. The Corresponding schematics are shown in Fig. 1.7b and Fig. 1.7c. In Comparison to the NAND gate, extra inputs are accommodated in the NOR structure by adding N-SWITCHES in parallel and P- [SWITCHES in series with the corresponding switch structures, FIGURE 1.7. A CMOS NOR gate va CMOS LoGic 374 CHAPTER 1 INTRODUCTION TO CMOS CIRCUITS 7 14 CMOS LOGIC 18 | yaBLe 13. NOR gate truth table OT AMaMnGr ENGNG AROMAS PSM OORT , : - ee am : ” 5 q o 1 OFF ON ‘ON OFF o : . ° oro 4 Poe ¥ . 1.45 Compound gates . AG aga es erica a oe perallel switch structures. For example the derivation of the switch Eonnection diagram for the function F = ((A.B) + (C.D) is shown in Fig. 1.8, The decomposition of this function and generation of the diagram may be approached as follows. For the n-sde take the ‘ninverted expression ((4.8) + (C.D,)- The AND expressions (A.B) “ land (C.D) may be implemented by sories connections of switches . ae. fs shown in Fig. 1.8a, Now taking these as subentities and ORing ° a the result requies the parallel connection of these two structures. . “Tis is shown in Fig. 1-0. For the pside we invert the expression used for the n-expansion yielding (A + B).(C + D).This suggests two OR structures, which are subsequently connected in series. This prowression ls evident in Fig. 1.8. The final step requires connecting tne end of the p-stucture to“ (Veo) and the otherto the output One side of the nestrctre Is connected to‘0' (Vas and the other — oe to the output in common withthe pstructre, This vields the Anal i Connection diagram (Fig. 18d). The schematic con's shown in Fig. ‘ile, which shows that this gato may be used ina 2-nput mulkiplexer, ° . VODpee Mita cise bei ee ie ao nthe Karnaugh map for @ second function F = ((A + B =] , Dj is shown in Fig. 180 on page 26. The subsunction (A + B + his implemented a three parallel switches. This suucture is then placed Vy sees with a switch with D on the input. The funtion (D+ ABC) This requires three switches in seies connected in tur in parallel witha switch with D on the input. The completed fate is shown in Fig. 1.9 on page 16. In general, CMOS gates ma : felimplemanted by onalyaig the selva rssh ap for both i Togic structures and subsequently generating the requ “4 parallel combinations of Wansisiors. al Romeo 1.4.6 Multiplexers Complementary switches may be used to select between a number of inputs, thus forming a multiplexer function. Fig. 1.10a on poge z $7 shows a connection diagram for a 2-input multiplexer. As the FIGURE 1.8, Construction of function F = (AB) CDH7 CHAPTER 1 INTRODUCTION TO CMOS CIRCUTTS: CURE 19. Construction ¢ unction Barer oD) o switches have to pass ‘0's and ‘1's equally well, complementary Switches with n- end petransstors are used. The truth table fr the ructure in Fig 110 is shown in Table 1.4. The complementary Switch is also called a arsmission gat or pass gate (complementary) ‘A commonly used circuit symbol for the transmission gate is shown in Fig, 1400, The multiplexer connection in tems of this symbol and transistor symbols is shown in Fig. 1.10c + L ® FIGURE 1.10. A CMOS 2nput multiplexer 14.7 Memory Werhave now constructed a sufficient sot of CMOS structures to tenable e memory element tobe constructed. A simple flip‘Nop using ‘one 2-input multiplexer and two inverters is shown in Fig. 1.11 TABLE 1.4. Two input multiplexer truth table s 8 3 5 ourreT A ¥ ° 7 7 om) x 1 o 1 18) ° x 1 ° (4) t x 1 o uA} Ts GMOSLOGiIG 17{a CHAPTER 1 INTRODUCTION TO cmos CIRCUTTS FIGURE 1.11. Connection ‘of components for asim le CMOS tip-top . 3 —T PT When LD = "1", Qis set to B and Qs set to D (Fig. 1.116). When. LD is switched to ‘0’ a feedback path around the inverter pair is tslebished (Fig, 1.12¢). This causes the current state of Q to be Stored. While LD = ‘0" the Input D is ignored. 1.5 Alternate circuit representations: In this section we will examine some alternate representations for the circuits developed so far. Generally, a design can be expressed in terms of behavioral, tructural, and physical properties. 13 ALTERNATE CIRCUIT REPRESENTATIONS 19 1.5.1 Behavioral representation ‘A behavioral representation describos how a particular design should respond to a given set of Inputs. In Section 1.4 the behavior of a gate was defined in terms of its boolean function Tatar OD. This is a technology independent behavioral specification at the Jogi level. No notion of how to implement this function is implied nor Is eny speed performance implied. Higher levels of behavioral escription are possible. For instance, an add operation may be summarized in @ high level language by sun =a +b Here no method of addition is implied and the word length is assumed to be that ofthe machine. further exemple ofthe behavior of the flip‘Nop designed previously is as follows: Ie(LD == 4) THEW a= Note there may be some ambiguity associated with this strle of Dehaviorel representation. It could also represent a multiplexer without implying storage of state. Higher levels of behavioral spec ication can specify the types of tegistrs involved in a design and the transfers that occur between them. Even less information about {implementation is implied. At some stage it i possible to express behavior as an algorithm written in high level language. The alm fof most modern design systems is to convert some such specification {nto a system design in a minimum time and with maximum like lihood that the systom will perform as desired 1.5.2. Structural representation {A structural specification specifies how components are intercon: nected to perform a certain function (or achleve a designated behavior) ‘We will use as an examplé of a complete structural description language. MODEL, a language conceived by Lattice Logic Ld, (Lat®2). ‘The specification for the inverter 's Part dar (in) out Nest out in vss Peet out in vad End —(CHAPTER 1 “SURE 132. Graphical felons of structural de- [Lifptions tor 8 cos NAND gate (schematics) INTRODUCTION TO CMOS CIRCUITS ‘The first line declares a pat called 4 followed by alist of inputs in this case 10. The outputs appear on the other sie of the symbol in this case ot. Following this is alist of transistors with their type and connections in the form eanaistor-type Eee aratn-conn gate-cona out in ‘Thus the first statement describes an transistor with drata = aut, gate = in, source = vss. The second statement describes § prtansistor with zain = out, gate = in, so: vad "The description for @2-iapot NAND gate would be part sand? (a,b) -> ovt Signal i eet Nfet Peet Pret out bal out a vad out b vad End In this description the internal signal 4 is declared by the keyword Signal. A diagram of this appears in Fig. 1.12 It is worthwhile to compare this description with a possible behavioral description out = -(240) out = (aot (and ab )) Te i i “ . 75 ALTERNATE GIRCUIT REPRESENTATIONS [Note that we can infer al ofthe transistor connections from these code fragments. However, the intermediate node 1 is “hidden. Im the MODEL description, we may augment the purely structural ‘description with some parameters such as capacitance and transistor ‘Sizing thal will affect performance. Although notation for this can bbe added to the behavioral representation, rather baroque forms result and the simple elegance of the logial statement is los. An expended MODEL description might be part aand2 (a,b) -> Signal 11 atee out. tha vss oat bb Peet out a vad size Pfet out b vdd size = Capacitance 11 50 Capacitance a 100 Capacitance b 300 Capacitance ov 200 Here the capacitance (in some units} has been specified. n addition, the p-transistor sizes have been modified according to some notional size parameter. This is shown in Fig. 1.12b. As we will lem in Subsequent chapters, this type of information is crucial to the per formance of CMOS cizcults. In other words, the behavioral description fensures that the function may be correctly Implemented but no reference is necessarily made to speed or other operational parameter. ‘The structural description allows the specification of all components that affect performance. The citcuit simulator SPICE [Nage75]| uses ‘a circut description for the specification of transistor connectivity ‘The specification of the NAND gate might look like the following -SUBCKT NANDZ DD VSS A B OUT Na Ty A YSS WSS NPET W HP} OUT A VDD vDD PFET e2 OUT 8 VDD vDD PFET ch A USS SOEF CBB VSS SOfP cour our ¥ss s0ofF ‘ENDS In this description the intemal model in SPICE calculates the parasitic capacitances inherent in the actual device using the device dimensions Specified. The capacitance statements in the above description add extra routing capacitance.22 CHAPTER FIGURE 1.13. Schematic Fepresentation of CMOS. fiptop ;RODUCTION TO GMOS GIRCUTTS Defining o transmission gate in MODEL. we have Part tg (a;cyed) -> weet ac b Peet ach D znd ‘We can now define the flip-flop (also called a D Iatch) as follows {a signal appended with “bar” is a complemented signal) part flipflop (in, 14, ldbar, qe abar) Signal tg (in, 14, Ldbar) -> a ine (a) ~> qbar sae (bac) > 4g tg (4) Ldbac, 1a) > @ End [Now we can use the flip-flop and other similarly constructed parts to hierarchically build larger and larger circuits "A move familiar type of structural description is the schematic diagram shown in Fig. 1.13. Here we have the graphical hierarchy 7 Hf yr op 7 15 ALTERNATE CIRCUIT REPRESENTATIONS. of parts corresponding to the MODEL descriptions that we have eveloped. The specification range from the circuit lave (transistors). to the logic level (gates), tothe functional block level {memory and collections of gates). ‘To all intents, both types of description aro interchangesble, with preference for use dependent on the user. The schematic de- Scription is more immediately descriptive — "a picture is worth a thousand words.” However, the language representation has some particular benefits, especially ifthe high level constructs such as Tooping, conditionals, and paremoter passing are available. For in stance. if we wanted to change the size of transistors inthe inverter wwe might say Part iny (10) (al -> out Wfet out in ss size =a Pfet out in vad size = 240 Bnd Here, nis a parameter passed to the inverter description to specify the size of the transistors. Emerging design systems show promise cof dealing with language and graphical aspects of a design in a consistent fashion, 1.5.3 Physical representation ‘The physical specification for a crcult is used to define how the particular part has to be constructed to yield a specific structure {and hence behavior. In an IC process, the lowest level of physical specification isthe photo-mask information required by the various processing steps required on the fabrication process (see Chapter 5) At this stage, we will not dwell on these details but propose a ‘simple model for the physical nature of a CMOS circuit, assuming that a program can translate our notation directly to the format needed for fabrication ‘typical physical representation fora transistor would consist ‘of two rectangles representing the lithography required to fabricate the transistor, Procise “design rules” specify the size ofeach rectangle. In addition, for each different process these rules change and the corresponding dimensions change —not necessarily linearly. Rather than try and remember these rules, we will use a single symbol to representa transistor In a non-metrc format. We will retain a form that reflects the physical nature of the transistor. The physical symbol for an n-transistor is shown In Fig. 1142 and Plate 1. This mirrors the physical realization in which at least two process levels are overlaid. As we have seen, the gate connection is on one layer of, the process and the source and drain on anather layer. A similar 2 J3 GHAPTER 1 INTRODUCTION TO CMOS CIRCUS: LeGURE 1.14. Physical symbols for transistors snd simple eres Ny ern ia oboe symbol is used for the p-ransistor, as shown in Fig. 1.14b and in olor in Plate 2. Here, a “horizontal” transistor is shown, These Symbols are overlaid on agri, The transistor symbol occupies three rid points, The center grid point is the connection point for the {ale of the transistor. The grid point to the right (or above is the train and the grid point tothe left (or bolow) isthe source. These two terminals are interchangeable. The schematic symbols are also ‘Shown forthe n-and p-transistrs in terms of grid connection points, "A symbolic layout for an inverter may be constructed using these symbols. I is substantially the same as the schematic but we hhave had to be careful about the layers in which connections have been made, We have “wires” on four layers. The interaction ofthese Nae layers is summarized in Table 1.5. OK denotes that 2 connection may be made, while an X designates thet a direct connection may be made between the two layers. Any off-diagonal OK requires “contact” (C) to connect the two layers ‘A completed symbolic layout for the inverter is shown in Fig. 1u1de. The symbolic layout for a transmission gate is shown in TE ALTERNATE CIRCUIT REPRESENTATIONS 25 FIGURE 1.14, (Continues)15 ALTERNATE CIRCUIT REPRESENTATIONS 26 CHAPTER | INTRODUCTION TO GMOS CIRCUITS TABLE 1.5. Physical layer Interactions ‘DIFFUSION DIFFUSION POLYSILICON “ALUMINUM Faison OK x Tranaisor OK (er peiffusion x OK ‘Transistor ok) polysilicon Transistor Transistor OK. OKC) ‘tuminum OKC) OK (Gh OK (CL OK Fig. 114d. Color versions of these are found in Plate 1. This may also be expressed in the form of a language description. The following represents the transmission gate inthe ICDL language (see Chapter 7 begin tg a device n (2/1) 01 t2: device p (2/5) orseast wire alum (0,0) (4,0) wire alam (0,6) (4/6) wire poly (2-4) (2/3) wire poly (217) (2-3) wire aluz (3,3) (1/5) wire alua (3,3) (3/3) wire alum (2,3) (1,3) wire alam (3/3) (4/3), contact ag (1/1) contact a2 (3,4) contact md (1/5) contact nd (3,5) end It consists of transistor, contact, and wire statements with type ‘qualifiers and grid coordinates. Note that although ths is an abridged form of the mask information needed to fabricate the trnsmission. gt, substantially larger than the corresponding MODEL structural Sescription, Using a number of such structures, we can construct ‘a physical sub-assembly that constitutes aflip-Top according to Fig. 1.15. Fig. 1.18a shows a simple physical abutment ofthe two trans- ‘mission gate cells and two inverter cells. The Vig and Vap supplies Ihave beon arranged to feed across the bottom and top ofthe cells. A feedback line in metal connects the Q output to one side of the input multiplexer. In Fig. 1.15b, the internal circuit details of the cells are displayed in the form of schematic circuit symbols. Finally, Fig. 1.15c shows the symbolic layout representation, which is identical in topology to that shown in Fig. 1.15b. Plate 2 illustrates this example in color. “To a large extent, most CMOS IC design involves the steps Illustrated in the preceding sections. Once a behavior is defined, the logie corresponding to that behavior is designed. That leads to a trangistor circuit description. Finally, a layout may be designed for the particular logic function. Quite often, frequently used logic structures may be designed at the layout {evel and placed in @ library. These library elements may then be assembled as illustrated fn Fig 1.16 to build more complex structures. An altermative to this approach is to compose primitive elements such as flip-ops from individual transistors. This yields more efficient layouts. Methods for designing inthis manner will be treated in subsequent chapters. FIGURE 1.15. Physical ‘construction of @ CMOS ‘pop 7 —‘CHAPTER 1 INTRODUGTION TO CMOS CIRCUTTS 1.6 _CMOS-nMOS comparison Many designers may have been introduced to VLSt design through MOS design. In order to illustrate tho salient features of CMOS. a Lape 1. CxO8 CMOS-nMOS quick summary MOS DS Se Togie Levels | ally restored logic. i. output sets at Yao oF Vs (GND) (i) Teansition Times oe an fall times are ofthe same order 1) Transmission Gates ‘Transmission gate passes both loge loves el ‘The output of transmission gate can be used qo dee the input of other teasmisson gates 1) Power Dissipation ‘Almost ceo static powar dissipation, However ‘power is dissipated duving logic transition Procharging Characteristics ‘Both n-type and plype devices ae aallabe for Srecharging 2 bus to Vop and Vax. Nodes can Be charged fully to Von or alternatively t0 Vs ina shor time. (i) Power Supply Toltage required to switch agate Is a ied pes ‘entage of Va. | arable range 1.310 15 volts (vi) Packing Density Require 2N deviers for N inpuls fr comple ‘mentary sale gates. Less for dynamle gates ii Pull to Pull-doven Ratio ‘Lod todrver device eatlo i typieally :t or 2A, Lg tayoun EOS encourages ele layout sls + Output does not sete at Vs {GND} — hence de add nose margin.” + Rise mes ae inherently slower than Fall + Pass transistor transfers loge 0° well but iogic "is degraded. Pass transistor cannot drive the gate of «second pass transistor With output of a ven gute = 0" power is dis sipatad inthe circuit i adition to power Giesipted during fogic vansitons.* + With enhancement mode transistor the best one ‘an do (with normal clocking) i to charge a bus to (Van ~ Yi). Generally use of bootstrap ping or hot cleking is needed to precharge to Vow + Somavehat dependant on supply voltage. Fined, + Reguire (+ 1) devices for N inputs + Load-to-enhancementdcver rll is typically 42 To optimize the loge 0" output level and min. Smize current consumption. ‘Depletion lad and diferent drtver transistor izes ibibo layout regularity quick summary” is ptesented in Table 1.6. However. it should be ‘Shessed that this is a broad overview and individual points may ary widely in importance. The comparisons are true of raioed Toate stvles for nMOS and those items marked with an asterisk are not valid for ratioless nSIOS logic design (dynamic circuits), The main points 10 note are that the output logic levels of CMOS are fully restored. CMOS gate consumes no DC povrer when the output is at"1'or 0'level. and 2N devices are required for an N-input gate for a fully complementory gate 1.7_Summary This chapter introduced a simple model for an MOS transistor and Gveloped logic that uses p-teansistors and n-transistors. This led {oa bosie discussion ofthe various levels of representation of circuits lind methods of composing these representations. The remainder of this book will elaborate on the materal introduced in this chapter. 1.8 Exercises 1.8__Exercises Ih elements 44 Design @ +-input NAND gate using CMOS swi Draw the ful transistor circuit for the function. La F = AB BCFAC implements a complemented cary function Design a complementary CMOS gate to perform this function. 1.3 Design @ input OR gate. Ta what conclusions do you come? 14 A 4-input multiplexer structure is needed to multiplex four ‘busses to a register in a microprocessor. Show two ways in which this may be implemented. Can you think of any reasons why one methed is preferable to the others? 1.5 Using graph paper and colored poncils, complete a symbolic, layout for the gates designed in Exercises 1.1, 1.2, and 1.3, What problems do you encounter? 16 Design and complete a symbolic I jout for a CMOS memory tlement other than that shown in Fig. 1.11, Include waveform Sequencing required for operation Te EXERCISES Ey— * | Mos TRANSISTOR 7 THEORY4a 444 I “ » “ FIGURE 21. MOS transis- tor symbols GHAPTER 2 MOS TRANSISTOR THEORY — 2. Introduction In Chapter 4 the MOS transistor was introduced in terms of its ‘operation as an ideal switch. In this chapter we will examine the characteristics of MOS transistors in more deal olay the foundation for predicting the performance of the switches. which is less than ideal. Fig. 2.1 shows some ofthe symbols that are commonly used for MOS transistors. The symbols In Fig. 21a will be used where itis only nacessary to indicate the switch logic necessary to build {2 function. I the substrate connection needs to be shown the symbols in Fig. 2.1b will be used, Fig, 2.1¢ shows an example of the many symbols that may be encountered in the literature ‘An MOS transistor is termed a majority-carier device. in which the current in a conducting channel between the source and drain is modulated by a voltage applied to the gate. In an n-type MOS transistor (ie. nMOS), the majority carriers are electrons. A positive ‘voltage appliod on the gate with respect to the substrate enhances the number of electrons in the channel (the region immediately ‘under the gate) and henoe increeses the conductivity ofthe channel. For gate voltages less than a threshold value denoted by V,, the channel is cutoff, thus causing a very low drain-to-source current ‘The operation of a p-type transistor (ie. pMOS) is analogous to the MOS transistor, with the exception that the msjority carriers are holes and the voltages are negative with respoct to the substrate. ‘The frst parameter of interest that characterizes the switching behavior of an MOS device is the threshold voltage. V, This is defined as the voltage at which an MOS device begins to conduct mon"), One can graph the relative conduction against the dif- ference in gate-lo-ource voltage in terms of the sourceto-drain ccurent (l.) and the gate-o-source voltage (Vy). These graphs for a fixed drain source voltage Va, ere shown in Fig. 22. Itis possible to make ndevices that conduct when the gate voltage is equal to the source voltage, while others quire a postive diference between gato and souree voltage to bring about conduction (negative for Prdevices). Those doviees that are normally cut-off (ie., noncon- ducting) with 2oro gate bias (gate voltage-source voltage) ae further classed as enhancement mode devices, wheress those devices that ‘conduct with zero gate bias are called depletion mode devices. The channel transistors and p-chennel transistors are the duals of each other; that is, the voltage polarities required for corect operation are the opposite. The threshold voltages for n-channel and p-channel fovices are denoted by V,, and V,, respectively In GMOS technologies both n-chennel and p-channel transistors are fabricated on the same chip. Furthermore, most CMOS integrated Circuits, at present, use transistors of the enancement type. orl ee owe: 7 vourace : a se om 2.1.1. nMOS enhancement transistor ‘The structure for an n-channel enhancement type transistor shown in Fig. 2.3 consists of a moderatoly doped p-type silicon substrate into which two heavily doped n° regions. the source and drain. Jone Set ROLY Oy 21 INTRODUCTION 33 FIQURE 22. Conduction characterises fo hancement and depletion mode transistors (assum Ing feed ¥.) FIGURE 23. Physica! structure of an AMOS, transistor