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use IEEE.STD_LOGIC_1164.ALL;
entity incisob is
Port ( s,r: in std_logic;
Q,Qn:buffer std_logic );
end incisob;
begin
Q <= (not s) nand Qn;
Qn<= not r nand Q;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity b is
Port ( S,R: in std_logic;
Q,p:buffer std_logic );
end b;
architecture Behavioral of b is
begin
P <= s nor Q;
Q<= r nor P;
end Behavioral;
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