Power IC Design

Power IC Design
From the Ground Up
Gabriel Alfonso Rincn-Mora
Georgia Institute of Technology
Rincon-Mora.gatech.edu

Chapters
1. Powering Microsystems
2. Analog Electronics
3. Bias Currents
4. Voltage References

5. Linear Regulators
6. Linear Power Supplies
7. Switched-Inductor Regulators
8. Switched-Inductor Supplies
Final Notes on Design

Page 1

Power IC Design

Chapter 1. Powering Microsystems

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1.2. Energy and Power Sources

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1.3. System Composition

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1.4. Design

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1.5. IC Requirements

1.1.A. Emerging Markets

Applications: Bio-monitors, micro-sensors, pacemakers, cochlear processors,
10200 W

defibrillators, hearing aids, reconnaissance, micro-robots, remote meters,

Peak to 510 W

0 22 mW

110 mW

Micro-sensor

neural recorders/stimulators, retinal implants, and others.

1100 mW

40250 mW

Requirements: Useful, unobtrusive, and economical.

Lightweight
Self-powered (with onboard power source)
Self-sustained (with ambient energy)
Silicon microchip (i.e., on-chip, in-package,
and on-package integration)

Page 2

Bio-monitor

Portable (i.e., small and compact)

Micro-robot

Smart (e.g., low-power sensor, processor, transmitter, etc.)

Power IC Design

B. Technological Constraints
Portable and Unobtrusive

Small Footprint: 1 Microchip

Low Breakdown Voltages

Low Supply Voltages: 11.8 V

High Integration

Diverse Power Levels: nW's to W's

Diverse Supply Voltages: 0.52 V
Low CMAX/m2 15 fF/m2

Low Filter Density

E.g.: 1 nF requires 260 260 m2

LMAX 40100 nH
Noise-Sensitive (analog) Blocks

Accurate and Fast Supplies:

vSUPPLY(DCRIPPLEDUMPS) 10100 mV

High Silicon (wafer) Density

Digital VLSI (CMOS) and

Mixed-Signal (BiCMOS) Microchips

C. Typical Microelectronic Systems

Power: Mixed signal Steady and switching power components.
On average, lightly loaded Low PAVG.
Highly functional Diverse vLOADiLOAD profiles.
High combined PPEAK.
Supply should: Draw maximum energy and power Condition source.
Supply system Feed and condition power.

Power (W)

Extend battery life Reduce load power and transfer losses.

PPeak

Mode 3

Mode 1
PA vg

Mode 2
Time (t)

PAVG is low, PPEAK is high, and load power and transfer losses limit battery life.

Page 3

Power IC Design

1.2. Energy and Power Sources

A. Terminology
Battery:

Energy-constrained source.

Primary:

Non-rechargeable battery.

Secondary:

Rechargeable battery.

Parameters:

Capacity in mA.Hr Energy-storage capacity.

Cycle Life Number of recharge cycles possible.
Internal equivalent series resistance RESR
Series voltage drop and ohmic power lost.
Self-Discharge Leakage.
Size and Weight Energy density and power density.

Page 4

Power IC Design

B. Energy and Power Sources

Inductor:

High Power
Very Low Energy
Quasi Lossless
Cumbersome
Capacitor: High Power
Very Low Energy
Quasi Lossless
Very Fast
Li Ion & Moderate Power
Super
Moderate Energy
Capacitor: Moderate Speed
Fuel Cell: Low Power
High Energy
Slow
Nuclear
Very Low Power
Battery:
Very High Energy
Unsafe and Costly

Transducer: Very Low Power

Virtually Infinite Energy
Intermittent

Li Ion(Super C): Depletes in years(days) and survives 2k(150k) recharge cycles.

Power-Assisted Energy Sources

Space-constrained microsystems should not oversize:
Energy-dense sources for power

or

Power-dense sources for energy.

Power-assist an energy-dense source.

Match source to load level:
Transducer
Nuclear Battery
Fuel Cell
Li Ion
Super Cap.
Capacitors
PAVG

Inductors

PPEAK

Page 5

Energy Sources:
Low PAVG
Charger
Power Banks:
High PPEAK
Burst Power
Conditioners:
Instant Power
Transfer Energy

Power IC Design

Energy Sources: Carbon Fuels

Fuel Cell: Electrochemical energy-conversion device.
Carbon Fuel + Oxidant C Product (e.g., CO2) + H Product (e.g., H2O) + e
Basic Advantage: 10 Li Ion's energy density.
Miniaturization: Eliminate fuel reformer.
Direct-methanol (DM)
proton-exchange membrane (PEM)
Glucose fuel cell
Challenges:
Manage hydrogen and carbon byproducts.
Low and decreasing power density.
Slow to respond.
Fuel leaks through filters and membrane (e.g., methanol crossover).

Light, Heat, and Electromagnetism

Photovoltaic Cell:

On-chip.

Photons separate

15 mW/cm2 for sunlight.

electronhole pairs.

5 W/cm2 for artificial light.

MEMS compatible.

Thermoelectric Piles:

200 V/K per pile pair.

Thermal gradient induces

10200 mV with 35.

e's in N and h+'s in P

530 W/cm3 with 35.

to flow to cold plate.

Inductively Coupled Coils:
produces magnetic-flux
that induces LR current.

d
ry

ma

Pri

il

HP

Co

LR

Rich
Source

we
r

Changing LT current

mW/cm3 across mm's.

W/cm3 across cm's.

ary

nd

co
Se

Page 6

il

Co

Small coils capture

little EM energy.
ACDC conversion.
Rich source.

Power IC Design

Motion
Vibrations and shocks are abundant and often steady at 1300 Hz.
Electromagnetic

Low voltage.

Transducer:

1 W/cm3.

Magnetic flux changes

ACDC conversion.

to induce charge flow.

Bulky magnet and coil.

Piezoelectric Transducer:

On- and in-package.

Deformation offsets

200300 W/cm3.

charge centers (polarizes)

ACDC conversion.

to induce charge flow.

Electrostatic Transducer:

MEMS compatible.

Motion loses energy to

50100 W/cm3.

opposing field when

Synchronization.

pulling CVAR plates apart.

Pre-charge CVAR.

Power Sources: Rechargeable Electrochemical Batteries

Lead Acid: High power, but bulky and low cycle life Good for cars.
Alkaline: Long shelf life, but low power density and low cycle life.
Good for electronics that are used infrequently like flashlights.
Nickel Cadmium (NiCd): Higher energy density, but contains toxic metals
and suffers from cyclic memory effects (non-recoverable
crystalline formations that induce higher self-discharge rates).
NickelMetal Hydride (NiMH): Less memory effects, less toxic,
and higher energy density, but poorer electronic performance.
Lithium Ion (Li Ion): No memory effect, not toxic, and better electronic
performance, but costly and explosive chemistry when over-charged.
Super/Ultra Capacitor: Long cycle life, but leaky.

Page 7

Power IC Design

Nickel-Based Batteries
Nickel Cadmium:
Higher cycle life.
Lower RESR.
Lower leakage.

Typical Discharge Profile

Most energy
is between
1.5 and 0.9 V.

Periodic discharge cycles mitigate

cyclic memory effects on
degraded discharge rates.

About 1000 Cycles

Typical Discharge Profile

Li-Ion Batteries
Li Ions:

Higher capacity, lower RESR,

lower leakage, and more
consistent across cycle life.

Most energy
is between
4.2 and 2.7 V.
10002000 Cycles

Charge Sequence:

Thin-Film
Li Ion

Precondition: With constant low trickle current.

Current Regulation: Charge with constant current.
Voltage Regulation: Constant voltage so iCHG drops as vBAT nears target.
Termination: Stop when iCHG reaches IMIN IEnd.

Page 8

Power IC Design

1.3. System Composition

Power M anagement IC's
Power
Routing

...

M ixed-Signal
Layout

Supervisory
Ckts.

DC-DC Cont.
Op-Amps

V/I
References

Protection
Ckts.

Oscillator
Linear Reg's

Power
Switches

Analog/Digital
Drivers

Passive/Active
Filters

A. Complete Microelectronic System

Power-Assisted
Energy Source

Energy-/Power-Supply System
Management
Circuits

Micro Fuel Cell

Functional
Load

High Load Mode

Sensor

Micro Battery

Moderate Load Mode

Driver

Ultra Capacitor

Light Load Mode

Processor

Sleep Mode

Micro Heat Engine

Source
Management

Etc.

Condition
Source

Telemetry

Etc.

Etc.

Circuit Management

Transfer
Energy/Power

Condition
Power

Energy Source:

Switched-Inductor ChargerSupply

Transducer or Fuel Cell

Maximum Power-Point Tracker

Low PAVG

Power Source:

Fast Multiple-Output Supply

High PPEAK

Li Ion or Super Capacitor

Fast Low-Voltage Starter

Page 9

Power IC Design

Typical Supply Components

Bias Currents: Supply and process independent.
Voltage References: Temperature, input, and fabrication-run independent.
Regulating Power Supplies:
Fast and temperature, input, fabrication-run, and load independent.
Difference between voltage references and power supplies Load.
Power supplies supply heavy and dynamic loads.
Voltage references bias light and steady loads.
Battery Chargers: With protection and maximum power-point control.
Protection: Electrostatic-discharge (ESD), thermal, over-current,
under-voltage lockout (UVLO), safe-operating area (SOA), etc.

B. Regulating Power Supplies

Linear Power Supply:

Linear Power Supply

AE compares vOUT and vREF to generate

an error vERR that adjusts the
conductance of a series switch.
Analog signals only.
Switched Power Supply:

Switched Power Supply

AE compares vOUT and vREF to generate

an error vERR that adjusts the
connectivity of a switching network.
Switches energize and drain inductors and capacitors
from vIN into vO in alternating phases of a switching cycle.
Analog and digital signals.

Page 10

Power IC Design

Comparison
Linear Power Supply

Switched Power Supply

Limited output range: vOUT < vIN

Flexible: vOUT or vIN

Low cost: Less PCB and Si area

Expensive: More PCB and Si area

No switching noise

Switching noise

Quick to respond

Slow to respond

Switch voltage = vIN vOUT 200 mV

Switch voltage 50 mV

Lossy Inefficient

Less Lossy More Efficient

Low-noise/-power applications

Boosting and high-efficiency systems

Check mark highlights features Advantages.

Design Considerations
Point-of-Load (PoL) Regulation:
Regulate vOUT at the load More accurate.
Satisfy specific load Better performance.
Shunt power-supply noise Less noise.
Classify supplies according to voltage, power, accuracy, speed, etc.
High power and poor accuracy Switched-inductor supply.
High power and good accuracy Switched-inductor supply + Linear supply.
Low power and good accuracy Linear supply.
Boost, low power, and poor accuracy Switched-capacitor supply.
Example:

Data

2.7-4.2V
Thin-F. Li-Ion

0110

0.9-1.4V
Fuel Cell

Chrgr

0.5-1V
P/DSP
Core

Power Management Core

Adaptive Buck/Boost
DC-DC Converter
Dynamic Buck/Boost
DC-DC Converter

0110
2.5-5.5V
PA

Fixed Buck/Boost
DC-DC Converter

LCD

Page 11

Power IC Design

Wireless Power-Supply System Example

Objectives: Draw, condition, and supply power to the loads.
Harvester-Assisted Li-Ion Power-Supply System

Point-of-load (PoL)
regulation for accuracy.
Multiple outputs
for PoL performance.
Dynamically adaptive
for better efficiency.
Harvester-assisted for
longer operational life.
One inductor for

Switched converters save power.

smaller board footprint.

Linear supplies suppress switching noise.

Top-level
Verification

Design Flow

1.4. Design

k=0

All Macro-Model Sim

k=1

Mixed-Level Sim 1

k=2

Mixed-Level Sim 2

k=N Full Transistor-Level Sim

Page 12

Power IC Design

System design with macro-models:

Hourglass Design Flow

Design architecture.

TopDown Design

Verify operation with simulations.

DownTop Assembly

Determine system/block specifications.

Circuit
Design
Top-level
Verification

Design Flow

System
Design

Top-Level Specification

Circuit design with microelectronic devices:

System-Level Simulation
Spec
U1

Spec
U2

Spec
UN

Circuit
Design
U1

Circuit
Design
U2

Circuit
Design
UN

Circuit
Sim
U1

Circuit
Sim
U2

Circuit
Sim
UN

Design architecture.
Verify operation with simulations.
Design physical implementation (layout).
Top-level assembly:
Assemble top-level circuit and layout.
Ensure circuit matches layout.
Verify circuit with simulations.
Extract circuit from layout and simulate.

Full Transistor-Level Sim

Tape-out submission and fabrication.

Iterate and re-design at every level.

Fabricate IC

Top-Level Simulations
Transistor-level simulations can be computationally intensive and long
Start with behavioral-based simulation using macro-models.

system by sequentially
substituting least-to-most

Top-level
Verification

Then, gradually build transistor-level

Design Flow

Then, substitute one block k at a time.

k=0

All Macro-Model Sim

k=1

Mixed-Level Sim 1

k=2

Mixed-Level Sim 2

k=N Full Transistor-Level Sim

1st Analog, linear blocks: Op amps, comparators, etc.

2nd Analog, nonlinear blocks: Bi-stable bias and reference circuits.

11%

3rd Slow-switching blocks: Power-on-reset, UVLO, etc.

4th At-speed digital gates: Drivers, etc.
5th At-speed, high transistor-count blocks: Oscillator, ramp generator.

Page 13

60%

Simulation Time

computationally intensive blocks.

Power IC Design

1.5. IC Requirements

Parameter
Linear Regulator
Vout (overall accuracy)
Line Regulation
Load Regulation
Short Ckt Current

Specifications
Min.
Typ.
2 85

Max.
3

Simulated Perf.
Min.
Typ.
Max.

3 15
10
50

2 87
3
190

31
7
42
250

Meas. Perf.
Mean Sigma
3 05
10
45
225

01
2
5
30

Un

V
m
m
m

Reference

Market Demand
Unobtrusive
On-chip, in-package, and on-package integration.
Powered from a tiny battery.
Wide input-voltage range: 0.91.8 V for NiMH or 2.74.2 V for Li Ion.
Low headroom vIN(MIN).
Limited energy and power.
Low quiescent power:

Low quiescent current iQ.

Low conduction power: Low-resistance switches RSW.

Low gate-drive power: Low-capacitance switches CSW.
Low switching frequency fSW.
Duty-cycled operation:
Disable blocks, but with:

Short wake-up time tWAKE.

Low leakage current iLEAK.

Define power modes: Adjust frequency, voltages, and bias.

Page 14

Power IC Design

High functionality

Parameter
Linear Regulator
Vout (o erall accuracy)
Line Regulation
Load Regulation
Short Ckt. Current

Multiple outputs
Wide output-voltage range:

Specifications
Min.
Typ.
2.85

Max.
3

Simulated Perf.
Min. Typ.
Max.

3.15
10
50

2 87
3
190

3.1
7
2
250

Meas. Perf.
Mean Sigma
3.05
10
5
225

01
2
5
30

Un

V
m
m
m

Reference

E.g., 0.52 V for DSP and 23.5 V for PA.

Wireless telemetry
Power-hungry power amplifier (PA)
Dynamic power supply High bandwidth fBW.
Extreme mode transitions: Idle to high performance.
Wide load dumps: From maybe nA's to A's.
Fast load dumps: From maybe several ns to several s.
Fast power supplies High bandwidth fBW.
Highly integrated
Noisy supplies: Require high power-supply rejection PSR.
Noisy ground: Design common-mode circuits.
Require high common-mode rejection ratio CMRR.

Noise-sensitive loads
Accurate power supplies: Within maybe 1%2%.
Fast power supplies: Variation within maybe 2%5%.
Reliable and low cost
Design simple circuits because fewer transistors
Occupy less silicon area Yield more chips per wafer.
Exhibit less parasitic capacitance Higher-frequency poles.
Incorporate fewer nodes.
Introduce fewer poles

Faster response.
More stable feedback loops.

I.e.: Highly functional: complex, fast, accurate, low cost: CMOS and few components,
small: SoC/SiP/SoP, long life: low power, reliable: few transistors, etc.

Page 15

Power IC Design

Chapter 2. Analog Electronics

2.1. Two-Port Models
2.2. Microelectronic Devices
2.3. Frequency Response
2.4. Analog Transistor Circuits
2.5. Analog Building Blocks
2.6. Negative Feedback
2.7. Simulations

2.1. Two-Port Models: Philosophy and Extraction

Purpose:

Model a device or complicated circuit with simple unloaded

two-component networks that can predict loaded response.

Philosophy: Avoid model redundancies.

with orthogonal components.

Two-Port Models

Extraction: When deriving a parameter,

nullify the effects
of the other.
Norton Equivalent: Derive gain ANI when iR = 0 vN = 0: Short terminals.
Derive resistance RP when control signal sC = 0.
Thvenin Equivalent:

Derive gain ATV when vR = 0 iR = 0: Remove load.

Derive resistance RS when control signal sC = 0.

Page 16

Power IC Design

Examples
Sample InputOutput Model

Sample Model:

Popular InputOutput Model

Derive RIN when iO = 0 Remove load.

Derive AG when iRIN = 0 vIN = 0: Short input.
Derive AV when vRO = 0 iO = 0: Remove load.
Derive RO when vIN = 0 Short input.

Popular Model:

Derive RIN as is No redundancies to consider.

Derive GM when iRO = 0 vO = 0: Short output.
Derive RO when vIN = 0 Short input.

2.2. Microelectronic Devices

Page 17

Power IC Design

A. PN-Junction Diode
Large-Signal Model:

v
i D = IS exp D 1
Vt

v D >3Vt

v
IS exp D A J
Vt

v D 0.6 0.7 V

Forward Bias: vD > 0

Junction Area AJ

Reverse-Saturation Current IS
Thermal Voltage Vt
Small-Signal Model:

rd

1 Vt

gd ID

Diffusion Capacitance

C D = C DIF + C DEP

C DIF

qC

= gd F = F
vC
rd

Forward-Transit Time F

Depletion Capacitance

Zero-Bias Capacitance/Area CJ0"

C DEP =

Built-In Voltage VBI

A J C J0 ''
v
1 D
VBI

If vD < 0 qC(DEP) >> qC(DIF) CD(REVERSE) CDEP.

If vD > 0 qC(DIF) >> qC(DEP) CD(FORWARD) CDIF >> CDEP.

B. Bipolar-Junction Transistor (BJT)

Large-Signal Model: Diode Current

v v
iC IS exp BE 1+ CE A E
Vt VA

iB =

iC
0

i E = i B + iC

v BE 0.6 0.7 V

Base-Width Modulation VA
Small-Signal Model:

v v
iC IS exp EB 1+ EC A E
Vt VA

v CE 200 300 mV VCE(MIN)

Emitter Area AE
gm

1
I
C
rgm Vt

r 0 rgm =

C C BE = C DIF + C DEP q

DIF >>q DEP

C C BC = C DIF + C DEP q

DEP >>q DIF

Transitional Frequency fT

gm
2(C + C )

Page 18

Current Gain 0
0
gm

C DIF
C DEP

ro

VA
IC

Power IC Design

C. MOS Field-Effect Transistor (FET)

Channel Width W

Large-Signal Model:
NMOS

Channel Length L

Subthreshold and Saturated

v
W
IST exp GS
L
nVt

v GS <v TN

i D(SUB,SAT) v

DS >4Vt

n 1.53

Inversion and Triode

W
2i D
K N' ( v GS v TN ) v DS , VDS(SAT) v GS v TN
W
L
K N'
Inversion and Saturation
L

v GS >v TN
W
2
i D(SAT) v V
0.5 K N'( v GS v TN ) (1+ N v DS )
Threshold vT
DS
DS(SAT)
L
v GS >v TN

i D(TRI) v

PMOS

DS <VDS(SAT)

v TN = VTN 0 + N

2 v BS 2

Transconductance Parameter K'

Channel-Length Modulation

vSG > v TP

i D(SAT) v

SD VSD(SAT)

W
2
0.5 K P'( v SG v TP ) (1+ P v SD )
L

v TP = VTP0 + P

2 v SB 2

Zero-Bias Threshold VT0

Bulk/Body Effect 0.40.6 V

Surface Potential 2 0.6 V

Small-Signal Parameters
Small-Signal Model:
g m(SUB)

g mb

CGS(OFF) = CGD(OFF) = CGD(SAT) = WCH L OL COX"

1
CGS(TRI) = CGD(TRI) = WCH L OL COX"+ WCH L CH COX"
2
2
CGS(SAT) = WCH L OL COX"+ WCH L CH COX"
3

Page 19

ID
nVt

g m(INV)

W
g m(INV) 2I D K'
L

2 2 VBS

rds

fT =

1
V
A
N ID ID

gm
2(CGS + CGD )

Overlap Length LOL

Oxide Capacitance/Area COX"

Power IC Design

SubthresholdInversion Transition

Current: iD carries diffusion and drift currents iD = iD(DIF) + iD(FLD).

gm: Exponential gm(BJT) > n-Suppressed exponential gm(SUB) > Square-law gm(INV).
Transition: At gm(SUB) = gm(INV) WCH(SUB) =

IDL
VDS(SAT) = 2nVt VDS(SUB).
2
2n 2 Vt K '

Weak Inversion: 50 mV of transition VDS(SAT) vGS vT 2nVt 50 mV.

Warning: Models usually do not emulate weak inversion well.
gm rises with W in strong inversion and peaks in subthreshold.
fT falls with 1/W in strong inversion and with 1/W in subthreshold.

gmfT
Tradeoff

For high gm, edge subthreshold WCH should not exceed WCH(SUB) by much.

2.3. Frequency Response

Page 20

Power IC Design

A. Poles and Feed-Forward Zeros

Parallel capacitors shunt energy away from nodes and require time to charge.
CSH shunts energy when 1/sCSH falls below parallel RSH, past pole pC.
1
sCSH

f=

1
pC
2R SH CSH

= R SH

Delays signal 90.

Feed-forward capacitors: Steer energy away from vIN Input pole pIN.
Add energy to vO Zero zFF in GM(EFF) when iFF iGM.
i FF =

v IN v O
ZC

v O =0

= v INsC FF z

FF =

GM
2C FF

= ( iGM i ZO ) v

O =0

= iGM = v IN G M

Short-Circuit Transconductance
An in-phase capacitor removes the effects of a pole zLHP recovers 090.
An out-of-phase capacitor opposes circuit zLHP 180 zRHP subtracts 090.

B. Current-Limiting Zeros

At Low Frequency: CSHUNT is open iO = iIN and vO = iINRO Flat response.

At Higher Frequency: CSHUNT shunts current energy away from RO.
iO and therefore vO drop past pole pSHUNT when 1/sCSHUNT RO + RLIMIT.
At High Frequency: Series RLIMIT limits CSHUNT's shunting current.
RLIMIT arrests (i.e., removes) the effects of pSHUNT past in-phase zero zLIMIT
when 1/sCSHUNT RLIMIT Response flattens to vO = iIN(RO || RLIMIT).
1
sCSHUNT

f=

1
z LIMIT
2R LIMIT CSHUNT

Page 21

= R LIMIT

Power IC Design

C. Miller Split

iFF zRHP
C MI = (1+ A V ) C M A VC M
!
1 $
C MO = ##1+
&& C M C M
" AV %

When vIN rises, vO falls more vIN vO rises more than vIN:
(vIN vO)CM demands more current than vINCM, like higher capacitance would.
Z MI

v IN
v IN
v IN
1
1
=
=
=

iC ( v IN v O ) sC M ( v IN + v IN A V ) sC M s (1+ A V ) C M sC MI

vO rises when vIN hardly falls vO vIN rises nearly as much as vO.
(vO vIN)CM demands nearly as much current as vOCM.
Z MO

vO
vO
vO
1
1
=
=
=

#
sC MO
iC ( v O v IN ) sC M #
1 &
vO &
( sC M s %1+
( CM
% vO +
AV '
$
$ AV '

D. Analysis: Capacitors Shunt Resistors

Capacitors open at low frequencies: Capacitors are absent at low frequencies.
Capacitors shunt resistors past 1/2REQCEQ poles.
Capacitors replace resistors above the poles they establish.
The lowest-frequency pole corresponds to the highest REQCEQ product.
Intentional, load, and C and CGS capacitors normally shunt first.
Frequency-Response Analysis
Low-frequency gain A0: Exclude all capacitors to determine A0.
p1: Determine which capacitor shunts its parallel resistance first.
Largest REQCEQ when all other capacitors are still open.
p2: Replace REQ1 with CEQ1 and find the next highest REQCEQ.
fP: If N REQCEQ's are close, N poles are near f P

Page 22

1
.
2 #$Avg R EQC EQ %&

Power IC Design

2.4. Analog Transistor Circuits

A. Signals and Terminals

Signal Composition
Bias (i.e., dc, steady state): All upper-case variables IC, VDS, etc.
Small-Signal Variations: All lower-case variables id, vbe, etc.
Entire Signal: Lower-case variables with
upper-case subscripts iS, vD, etc.

BJT

Terminal Roles in Transistors

Bases and gates carry little to no current Bad outputs.
Collectors/drains and emitters/sources carry almost
all the current: iC iE and iD = iS Good outputs.
iC/E and iD/S are sensitive to vBE and vGS.
Bases, emitters, gates, and sources are good inputs.
iC/E and iD/S are insensitive to vC and vD.
Collectors and drains are bad inputs.

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MOS

Power IC Design

Transconductor

B. Transistor Primitives
Possible Transistor Configurations
Common Emitter (Source)
Base to collector: ic = vbGM Transconductor.
Common Collector (Drain)

Voltage Follower

Base to emitter: vb ve Voltage Follower.

Common Base (Gate)
Emitter to collector: ie ic Current Buffer.

Current Buffer

Relative Magnitudes:
gm

>>

1/r, gmb >> gds

1/gm

<<

r, 1/gmb << ro, rds << gmrro, gmrdsrds

C, CGD << C, CGS(SAT) << CINTENTIONAL

Low

<<

Moderate <<

High

<< COFF-CHIP

<< Very High

C. Signal Flow
Possible Signal-Flow Paths
First Input: Higher vB (+) raises vBE iC rises (+) iC lowers vC () and raises vE (+).

Second Input: Lower vE () raises vBE iC rises (+) iC lowers vC ().

Polarity:

Base/gate to emitter/source In phase.

Emitter/source to collector/drain In phase.
Base/gate to collector/drain Out of phase Only one that inverts.

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Power IC Design

D. Expressions
Small-Signal Translations:
RE/S degenerates vbe/gs in gm.
gm
ic/d/s
G M(EQ)
v b/g
1+ g m R E/S

RE/S loads RB(EQ) and RC/D(EQ):

vb
R B(EQ) = r + (1+ g m r ) R E = r + (1+ 0 ) R E
ib
v c/d
R C/D(EQ) = ro + g m'ro R E/S' + R E/S'
ic/d

R E/S' = R E/S || ( r + R B )

RC/D loads RE/S's 1/gm and r + RB shunts RE:

r + R C/D
v e/s
R E/S(EQ) = o
|| ( r + R B )
ie/s
1+ g m'ro

v eg m' =

v eg mr
r + R B

RB degenerates veb in gm.

RGM

E. Analysis
Analysis: Trace small-signal path and track voltagecurrent conversions.
Example: iin vg(CS) id(CS) ve(CB) ie(CB) vo1 ie(CC) vo
# 1 &
v o1
(( ( rds(PL) || R B(CC) ) R Sg m(CS)rds(PL)
= ( R S ) (g m(CS) ) ( rds(CS) || r(CB) || R GM(CB) ) %%
i in
$ R GM(CB) '

g m(CC)
vo
rds(NL) 1
=
v o1 1+ g m(CC)rds(NL)

Where:

R GM(CB) =

ro(CB) + ( rds(PL) || R B(CC) )

1+ g m(CB)ro(CB)

2
g m(CB)

R B(CC) = r(CC) + (1+ 0(CC) ) ( rds(NL) || ro(CC) )

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Power IC Design

2.5. Analog Building Blocks

A. Current Mirror: Theory of Operation

Basic Operation:
iC and iD are sensitive to vBE and vGS.
iC and iD are insensitive to vCE and vDS.
vBE's and vGS's equal iO iIN.
(
(
! v $ +! v $
!v $ +
iC = IS *exp # BE & 1-#1+ CE & IS *exp # BE & 1- i IN i O
" Vt % ," VA %
" Vt % ,
)
)
!W$
!W$
2
2
i D = # & K ' ( v GS v T ) (1+ v DS ) # & K ' ( v GS v T ) i IN i O
"L%
"L%

Since vIN = vBE = vDIODE, Q1 is a diode-connected transistor.

And by translation, M1 is also a diode-connected transistor.
Voltage Limits:

vIN = vBE or vGS

and

Page 26

vO VCE(MIN) or VDS(SAT).

Power IC Design

B. Differential Pair: Small-Signal Operation

Inputs: Each input carries common-mode voltage vIC and
opposite halves of differential signal vID vIC 0.5vID.
Differential Signals:

Equal, but opposite io's drop zero volts across RTail.

Circuit reduces to two CE/CS transistors.
R ID

GD

v id
v id
=
= 2r
i id # 0.5v id &
%
(
$ r '

R OD

v od
v od
=
= 2ro
iod " 0.5v od %
$
'
# ro &

io1 io2 io1 io2 (0.5v idg m ) 0.5v idg m

=

= g m
v id
v id v id
v id
v id

C. Summing Transconductor
Matched differential pairs project voltages to matched currents:
iOD = (vP vN)gm + (vAP vAN)gmA iOD = vIDgm + vAgmA.

If MAT matches MT.

If MA1,A2 matches M1,2.
iOD = (vID + vA)gm if gmA gm.
!g $
MA1,2 produces a programmable offset that M1,2 refers to vID as v OS = v A # mA & .
" gm %

GM = gm
if gmA = gm.

Analog
Summer

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Power IC Design

D. Differential Amplifier: Folded-Cascode

Bias:

MT sinks ITAIL.
Negative feedback ensures vI1 vI2 M1 and M2 split ITail.
M9 and M10 source I9,10 > ITAIL M5 and M6 sink excess I9,10 0.5ITAIL.

Limits: iO(MAX)+ = (I10 i2(MIN)) (I9 i1(MAX)) = i1(MAX) = ITAIL

iO(MAX) = (I9 i1(MIN)) (I10 i2(MAX)) = i2(MAX) = ITAIL
vO(MAX) = vDD VBIAS3 + vSG6 vSD6(SAT) = vDD VBIAS3 + |vTP|
vO(MIN) = vSS + vDS4(SAT)
Small-Signal Gain:
vo = (i6 igm4)rds4 2i6rds4

where

" 1 %
i 6 = 0.5v id (g m2 ) ( rds2 || rds10 || R S6 ) $
' igm4
# R S6 &
" 1 %
v
o 2 ( 0.5g m12 ) R S56 $
' rds4 = g m12 rds4
v id
# R S56 &

2.6. Negative Feedback

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Power IC Design

A. Loop Composition and Action

Negative feedback opposes the effects of external forces on the loop.

Definition: Loop Gain ALG AOLFB.

Loop gain reduces sE to nearly 0 when stable.
s E = s I s FB = s I s E A OL FB = s I s E A LG =

sI
s
I 0
1+ A LG A LG

sFB sI sFB "mirrors" sI Loop regulates sFB to sI.

sO sFB/FB sO is a FB translation of sFB Of sI.

B. Feedback Concepts
Gain Relationships: AOL sO/sE
Mixers:

and

FB sFB/sO.

Sum (mix) voltages in series.

Sum (mix) currents in parallel (shunt).

Samplers:

Monitor (sample) voltages in parallel (shunt like a voltmeter).

Monitor (sample) currents in series (like an ammeter).

Impedance: Series feedback raises open-loop impedance.

Z CL = Z OL + Z SERIES = Z OL + Z OL ( A OLFB ) = Z OL (1+ A OLFB )

Shunt feedback shunts open-loop impedance.

Z CL = Z OL || Z SHUNT = Z OL ||

Z OL
Z OL
=
A OLFB 1+ A OLFB

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Power IC Design

C. Frequency Response
A CL =

A OL
1
= A OL ||
1+ A OLFB
FB

ACL Whichever is lower.

When 1/FB dominates, negative feedback reduces AOL to 1 + ALG and

removes AOL poles and zeros: pOL1,2,3 and zOL2 in the example.

Example

When AOL dominates, poles and zeros in AOL appear in ACL: zOL1 and pOL4.
1/FBAOL crossings remove and add poles and zeros in ACL: pCL1 and pCL2.

A CL =

A OL
1
= A OL ||
1+ A OLFB
FB

ACL Whichever is lower.

Poles in FB are zeros in 1/FB and zeros are poles: pFB1,2 and zFB1 in the example.
When 1/FB dominates, poles and zeros in 1/FB appear in ACL: pFB1and pFB2.

Example

1/FBAOL crossings remove and add poles and zeros in ACL: pCL1, pCL2, and pCL3,4.
ACL's phase follows whichever dominates: ACL's phase after pCL3,4 is AOL's 90.

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Power IC Design

D. Embedded Loops
Outer Loop:
Processes
external I/O's
sI and sO.
Embedded Loops:
Trace and identify outer loop and determine if it is negative feedback.
Trace and identify inner loops and determine if they are negative feedback.
Analyze inner loops first one at a time with outer loop open.
Analyze outer loop last using inner loop's two-port closed-loop model.
Analyze overall gain using outer loop's two-port closed-loop model.
ACL I's change with frequency Designers often ensure fIN CL(3dB) > fOUT OL(0dB).

E. Stability Criterion
With two poles below f0dB, phase shift is 180 at f0dB.

A CL f0dB = A CL fBW(CL) =

A OL
1+ A OLFB

=
A OL FB=1180 o

A OL
Uncontrolled
11

Stability Criterion: ALG should reach f0dB with less than 180 of phase shift.
Phase Margin PM: Margin of phase at f0dB to 180 before system becomes unstable.
Gain Margin GM: Margin of gain below 0 dB at f180.

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Power IC Design

F. Compensation
Objective:
Establish dominant low-frequency pole p1.
Approach:
Keep second pole p2 at or above f0dB
for 45 or more of phase margin.
Use in-phase zeros to offset poles.
Keep parasitic poles above 10f0dB
to keep phase margin from
avalanching near f0dB.
Since out-of-phase zeros invert signals
to close a non-inverting loop
at higher frequency, keep them above 10f0dB.

2.7. Simulations

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Power IC Design

A. Differential Amplifiers: Static Parameters

Bias:
Bias in unity-gain configuration when VIN is within its ICMR.
Monitor all node voltages and currents.
Ensure all transistors are in the
desired region of operation.
Quiescent Power PQ:
Bias the same way and monitor iVDD(vDD vSS).
Input-Referred Offset VOS:
Bias the same way VOS vIN vO.
Output Swing vO(MAX):
Fix vIC within its ICMR.
Sweep vIN slowly below and above vIC.

Monitor vO's swing limits.

Static Parameters
Input Common-Mode Range ICMR
Bias in unity-gain configuration.
Sweep vIN slowly.
Monitor vO and iTAIL.
ICMR when

vO vIN and

iTAIL is nearly unchanged.

Valid only when vO is within vO(MAX).

B. Dynamic Parameters
Dynamic Parameters
Open-Loop Gain AV: Bias in unity-gain
when VIN is within ICMR, nil feedback with LDC 1 kH
and CAC 1 kF, inject ac signal with vin 1, and monitor vo = vo/vin.

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Power IC Design

C. Small-Signal Response
Open the loop at a convenient location vB'vB.
Reconnect bias without closing the loop: With high LDC.
Reconstruct the load without altering the bias: With ZIN through high CACO.
Inject distinguishable small signals: Through high CACI.
Simulate: ALG = vb'/vb.

A CL0 = 180
E.g.: LDC = 1 kH and CAC's = 1 kF.

Convenient Location: At a gate because ZIN = CG and CACO can be a short.

Ultimate Stability Test: When disturbed with sudden wide-step changes in
the supply or load, loaded closed-loop system should recover after a delay.

Page 34