Power IC Design

Chapter 3. Bias Currents

3.1. Voltage Primitives
3.2. PTAT and CTAT Currents
3.3. Temperature Compensation
3.4. Startup
3.5. Frequency Compensation and Noise
3.6. Bandgap Current References
3.7. Precision

3.1. Voltage Primitives

Extract voltages and currents from predictable voltages.
Diode Voltage vD
vD
" vD %
V
V
i D = IS $ e t 1' ISe t
$
'
#
&

" i % KT " i %
v D Vt ln $$ D '' =
ln $$ D ''
# IS & q # IS &

Logarithm suppresses variations in diode current iD.

vD 0.60.7 V 2% at TROOM and falls 2.2 mV/C.
vD is accurate and consistent across close to five decades of current.
Breakdown Voltage vBD
Logarithm-like response suppresses variations in current iD.
vBD(ZENER) < 5 V 2% to 4% at TROOM and falls with temperature.
vBD(AVALANCHE) > 5 V 2% to 4% at TROOM and rises with temperature.
Typically, vBD 57 V and rises +2+4 mV/C vBD is high.

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Power IC Design

GateSource Voltage vGS in Strong Inversion

"W%
i DS 0.5$ ' K ' v GS v T
#L&

v GS = v T +

2i DS
v T + VDS(SAT)
K '(W/L)

Square root suppresses variations in drainsource current iDS.

vT 100150 mV, K' 20%, and both fall with temperature.
vGS 5% to 10% at TROOM Less accurate than diode.
GateSource Voltage vGS in Subthreshold
v

GS
"W%
i DS(SUB) $ ' IST e nVt
#L&

Where n = 1.53.

Logarithm suppresses variations in drainsource current iDS(SUB).

vGS is sensitive to noise energy in subthreshold.
Behavior of vGS is consistent across one or two decades of currents.

3.2.A. Proportional-to-Absolute-Temperature Currents

Definition: Rises with junction temperature vPTAT and iPTAT TJ
Popular Example: Thermal voltage Vt = KTJ
q
Features of Vt: Predictable, linear across temperature, consistent,
and good to cancel Vt effects gm BJT = iPTAT/Vt TJ/TJ
vPTAT Generation: Difference of two matched, but ratioed
diode or gatesource voltages in subthreshold is PTAT.
$i I '
$i A '
v D = v D1 v D2 Vt ln && D1 S2 )) = Vt ln && D1 D2 )) = v PTAT
I
i
% A D1i D2 (
% S1 D2 (

Where IS AD.

*
$W' , i DS1 & ) /
% L (2 /
=v
v GS = v GS1 v GS2 nVt ln ,
,$ W '
/ PTAT
, & ) i DS2 /
+ % L (1
.
Where IST W/L.

If currents, areas, and widthlength ratios match, ln term is constant.

iPTAT = vPTAT/RP RP should drift little across temperature TJ.
Poly-silicon resistances vary 20% RP requires adjustment Trimming.

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Power IC Design

i. Cross-Coupled Quad
Difference of four matched baseemitter voltages.
iR =

v BE v BE1 + v BE4 v BE3 v BE2 Vt # i1i 4 A 3A 2 & Vt

=
=
ln %
ln C2 D3 = i PTAT
(
RP
RP
R P %$ A1A 4i 3i 2 (' R P

iRB (vIN 2vBE)/RB

vIN(MIN) vRB + 2vBE (High)
Base-current error:
iB4 iB1 iO = iC4 iC2
iC2 = iPTAT iB2 < iPTAT
Voltage error: vCE1 vCE2 + vRP and vCE3 vCE4
PTAT for close to five decades of current.

ii. Latched BJT Cell

Latched BJT Cell: Difference of two matched baseemitter voltages.
Current mirror matches currents and positive feedback latches cell into PTAT state.
iR =

v BE Vt " i P1A P2 % Vt
=
ln $
ln C = i PTAT
'
RP
R P $# A P1i P2 '& R P

( )

vIN(MIN) VSD(SAT) + vBE

Base-current error:
iC1 iC2 and iC2 = iPTAT iB2 < iPTAT
Voltage error: vC1 vC2
PTAT for close to five decades of current.
Circuit is stable when:

iC1 iC2 vBE/RP = iPTAT

iC1 iC2 = 0 Bi-stable

Requires a startup circuit.

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Power IC Design

Error-Compensated BJT Cell

Replace diode connection with voltage-matching feedback loop.
vIN(MIN) Max{vSG + VCE(MIN), VSD(SAT) + vBE}
Low base-current error:
iCB1 2iCP iBB1 2iBP and iCP1 iCP2,
But iM2 = iPTAT + iBP1 > iPTAT
Low voltage error: RP' = RP, so
vSD1 vSD2 and vCE1 vCE2 vBEP1 vR
PTAT for close to five decades of current.
Bi-stable Requires a startup circuit.
Ensure + and feedback loops are stable.

iii. Latched MOS Cell

Latched MOS Cell: Difference of two matched gatesource voltages.
Current mirror matches currents and positive feedback latches cell into PTAT state.
In Subthreshold
iR =

v GS
RP

) #W& ,
+ i P1 % ( .
nV
$ L 'P2 . nVt
=
t ln +
ln C = i PTAT
. R
R P +# W &
P
+ % ( i P2 .
* $ L 'P1 -

( )

vIN(MIN) VSD(SAT) + vGS

No base-current error.
Voltage error: vD1 vD2
PTAT for maybe two decades of current.
To operate in subthreshold:
VDS(SAT) STRONG INV 50 mV

Bi-stable Requires a startup circuit.

Less linear across temperature than BJT.

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Power IC Design

iv. Latched Diode Cell

Latched Diode Cell: Difference of two matched diode voltages.
Current mirror matches currents and gate-coupled pair matches voltages.
vIN(MIN) VSD(SAT) + vGS + vD (High)
No base-current error.
Voltage error: vDM1 vDM2
PTAT for close to five decades of current.
Bi-stable Requires a startup circuit.

Error-Compensated Diode Cell: Difference of two matched diode voltages.

Amplifier diode-connects MM2
Mirror matches currents and feedback matches voltages.
vIN(MIN)
Max{VSD(SAT) + vD, vSG + vOA(MIN)}
No base-current error.
Low voltage error: vDM1 vDM2
PTAT for close to five decades of current.
Bi-stable Requires a startup circuit.
Ensure + and feedback loops are stable.

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Power IC Design

3.2. Complementary-to-Absolute-Temperature Currents

CTAT is the complement and counterpart to PTAT.
Definition: vCTAT and iCTAT fall with rising temperatures.
Popular Examples:
Diode voltage falls 2.2 mV/C.
Threshold voltage vT falls with temperature.
Transconductance parameter K' falls with temperature.
Feature of vCTAT: Good to cancel PTAT effects
For temperature independence sREF = sPTAT + sCTAT f(Temperature)
Benefit of Temperature-Independent Current:
Good to bias blocks, so quiescent power does not rise with temperature.
iCTAT Generation: Impress diode voltage vD across a resistor.
V !i $
v
i R = D = t ln ## D && = i CTAT
R C R C " IS %
vD is not perfectly linear with temperature iCTAT is not perfectly linear.

A. BJT and B. Diode Derived

Use negative feedback to sample and convert a diode voltage vD into a CTAT current.
Voltage-Sampled Diode

Current-Sampled BJT

MS diode
connects
QC.

AG diode
connects
M M.

"T" mixes/mirrors iCTAT and iS.

AG mixes/mirrors vD and vR.

MS series-samples iCTAT.

MM series-samples/mirrors iCTAT to iO.

MMMMO mirrors iCTAT to iO.

vIN(MIN) =

vIN(MIN) vSG + VDS(SAT) + vBE (High)

Page 6

Max{VSD(SAT) + vD, vSG + vOA(MIN)}

Power IC Design

3.3. Temperature Compensation

Approach: Use PTAT behavior to cancel CTAT component.
PTAT Primitive: Thermal voltage Vt is zero at 0 K and linear with temperature.
CTAT Primitive: Diode voltage vD is VBG 1.2 V at 0 K and 0.60.7 V at 27 C.

Taylor-series expansion of vD when iD = KXTX:

1
V v
T
v D VBG BG D(ROOM) TJ ( x ) Vt ln J
TROOM

TROOM

Where 4 and
x is from iD = KATJX.

vD has TJ0-, TJ1-, and TJ ln TJ terms vD is nonlinear with temperature.

Compensated vD leaves bandgap voltage VBG 1.2 V.

At TROOM, vD + vPTAT VBG vPTAT 1.2 V vD(ROOM) 0.50.6 V.
Compensated reference current iREF: vPTAT cancels vD's K1TJ1 term.
i REF = iCTAT + i PTAT =

( 1) Vt T V
v D v D v D Vt
V
+
=
+
ln (C) BG
ln T BG
RC RP RC RP
R C R C TROOM R C

Nonlinearity
If

i PTAT(ROOM) =

Vt(ROOM)
RP

( )

ln C

VBG v D(ROOM)

RC
RC

R C VBG v D(ROOM)

R P Vt(ROOM) ln C

( )

iD = iPTAT reduces vD's nonlinearity 1 in TJ1 corresponds to 1 in 1.

TJ ln TJ term causes curvature.
When TMIN is higher, optimal iREF' requires more iPTAT iREF' > iREF.

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Power IC Design

Example
Example: What resistances produce a temperature-compensated 5-A
reference current when the diode voltage at room temperature is 0.62 V
and the area ratio of the matched diodes is eight?
Solution:
R C VBG v D(ROOM)
1.2 0.62

= 10.73
R P Vt(ROOM) ln C
26m ln 8

( ) (

RC

) ()

VBG 1.2
=
= 240 k
i REF 5

"R %
" 1 %
R P R C $$ P '' = 240k $
' = 22.4 k
# 10.73 &
# RC &

After, simulate and adjust RP or RC until iREF flattens across temperature.

A. BJT Derived
PTAT-to-Reference Conversion
Use resistors across matching and mirrored vD's or vBE's
to pull matched and compensating iCTAT's from mirror.
Error-Compensated BJT Current Reference
QP1QP2RP establishes iPTAT and
RC1 and RC2 pull matched iCTAT's
from mirror
i REF

v BE v BE
+
= i CTAT + i PTAT
RC
RP

Base currents and transistor

voltages still match: iBB 2iBP,
vSD1 vSD2, and vCE1 vCE2

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Power IC Design

B. Diode Derived
Diode-Derived Current Reference

DP1DP2RP establishes iPTAT.

RC1RC2 pulls matched iCTAT's.

Error-Compensated Diode-Derived
Current Reference

i REF

v D v D
+
= i CTAT + i PTAT
RC RP

To relax vIN(MIN) and AG's ICMR, AG can mix fraction of vD across RC's.

3.4. Startup: A. Continuous

Challenge: Latched positive-feedback cells are bi-stable: iOUT = 0 or iBIAS.
Fix: Ensure positive-feedback currents are not 0, so iOUT can latch to iBIAS.
Continuous: Source/sink ITRICKLE continuously from/to positive-feedback node.
ITRICKLE is independent of circuit's state.
ITRICKLE dissipates power and can produce error iST << iPTAT
Use narrow- and long-channel JFETs or PFETs to generate ITRICKLE.

iC1 iC2 + iST Error

iC1 iC2 Low Error when iCB nears iC1.

Page 9

Power IC Design

Example
Example: What PMOS widthlength dimensions for a diode-connected
PFET can generate 250 nA at room temperature when impressing
2.5 V across the device and |vTP| = 0.5 V, KP' = 25 A/V2,
LMIN = 0.5 m, and WMIN = 2 m?
Solution:
ITRICKLE is low, so use minimum width W = WMIN = 2 m
PMOS is in saturation
"W%
iSD 0.5$ ' K P ' vSG v TP
#L&

" 0.5W %
L $$
'' K P ' vSG v TP
# iSD &

) 0.5 2 ,

) = ++ (250n)) ..(25))*(2.5)(0.5),- = 400 m

2

B. On Demand: i. Voltage Mode

On Demand: Source/sink ITRICKLE only when iPTAT nears zero.
Must sense the state of the circuit.
Voltage Mode: Engage ITRICKLE when vBE or vGS drops.
Example:
Differential pair QS1QS2 senses
and compares vBEP1 with vBESR.
AS1 > AS2 QS1QS2 favors vBEP1
QS2 is off when vBEP1 vBESR
QS2 sinks iST when vBEP1 << vBESR
In practice, iST is low, but not zero.

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Power IC Design

ii. Current Mode

On Demand
Current Mode: Engage ITRICKLE when iBIAS drops.
Example:
Mirror MM2MMB senses
and compares iPTAT with iLONG.
MS is off when iPTAT > iLONG
MS sinks iST when iPTAT < iLONG
CS keeps noise from triggering iST.
Design Notes: iLONG << iPTAT across temperature and process.
Connect CS to the positive supply vDD to
keep noise from affecting MS's vSG and iST.

3.5.A. Frequency Compensation

Latching cells employ positive feedback to latch iO to iBIAS.
and negative feedback to diode-connect the mirroring transistor.
Design: ALG+ > ALG when circuit is off.
Use iST to raise ALG+.
ALG > ALG+ when circuit is on.
Attenuate ALG+ with a

Example

low-pass filter RFCF.

Use RP to degenerate ALG+
or boost ALG.
Stabilize ALG with CC's.

CC
stabilizes
ALG.

RP
boosts
ALG.

Notes: More feedback loops raises the number of stable states Difficult to start.
Startup is often cumbersome and empirical Involves some trial and error.

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Power IC Design

B. Suppressing Supply Noise

Modern ICs integrate sensor-interface circuits, power amplifiers (PA), receivers,
data converters, power supplies, microprocessors, bias circuits, and more.
Power transistors inject substrate current that produces ground noise.
Dynamic loads pull power from the supply to produce supply and ground noise.
Power-Supply Rejection (PSR): Ability to suppress noise.
Noise Suppressors:
Separation of 50 m can suppress substrate noise 50 dB.
Shallow P+ guard rings can suppress substrate noise 10 dB.
Bias Noise Margin: IBIAS(MIN) >> iN.
Negative feedback opposes the effects of noise disturbances up to f0dB.
Differential pairs and transistors reject common-mode noise
in inputs because iO = (vP vN)GM and io = (vg/b vs/e)gm.
Common-mode capacitors couple source/emitter noise
to/from gate/base terminals for transistors to reject noise.

Example

RP boosts ALG.
$ 1 '$ 1 '
$ 1
'
i p1 *
A LG
,rB1 || ( roP1 + R P') || rdsM1 || &
+ R P ) g mP1
)/g mB1 &
) g mM2 &
sC
g
g
ii +
% mB2 (
% mP2
(
% C (.
A LG+

# 1 &,
# 1 &#
&
i m1 )
1
+rB1 || ( roP1 + R P') || rdsM1 || %
(.g mB1 %
(%
( g mM1
sC
g
1+
R
ii *
C
s
$ mB2 '$
$ C 'F F '

How much circuit favors ALG over ALG+.

&
A LG g mM2 # 1

+ R P (( g mP1 1+ R FC Fs
%%
A LG+ g mM1 $ g mP2
'

! 1
$
= ##
+ R P && g mP1 1+ R FC Fs
g
" mP2
%

CC couples emitter ground noise to QB1's base.

CF couples source supply noise to MM1's gate.
Negative feedback opposes the effects of noise.

Page 12

RFCF filters ALG+.

Power IC Design

3.6. Bandgap Current References: A. BJT Derived

Integrate baseemitter-derived CTAT currents into PTAT-current generators.
QP2QP1QB1MB2
diode-connects MM2, so
MM2MM1MB2MMO
mirrors currents and
sources both iPTAT and iCTAT.
RC1 and RC2 pull matched iCTAT's.
QP1QP2RP generates iPTAT.
QB1 and QP1QP2 pull
similar base currents.
v
v
i REF = i CTAT + i PTAT = D + D
RC RP

RFCF filters the + feedback loop.

CC stabilizes the feedback loop.
MLONG starts the circuit.

B. Diode Derived
Integrate diode-derived CTAT currents into PTAT-current generators.
AG mixes fraction of MM1MM2's
drain voltages, so
RC1 and RC2 pull matched iCTAT's.
AG diode-connects MM2, so
MM2MM1MMBMMO
mirrors currents and
sources both iPTAT and iCTAT.
DP1DP2RP generates iPTAT.
RFCF filters the + feedback loop.
i REF = i CTAT + i PTAT =

CC stabilizes the feedback loop.

v D v D
+
RC RP

MMBMLONGMS starts the circuit.

Page 13

Power IC Design

3.7. Precision: A. Tolerance and Drift

i REF = i CTAT + i PTAT =

v D v D VBG
+
=
R C R P R EQ

If RC and RP match, vCTAT and vPTAT shift proportionately

with RC and RP's 20% tolerance.
iREF's temperature drift is nearly independent of tolerance.
But since iREF 1/Resistance,
iREF drifts with RC and RP's temperature drift.
Choose low-drift resistors.
Absolute value of iREF shifts with RC and RP's 20% tolerance.
Bias current shifts 20% across fabrication corners.
If more precision is necessary,
adjust RC and RP after fabrication (i.e., trim).

B. Layout
Mismatch between non-degenerated transistors offset iREF.
Match

PTAT-generating pair DP1DP2, QP1QP2, or MP1MP2,

PTAT Resistors RP and RPTAT,
Mirroring Devices QM1QM2, MM1MM2, or RL1RL2, and
Non-degenerated transistors in diode-connecting loop.

The effect of mismatch between degenerated transistors is low in iREF.

Cascode transistors need not match as well.
Best-Matched Layout Cross-coupled, common centroid, same orientation,
compact, low spread, and
dummy devices.
Typical Layout Strategies
for the PTAT-generating pair:
A. 8 around 1 Compact.
B. 1 or 2 on either side of 1.

Page 14

Power IC Design

Chapter 4. Voltage References

4.1. Bandgap References
4.2. Power-Supply Rejection
4.3. Precision
4.4. Trim
4.5. Curvature Correction

4.1.A. Current-Mode Bandgap

Balanced PTAT and CTAT currents flow into a resistor.

"V %
"v
v %
v REF = i CTAT + i PTAT R O = $$ D + D '' R O $$ BG '' R O
# RC RP &
# R EQ &
RO should match RC and RP.

CO shunts noise coupled and injected.

vREF can be a fraction of the bandgap voltage VBG.
Regulating current mode's iBG helps reject supply noise,
but does not help shunt coupled noise.
Buffering vREF with unity-gain amplifier helps shunt noise,
except amplifier's input-referred offset VOS degrades accuracy.

Page 15

Power IC Design

i. BJT Implementation
QP1, QB1, and MB2 diode-connect MM2, so
MM1, MM2, and MMO
mirror iREF's iPTAT + iCTAT.
QP1, QP2, and RP
generate iPTAT.
RC1 and RC2 establish iCTAT.
RP' keeps vCEP1 vCEP2.
RO converts iREF to vREF.
MLONG's iST ensures iPTAT 0.

i PTAT =

CO shunts noise coupled and injected.

RF and CF filter the positive feedback path.

v BEP1 v BEP2 Vt
=
ln C
RP
RP
i CTAT =

v BEB1 v BEP1
=
R C1
R C2

Note iST + iCB1 2iPTAT and mirror voltages and base currents match.

B. Voltage-Mode Bandgap
Stack PTAT and diode voltages.

vREF = iPTATRP + vD iPTATRPTAT + vD = vPTAT + vCTAT VBG.

RPTAT should match iPTAT's RP.
CO shunts noise coupled and injected.
vREF is roughly 1.2 V.
Regulating vREF or vPTAT helps shunt noise without degrading accuracy,
if vREF accounts for amplifier AV's offset VOS drift AV is in vREF.

Page 16

Power IC Design

i. BJT Implementation
QP1, QB1, and MB2 diode-connect MM2, so
MM1, MM2, and MB2 mirror iPTAT.
QP1, QP2, and RP generate iPTAT.
RP' matches vCEP1 and vCEP2.
MLONG ensures iPTAT 0.
CO shunts noise coupled and injected.
MB2, MM1, and MM2's 4iPTAT
into RPTAT establishes vPTAT.
QP1's vBEP1 establishes vD.
RF and CF filter ALG+.
i PTAT =

Notes: iST + iCB1 2iPTAT.

Mirror voltages and base currents match.
Reacting to noise in vREF alters iPTAT.

v BEP1 v BEP2 Vt
=
ln C
RP
RP

v REF = 4i PTAT R PTAT + v BEP1

ii. Diode Implementation

AG diode-connects MM2, so
MM1 and MM2 mirror iPTAT.
AG impresses vDP1 on RP and DP2, so
Mirror voltages match and
DP1, DP2, and RP generate iPTAT.
2iPTAT into RPTAT establishes vPTAT.
DP1 establishes vD.
AG shunt-samples vREF.
RFCF filters ALG+.
CO shunts noise coupled and injected.
Reacting to noise in vREF alters iPTAT.

Page 17

i PTAT =

v DP1 v DP2 Vt
=
ln C
RP
RP

v REF = 2i PTAT R PTAT + v DP1

Power IC Design

iii. Shunt Feedback

To incorporate shunt feedback, modify diode-connecting loop to drive vREF
with a source or an emitter iPTAT is less sensitive to loop reactions.
AV impresses vRL2 on vRL1, so
RL1 and RL2 mirror iPTAT.
QP1, QP2, and RP generate iPTAT.
QP1 shunt-samples vREF.
2iPTAT into RPTAT establishes vPTAT.
QP1's vBEP1 establishes vD.
RP' matches vCEP1 and vCEP2.
V
v
v
i PTAT = BEP1 BEP2 = t ln C
RP
RP
v REF = 2i PTAT R PTAT + v BEP1

AV sources base currents, so

no base-current error.
CO shunts noise coupled and injected.

Diode-Loop Implementation
AV impresses vRL2 on vRL1, so
RL1 and RL2 mirror iPTAT.
QP1, QP2, and RP generate iPTAT.
QP1 shunt-samples vREF.
2iPTAT into RPTAT
establishes vPTAT.
QP1's vBEP1
establishes vD.
RF and CF filter ALG+.
RP' matches vCEP1 and vCEP2.

RBP1 matches RIF's vRIF.

AV sources base currents.

RP degenerates ALG+ and MD1,2 series-mixes vRL's.

RMFCMF and RIFCIF filter ALG+.

CO shunts noise coupled and injected.

Page 18

Power IC Design

Differential-Pair Implementation
A differential pair QP1QP2 can also implement a loop that
impresses vBE across an external RP to generate iPTAT.
QP1, QP2, and RP generate iPTAT.
RF and CF filter ALG+.
RB matches RF's vRF.
CO shunts noise coupled and injected.
RP's iPTAT through RP and RPTAT
establishes vPTAT.
DC's vDC establishes vD.
iBIAS ensures currents are not 0 Starts vREF.
iPTAT is less sensitive to loop reactions.

i PTAT =

v EBP1 v EBP2 Vt
=
ln C
RP
RP

Loop shunts coupled noise.

v REF = i PTAT R P + R PTAT + v D

iv. Sub-Bandgap: Shunt-Feedback Implementation

Since a voltage divider reduces vD, vCTAT + vPTAT can be a fraction of VBG.
Feedback loop ensures RP conducts iPTAT, so RP is like a current source.

vO =

vDRO
+ i PTAT ( R O || R C )
RC + RO

i PTAT =

v EBP1 v EBP2 Vt
=
ln C
RP
RP

v R
V R
v REF i PTAT "#R P + ( R O || R C )$% + D O BG O
RC + RO RC + RO

Page 19

Power IC Design

4.2. Power-Supply Rejection

A. Basic Concepts
Power-Supply Rejection (PSR) is the ability to suppress power-supply noise.
Inability to amplify power-supply noise.
PSR is the complement of supply gain AIN.
Line Regulation (LNR) is how vO varies with steady-state changes in vIN.
PSR

v
v
1
= IN in
A IN v O v o

LNR

VO v O

VIN v IN

Low Freq

= A IN0 =

1
PSR 0

PSR Model Voltage Divider

Supply impedance ZT couples noise.
Ground impedance ZB shunts noise.
Shunt feedback ZSH FB opposes the effects of noise.
Raise ZT, lower ZB, and raise the gain and bandwidth of the feedback loop.

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Power IC Design

B. Improving PSR
Current-mode bandgaps: Regulate iREF Raise ZT.
Voltage-mode bandgaps: Shunt-feedback loops that do not alter iPTAT.
Use shunt feedback to shunt noise and reduce ZB.
Cascode supply-connected current-sourcing transistors.
Filter the input supply vIN:
RC shunts high-frequency ripples.
Linear pre-regulator rejects low-frequency ripples.

PSR

v o " v in' %" v o % " 1 %" 1 %

= $ '$ ' = $
'$
' = PSR PRE PSR REF
v in # v in &# v in' & # A PRE &# A REF &

C. Pre-Regulators: i. Unregulated and ii. Regulated

Pre-regulated supply vIN' should accommodate vREF's
headroom vIN(MIN) across process and temperature.
Uncompensated
and Unregulated

vIN' = 3vD
Falls with temperature.

Temperature-Compensated and Regulated

vIN' = iPTAT(RP + RPTAT) + 2vD

Can rise or fall with temperature.

Page 21

Power IC Design

Low Voltage
Self-contained, temperature-compensated, and regulated pre-regulator.
QP1, QP2, and RP generate iPTAT.
RF and CF filter ALG+.
RB matches RF's vRF.
Startup: MS pulls iST when
MMS's iMS < MLONG's iLONG.
CS couples supply noise to
reduce noise in MS's vSG.
QP3 mirrors QP1's iPTAT, so
vIN' = 2vD + iPTATRPTAT.
Remove or insert diodes and adjust RPTAT

i PTAT =

to define voltage level and temperature drift.

4.3. Precision

Page 22

v BEP1 v BEP2 Vt
=
ln C
RP
RP

Power IC Design

A. Sources of Errors
First-Order Core: PTAT Generator vBE loop.
Current Mirror With or without feedback amplifier.
Summer Current mode or voltage mode.
Error Sources:
Mismatch of resistors, transistors, and mirror.
Tolerance of vBE and resistors.
Error Analysis: Deviations from ideal produce vREF.
Mismatched currents iC/D appear as vBE/GS in vREF.
QP1QP2 impresses vBE/GS across RP to produce vPTAT in vREF.
vREF = vREF(IDEAL) vREF(ERR) = vBE + vPTAT.

!i
$
!R
$
v REF = v BE + v PTAT = Vt ln ## PTAT && + 2Vt ln C ## PTAT &&
I
R
" P %
" S %

( )

1% Resistor Mismatch (R/R):

No effect in iPTAT No effect in vBE.
vPTAT = 2Vtln(C)(R/R) T1 and small Trimmable with RPTAT.
20% Resistor Tolerance R:
No effect in R/R No effect in vPTAT.
vBE = Vtln(RERR/R) T1 and small Trimmable with RPTAT.
Resistor's Drift over Temperature:
No effect in R/R No effect in vPTAT.
vBE = Vtln(RTC/R) = Nonlinear, but small Not trimmable.

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Power IC Design

5% Current Mismatch iP/M between PTAT and Mirror Transistors.

Effect in vBE and iPTAT.
vBE/GS = iC/D/gm = (iC/D/iC)Vt for BJT pair QP1,2.
= (iC/D/iC)nVt for MOSFET pair MP1,2.
vPTAT = vBE/GS(R1/RP) = (iC/D/iC)Vt(R1/RP) for BJT pair QP1,2.
= (iC/D/iC)nVt(R1/RP) for MOSFET pair MP1,2.
vBE/GS + vPTAT T1 and high Trimmable with RPTAT.
0.5-V Mirror-Voltage Mismatch vC/D vC/D and VA can vary with temp.:
iC/D = vC/D/rds/o = iC/DvC/D/VA vBE/GS = (iC/D/iC)Vt and
vPTAT = (iC/D/iC)Vt(R1/RP) Nonlinear, but small Not trimmable.

Package-Induced Offset:
Thermal Coefficient of Expansion (TCoE): TCoEPackagae >> TCoESilicon Die.
Plastic melts at 170 C and undisturbed die remains relatively flat.
As temperature T rises, plastic contracts and bends die.
Add fillers to reduce TCoEPackage and avoid cracking die.
Die's electrical properties change with T Piezo effects.
Die-wide stress bends die and produces a variable systemic offset VOS(S).
Die is unstressed at 170 C Die un-stresses with T.
VOS(S) 26 mV T1 and small Trimmable.
Fillers produce localized random stress fields VOS*.
Stressed
Mean

Page 24

Less
Stressed

Power IC Design

B. Typical Error Profile

Error Source

Untrimmed Error

vREF

Resistor Mismatch

1%

6 mV

Resistor Tolerance
Drift of
Poly-silicon Resistors
PTAT-Pair I Mismatch
Voltage Mismatch (VA = 50 V)

20%
TC1 = 500/C
TC2 = 200/C2
5%
0.5 V

5 mV

Current-Mirror I Mismatch

5%

15 mV

vBE Tolerance

2%

24 mV

0.0 mV
15 mV
3 mV

Total vREF (RMS Sum)

33 mV

Package Shift

12 mV

Total vREF (RMS Sum)

35 mV

Full-scale trim range should cover 6070 mV 5%6% of VBG.

Wafer adjustments cannot cancel package effects.
Post-package adjustments require more silicon area and additional test time.

C. Mismatch-Error Reduction
Dynamic Element Matching:
Circulate pair or bank of transistors.
All transistors occupy all positions.
Average offset between positions is zero.
Drawbacks:
Changing positions generates switching noise.
Switching network occupies silicon area.
Apply only to critical match-sensitive transistors.

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Power IC Design

Startup Calibration: "Survivor" Scheme

Sample and compare the offsets of two transistor pairs.
Discard loser and replace loser with another pair.
Repeat and ripple winner until all pairs are tested.
The winner is the best-matched pair.

Challenge: Untrimmed comparator CPERR must be accurate.

Startup Comparator
Reduce VOS with dynamic element matching.
Generates noise only during startup,
when the system is off.
Short the inputs of a summing comparator CPSUM.
Use latch to store CPSUM's output vO.
Flip one differential pair:
If vO trips, flipped pair's VOS dominates.
XOR transitions Discard flipped pair.
If vO does not trip, flipped pair's VOS is lower.
XOR does not transition.
Discard un-flipped pair.
Results: Can select a 2-mV pair from 22-mV pairs.
Drawback: Controller and transistor bank can occupy substantial silicon area.

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Power IC Design

D. Package-Shift Reduction
Systemic Offset: Model in simulations and include in design Lower vPTAT.
Random Offset: Buffer the effect of fillers with mechanically compliant layers.
Examples: Nitride layer, uniform metal planes, and
post-fabrication layers, which add cost.

Planarized Die:

Planarized Die and

16%18% lower vREF*.

15-m Copper Layer:

35% lower vREF*.

Ceramic packages stress dies substantially less, but they cost more.

4.4. Trim

Page 27

Power IC Design

A. Trim Basics
vREF = vPTAT + vD KPTATT + (VBG KCTATT) VBG if KPTAT = KCTAT.
Since VBG 1.2 V and vD(ROOM) 0.65 V vPTAT 0.55 V.
Since vPTAT = 0 at 0 K, only one more point sets correcting slope.
All T1 errors can be trimmed at one temperature At TROOM.
First-order PTAT compensation cancels the first-order T1 term only.
Higher-order terms in T ln T produces curvature in vREF.
vREF's fractional temperature coefficient TC at TMID is zero.
Note TROOM is not always TMID.

" 1 %" v %
TC $$
''$ REF '
# v REF &# T &

B. Trim Process
Adjust vPTAT by trimming RPTAT.
vREF's TC at TMID rises with RPTAT.
TC at RPTAT(MAX) is TCMAX.
TC at RPTAT(MIN) is TCMIN.
TC rises linearly with trimmed vREF.
0-TC vREF(MID) setting is a linear extrapolation of TCMIN and TCMAX.
Extrapolate vREF(ROOM) target from vREF(MID) setting.
Typical commercial range is 0 to 85 C.
Extended commercial range can be 40 to 125 C.
TMID = 42.5 C > TROOM and VMID(0TC) > VTARGET(ROOM).
Typical 3 TC is 20100 ppm/C 315 mV across 125 C at 1.2 V.

Page 28

Power IC Design

C. Trim Methods
Zener Zap: Zener diodes short with high reverse voltages.
Fusible Links: Poly-silicon strips break with high currents.
Laser Trim: A laser beam cuts poly-silicon strips into desired shape.
E-EP-ROM: Floating gates receive/lose charge with high on-chip voltages.
Trimming Methods

Normally
Open

Zener Zap
At
Wafer

PostPackage

Normally
Closed

Resolution

Stress
on IC

Cost

Bit Defined

High

Low

Fusible
Link

Bit Defined

Moderate

Low

Laser Trim

Laser Defined

Low

Highest

Fusible
Link

Bit Defined

Highest

Moderate

Bit Defined

Low

High

EEPROM

On-chip EEPROM and fusible poly-silicon links are popular.

Zapping packaged fusible links is not as reliable Possible fuse re-growth.

D. Fusible-Link Circuit
Poly-Silicon Fuses: 200- fuses break to M's with 5 V and 25 mA.
200- fuses and 15-k RTG drop mV's, so FETs short trim resistors.
Bias currents raise bit lines
after fuses open.
Trim ground and RTG steer fuse
current away from the substrate.
Wide traces carry
breakdown current.
Diodes block reverse currents into bias
currents when vTRIM > vIN and vIN = 0 V.
RDS LSB(HOT) << RLSB, so keep ladder near ground for maximum gate drive.

Page 29

Power IC Design

E. Design Process
Conceptualize circuit.
Simulate functionality: Steady state, startup, stability, response time, etc.
Simulate temperature drift:
Monte-Carlo simulations under nominal conditions.
Trim every corner when using Monte-Carlo simulations
because untrimmed cases are unrealistic worst cases.
Determine worst-case trim range and expand for characterization.
Temperature models are imperfect, so measure and characterize drift.
Determine optimum vTARGET (i.e., vREF(ROOM) setting with lowest temperature drift)
before packaging die for low cost, or after if test time allows it for high accuracy.
Incorporate results into next design cycle: Re-center trim and reduce trim range.
Trim to vTARGET at TROOM.

F. Measurements
Temperature Considerations
Soak Time tSOAK: Variations vREF have a slow time constant.
Allow sufficient soak time tSOAK for vREF to settle to its final value.
Thermal Hysteresis vHYS:
vREF for TRISE may not match vREF for TFALL.
Raise soak time tSOAK to ensure tSOAK is not the problem.
Temperature Coefficient TC: Include all statistical effects.
Box Method:
TC REF

$v
v REF(3MIN) '
&& REF(3MAX)
))
v REF(MEAN) %
TMAX TMIN
(
1

Thermal Stability: Thermal feedback loop may exist.

E.g.: High power Temperature rises System shuts Die cools.
System restarts Power again rises Cycle repeats.

Page 30

Power IC Design

4.5. Curvature Correction

A. Basic Principles
First-Order Reference: vPTAT cancels vD's T1 term.
T ln T produces a curvature in vREF.
Second-Order Reference: Parabolic vPTAT2 cancels vD's T2 term.
At low temperatures, T2 term disappears vREF is first order.
At higher temperatures, T2 term over-compensates vREF curves up.
Curvature Correction: vPTAT2 and/or other components offset vD's T ln T term.
v D VBG
"V v
%
D(ROOM)
'' T1
$$ BG
T
#
&
ROOM
# T &
x Vt ln %%
((
$ TROOM '

Page 31

Power IC Design

B. Parabolic Correction: i. BJT Example

Current Mode:
Generate a nonlinear current iNL.
Superimpose iNL on PTAT resistor stack.
iPTAT(RPTAT + RPTAT2) + iNLRPTAT2 = vPTAT + vNL.
!i i $
v BE1 + v BE2 = Vt ln ## Q1 Q2 &&
Parabolic Correction:
" IS IS %
QP mirrors Q1's iPTAT.
RC's iCTAT compensates QP2's 0.5iPTAT.
iQ3 iCTAT + 0.5iPTAT i0TC.
i0TC iPTAT near TROOM.
Q1, Q2, Q3, and Q4 close a vBE loop.
iQ1iQ2 = iPTAT2 iQ3iQ4 i0TCiQ4 iQ4 iPTAT2.
Since i0TC iPTAT near TROOM, Q14's current densities are similar.

ii. MOS-in-Triode Example

MS, MMB, and MLONG start the circuit and CS keeps noise from engaging iST.
MM1, MM2, MM3, and MMO mirror MNL's iNL.
MP1 and MP2 are in
sub-threshold.
MP1 and MP2 impress vGS
across MNL's RDS NL.
MNL is in triode
i NL =

v GS
nVt
v

ln C = PTAT
R DS NL R DS NL
R DS NL

R DS.NL

( L)

K' W

1
NL

(v

GS.NL

v TN

( L)

K' W

i NL v PTAT i NL

1
NL

Page 32

VDS.NL(SAT)

( L)

2i NL K ' W

iNL vPTAT2.

NL

1
i NL

Power IC Design

C. Piecewise-Linear Correction
At low temperatures, below transitional point TTRAN, iCTAT overwhelms iPTAT.
MCO pulls vNL toward vDD, MMO's iNL 0, and vREF is first order to TTRAN.
At high temperatures, above TTRAN, MCO's iCTAT < iPTAT.
MNL sources iNL = iPTAT iCTAT PTAT, so vREF is first order after TTRAN.

More iNL segments with staggered TTRAN's can reduce vREF further.

D. T ln T Correction
QP and Q0TC impress diode difference vBE across RNL.
vBE with PTAT and 0-TC currents IPTAT and I0TC generate T ln T behavior.
i NL =

'
$I
v BE v BEP v BE 0 TC
V
=
t ln & PTAT ) T ln T
R NL
R NL
R NL % I 0TC (

MFB1MFB2 and MFBMM1MM2 implement inverting feedback loops

that ensure iNL flows through RNL.

Page 33

Power IC Design

E. Higher-Order Correction
T ln TX Voltage: vBE offsets vBG1's T ln T term:
vREF = vBG1 vBEC + vBEP where
#
# I
&
&
I PTAT
v BE = Vt ln %%
(( T ln %% PTAT (( T ln +TC
$ I CTAT I PTAT '
$ K X I CTAT '

Quasi-Exact Correction:
Since "1" in vD's " 1" corresponds
to iD's PTAT dependence T1,
AvD(iPTAT) BvD(i0TC) removes
T ln T term when

A
.
AB

E.g.: If = 4, A 4, and B 3.
v REF = Av D(iPTAT) Bv D(i0TC) + v PTAT

VT1T1
(
+
T
VBG VT1T1 $%A 1 B&' Vt ln **
-- + v PTAT VBG
) TRM ,

F. Parasitic Correction
Use "parasitic" effects to correct nonlinearity.
Base Current: Add iBP1RB to vBG1.
Base-Width Modulation: Adjust iPTATRP'
to mismatch collectoremitter voltages vCE's.
High-TC Resistor RHTC: Add iPTATRHTC to vBG1.
!R $
i PTAT R HTC = Vt ## HTC && ln (C) T 2
" RP %
Trimming at more than one temperature is too costly.
Do not trim curvature-correcting component.
Systemic correction reduces 20100-ppm/C 3 first-order variation.
But randomness limits improvement to 540 ppm/C.
Parasitic correction requires less power and silicon area.
BJT PTAT pair suppresses offsets more than MOSFETs.

Page 34