Sequential circuits

The main components of this kind of circuits are shown in the figure.

As you might recognize the output of this circuit doesnt depend only on
its input but rather on value coming from within the circuit through the
feedback circuit. This value called the state of the circuit.
Ex. The clock increments its value by one when each pulse arrives, but if
I asked you what is the value of the clock when the input (i.e. pulse)
arrives, you cant answer without knowing the current state of the clock,
so if you know the holding value in the clock (say 10), then your answer
will be 11. In this example, your answer will depend on the current value
of the clock which is called the state of the circuit.
Summary :
Output depends on current as well as past inputs
Depends on the history
Have memory property
Sequential circuit consists of
Combinational circuit
Feedback circuit
Past input is encoded into a set of state variables
Uses feedback (to feed the state variables)
Simple feedback
Uses flip flops

 Clock serves two distinct purposes

For synchronization purposes, which makes group of
components change their state according to predefined
policy.
For timing information
By adjusting the ON, and OFF periods
Propagation delay: any electronic component need some time to
find its output react to its input value, this time is called delay.
Clock pulses are generated by special electronic circuit called Oscillator.
Inside the computer these pulses are generated by crystal oscillator, to
guarantee pulses at fixed frequency (highly accurate).
Latches
Latches are used to remember a bit 0 or 1.
Many types of latches exist such as:
1. S-R Flip/Flop.
2. D- Flip/Flop.

3. J/K Flip/Flop.
S-R Flip/Flop

The circuit, the symbol and the transition table of the S/R F/F are shown
in the above figure. Applying 0 for both of S and R will cause the flip
flop to keep its state, while applying 0 to S and 1 to R will make Q=0
(Reset) and applying 1 to S and 0 to R will make Q=1 (Set). Applying 1
to both of the S and R is not allowed, since it causes both of Q and Q to
have a value of 0 (on the contrary of the basic principle of being Q is the
complement of Q), then, if we applied 0 for both of R and S, it will cause
the flip Flop to oscillate (change from 0 and 1 and from 1 to 0
indefinitely).
A modified version of the S-R Flip Flop called Clocked Flip-Flop is
shown in the figure down here. This circuit guarantees that the change of
the F/F state will take place during the +ve half cycle of the clock).

Another version called master-slave F/F allows the state change of the
F/F at the rising edge of the clock (transition from 0 to 1 only, and
sometimes we call it the +ve edge) or at the falling edge (transition from
1 to 0 only, and sometimes we call it the ve edge). Traditionally, if the
F/F makes its change at the falling edge or the negative half cycle, a
circle will be marked on the clock line to indicate that on the F/F symbol
(see the figure down here).

Positive half cycleNegative half cyclePositive edgeNegative edge

 D- Flip/Flop
Connecting the S/R in the way shown in the figure blow here will lead to
D- F/F, which function only in two states of the S-R (since inverter is
connected between S and R as shown in the figure).

J/K Flip/Flop
JKQn+100Qn0101011
1Qn
(b) Transition Table

The J/K Flip Flop working as the S-R Flip Flop in the first three rows in
the transition table of the S/R and the last row (i.e. when both S and R are
1s) if both of J and K are set to 1, this will cause changing the state of the
J/K F/F.

Counters
Used inside the computer to synchronize the different operations and to guarantee the
correct sequence of execution. There are synchronous and ripple counters. In the
synchronous central clock is used to pulse all Flip Flops, while the ripple counter
isnt.
Synchronous counter can use any type of the F/Fs, all what we need to design counter
is to:
1. Determine the counting sequence.
2. Calculating the required number of the F/Fs (n). Consider that the maximum
value that counter will reach is m, now n is calculated according to the
equation 2n m.

3. Build the transition table for the counter and hence derive the design
equations.
4. Draw and implement the circuit.
But first we have to know how to derive the different F/Fs to get in the required state.
The next table shows how to derive the J/K F/F from the state it was at time t, to its
next state required at t+1. The table enumerates all the possibilities, and determines
the required value for J and K to make the required transition.
QtQt+1operationJKGeneral valuesJK00Reset010dNo
Change0001Set101dChange1110Reset01d1Change1111No Change00d0Reset10

Similarly, if S/R is to be used in the counter design, then the following table has to be
used to determine the value of S and R required for deriving the S/R F/F from its
current state to the next required state.
QtQt+1operationSRGeneral valuesSR00No
Change000dReset0101Set101010Reset010111No Change00d0Reset10

To show how counter is designed we will consider the counter which count in the
sequence 0 to 7 and repeat (design using J/K F/F.
1. The counting sequence is 0, 1, 2, 3, 4, 5, 6, 7, 0 .
2. Since the greatest value the counter counts is 7, then the required no. of F/F
(n), is calculated from equation 2n 7, therefore n= 3 (i.e. 3 J/K F/F are
required).

3. Transition Table is as follow:

Current State
Q2 Q1 Q0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1

Next State
Q2+ Q1+ Q0+
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
0
0
0

J0

K0

J1

K1

J2

K2

1
d
1
d
1
d
1
d

d
1
d
1
d
1
d
1

0
1
d
d
0
1
d
d

d
d
0
1
d
d
0
1

0
0
0
1
d
d
d
d

d
d
d
d
0
0
0
1

Q
Q
2 Q00011110011111dddd
01
J0= 1

Q
Q
2 Q000111100dddd11111
01
K0= 1

Q
Q
2 Q0001111000dd011dd1
01
J1= Q0

Q
Q
2 Q000111100d00d1d11d
01
K1= Q0

Q
Q
2 Q00011110000dd101dd
01
J2= Q0Q1

Q
Q
2 Q000111100dd001dd10
01
K2= Q0Q1

4. The implementation (N.B. in the figure below the F/F on the Left side
represents Q0).

Now let us repeat the design using S-R F/F. we have to follow the same steps as those
used with J/K with one exception which is using S-R F/F transition table instead of
the J/K F/F.
1. The counting sequence is 0, 1, 2, 3, 4, 5, 6, 7, 0 .
2. Since the greatest value the counter counts is 7, then the required no. of F/F
(n), is calculated from equation 2n 7, therefore n= 3 (i.e. 3 S/R F/F are
required).

3. Transition Table is as follow:

Current State
Q2 Q1 Q0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1

Next State
Q2+ Q1+ Q0+
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
0
0
0

S0

R0

R1

K1

S2

R2

1
0
1
0
1
0
1
0

0
1
0
1
0
1
0
1

0
1
d
0
0
1
d
0

d
0
0
1
d
0
0
1

0
0
0
1
d
d
d
0

d
d
d
0
0
0
0
1

Q
Q
2 Q000111100111110000
01
S0= Q0

Q
Q
2 Q000111100000011111
01
R0= Q0

Q
Q
2 Q0001111000dd011001
01
S1= Q0 Q1

Q
Q
2 Q000111100d00d10110
01
R1= Q0Q1

Q
Q
2 Q00011110000dd1010d
01
S2= Q0Q1Q2

Q
Q
2 Q000111100dd001d010
01
R2= Q0Q1Q2

4. The implementation (N.B. in the figure below the F/F on the Left side
represents Q0).

As you might see the design using J/K F/F leads to simpler circuit, this because the
many ds existed in the J/K F/F transition table.

Shift Register
Registers, in general, consist of set of Flip Flops to store values temporarily to
perform operations. They are accessed faster than memory. Normal sizes of registers
are 8 bits, 16 bits, 32 bits or 64 bits. The register to store value of 8-bits it must have
8- Flip Flops.
Shift register beside its ability to store values; it can shift the value it holds to the left
or to the right one bit at time (the shift take place at the clock edge, if the proper
control signal is set). Normally, each shift register is equipped with two control
signals (we indicate them as Shift Left L and Shift Right R) and it may have another
control signals such that needed to load the register with value on its inputs.
The Question Now, What are the values that affect the value of Qn?
The answer is quite simple, since each bit in the shift register takes the value of one of
the neighboring bits which, in this case, Qn-1 and Qn+1 . Qn will assign one of these two
values depending on the value of L and R.
The accepted values of L and R are 00, which mean no shift at all, 01 to indicate shift
to right and 10 to indicate shift to left, while 11 is not allowed (because it has no
meaning).
J

Qn-1

Clk

Qn

Clk

Qn-1

Qn+1

Clk

K
Qn
K
Qn+1
I will depict the Karnough map that assign the value of Q n according to the values of
Qn-1, Qn+1, L and R

LR

Q
n+1 Q
000111100001011011100011
Qn
n-1

No Change No Change

Dont care Dont care

The first row: Qn have to keep its value without change since the value of LR=00.
The second row: the value of LR=01 (shift right), Q n takes the value of Qn-1. Note that
in all cells the Qn assigned the corresponding value of Qn-1.
The third row: the value of LR=11 and this is not possible, so the value for Q n is dont
care.
The 4th row: the value of LR=10 (shift left), Qn takes the value of Qn+1. Note that in
all cells the Qn assigned the corresponding value of Qn+1.
To let Qn assigns the values indicated in the above map, we assign its corresponding J n
and Kn as follow:

Q
0001111000000001011011dddd100011
n+1 Q
-1
JLRn = R nQ
+ L Qn+1
n-1

Q
0001111000000001100111dddd101100
n+1 Q
n-1
K
+ L Qn+1
LRn = R Q
n-1

Qn-1

Clk

Qn

Qn+1

Clk

Clk

Qn-1

Qn

Qn+1

Each flip flop in the shift register will have its J and K implemented by logical
expression which is function of the next Q, previous Q , L and R.