CMOS VLSI Design

Sem. VI EC
Questioners
Week-4
1. Why Aluminum is not used as a Gate in MOSFET Device?
2. Give the significant use of following material in processing line of CMOS.
i) Refractory Metals, ii) Silicides, iii) Copper, iv) Silicon Nitride
3. Why CMP technique is used?
4. Explain following terms: i) beading effect, ii)Test Sites, iii) Registration Targets, iv)
Pellicle
5. Why field oxide growth is employ as a starting step of MOS process flow?
6. What do you mean by self- aligned gate process?
7. What are the variations apply in Basic CMOS process flow? Why?
8. How to increase reliability of MOSFET device during fabrication process?
9. How Cu patterning technique is differing from Al patterning technique?
10. What are Lambda design rules? What is the disadvantage of it?
11. What are the misalignment induced defects occur in CMOS process flow? What are the
remedies against them?
12. List out the physical limitations of processing line and explain each.