CMOS VLSI Design

Sem. VI EC
Week 3: Questioners
Q.1 Do the comparison of pFET and nFET with respect to two different V-I characteristic.
Q.2 How does the scaling effect the channel resistance of FET? How that can be compensated?
Q.3 How is the power dissipation affected by scaling of FET device?
Q.4 Why threshold voltages of FET device are affected by scaling L and W individually?
Q.5 Why small FET devices are frequently enter into the velocity saturation?
Q.6 Show that the value of transit time is decreased by decreasing the channel length.
Q.7 What are the types of growing the silicon dioxide(SiO2) layer?
Q.8 Where CVD oxide process is apply in process line?
Q.9 Where Silicon Nitride is used in process line and Why?
Q.10What is electro migration problem? What are the remedies against it?