HW problems for Hu’s Chap.

1. For a planar (bulk) n+poly n-channel MOSFET, with the gate oxide thickness tox = 20A and p-type
substrate concentration of 1E18 (1/cm3), what is the long-channel sub-threshold swing (SS) for this
device?

2. What is the long-channel Vt for the above device ?

3. Assume Vt is equal to sub-threshold current of ID=10nA per device width, what is the IOFF (at VG=0) for
this device ?

4. Explain why Vt-roll off (a key indicator of short-channel effect) is aggravated by higher VD .

5. What are the three key device factors affecting SCE (short channel effect) ?

6. For Fig.7-8, explain why the SiO2 gate current density increases rapidly for decreasing tox , also explain
why using High-K dielectric we can reduce this gate leakage.

7. What are the two major benefits of using FinFET device structure (compared to planar MOSFET) ?
Explain why.