15 A Synchronous Machine PDF

Asynchronous Machine
Types of Asynchronous Sequential Machines
Pulse-Mode
Pulse will not occur simultaneously on two or more inputs

Memory Element transitions are initiated by input pulses
Input variables are used only in the uncomplemented or
complemented forms, but not both
x1
z1
xn
zm
Combinational
logic
y1 yr
Yr Y1
Flip-Flop
memory
Pulse Mode circuit model
Fundamental Mode
Level inputs and unclocked memory element

Assume delay is lumped and equal (t)
In reality often not necessary
Only one input is allowed to change at any instant of time

x1
z1
xn
zm
Combinational
logic
y1 yr
Yr Y1
Delay, t
Fundamental Mode circuit model
In all types: State must be stable before input can be

change
Behavior is unpredictable (nondeterministic) if circuit not

allowed to settle
Stable State
PS = present state
NS = next state
PS = NS = Stability
Machine may pass through none or more intermediate

states on the way to a stable state
Desired behavior since only time delay separates PS from NS
Oscillation
Machine never stabilizes in a single state
Races
A Race Occurs in a Transition From One State to the Next

When More Than One Next State Variables Changes in
Response to a Change in an Input
Slight Environment Differences Can Cause Different State
Transitions to Occur
Supply voltage
Temperature, etc.
Races
Present State : PS (Y1Y2)
if Y1 changes
first
01
11
if Y2 changes
first
00
10
Desired Next State: NS
Types of Races
Non-Critical
Machine stabilizes in desired state, but may transition through

other states on the way
Critical
Machine does not stabilize in the desired state
Races
Present State : PS (Y1Y2)
if Y1 changes
first
01
11
if Y2 changes
first
00
Critical Race
Non-Critical Race
10
Desired Next State: NS
00
Asynchronous FSM Benefits
Fastest FSM
Economical
No need for clock generator
Output Changes When Signals Change, Not When Clock

Occurs
Data Can Be Passed Between Two Circuits Which Are Not
Synchronized
In some technologies, like quantum, clock is just not
possible to exist, no clocks in live organisms.
Asynchronous FSM Example
input
present
state
next
state
y1
y2
Next State Variables
( ) ( x y y )+ x + y
Y1 ( x, y1 , y2 ) = x y1
= x y1 + x y1 y2 + x y2
Y2 ( x, y1 , y2 ) = y2 x y
= y2 + x y1
Asynchronous State Tables
States are either Stable or Unstable.
Stable states encircled with

Present
state
symbol.
Next state, output

x=0
x=1
Q0
Q0,0
Q1,0
Q1
Q2,0
Q1,0
Q2
Q2,0
Q3,1
Q3
Q0, 0
Q3,1
Oscillations occur if all states are unstable for an input value.

Total State is a pair (x, Qi)
Constraints on Asynchronous Networks
If the next input change occurs before the previous

ones effects are fed back to the input, the machine
may not function correctly.
Thus, constraints are needed to insure proper

operation.
Fundamental Mode Input changes only when the

machine is in a stable state.
Normal Fundamental Mode A single input change

occurring when the machine is in a stable state
produces a single output change
Analysis Pulse-Mode Asynch. Circuit
Assumptions
Pulse do not occur simultaneously on two or more input lines

State transition only occurs only if an input pulse occurs
All devices trigger on the same edge of each pulse

z
x1
States:
y=0=A
y=1=B
x2
y Q
SET
y
Q
CLR
Inputs:
[x1,x2] = 00 = I0
[x1,x2] = 10 = I1
[x1,x2] = 01 = I2
z = x1 y
S = x1 y
R = x2 y

States:
y=0=A
y=1=B
x1
x2
y
S
R
z
Inputs:
[x1,x2] = 00 = I0
[x1,x2] = 10 = I1
[x1,x2] = 01 = I2
z = x1 y
S = x1 y
R = x2 y

States:
y=0=A
y=1=B
z = x1 y
Inputs:
[x1,x2] = 00 = I0
[x1,x2] = 10 = I1
[x1,x2] = 01 = I2
S = x1 y
R = x2 y
R
y\x1x2
00
01
11
10
y\x1x2
00
01
11
10
z
y\x1x2
00
01
11
10

S
R
y\x1x2
00
01
11
10
y\x1x2
00
01
11
10
SR
y\x1x2
Y
00
01
11
10
y\x1x2
00
01
11
10
00
00
10
00
01
00
Y/z
y\x1x2
00
01
11
10
z
y\x1x2
00
01
11
10
0 0/0 0/0
1/0
1 1/0 0/0
1/1

z
States:
y=0=A
y=1=B
x1
x2
z = x1 y
y Q
SET
S = x1 y
R = x2 y
y
Q
Y/z
y\x1x2
Inputs:
[x1,x2] = 00 = I0
[x1,x2] = 10 = I1
[x1,x2] = 01 = I2
CLR
10
Present
State
0 0/0 0/0 1/0
A/0
A/0
B/0
B/0
A/0
1 1/0 0/0 1/1
B/0
A/0
B/1
B/1
A/0
00
01
I0
I2
I1
Present
State
x1
x2
Exercise
x
D1 = y1 , C1 = xy2
D2 = y1 , C2 = x
z = xy1 y2
y1
y2
SET
Inputs:
I0 = no pulse on x
I1 = pulse on x
CLR
SET
CLR
States (y1, y2)

A = 00
B = 01
C = 10
D = 11
Exercise
D1 = y1 , C1 = xy2
D2 = y1 , C2 = x
z = xy1 y2
Inputs:
I0 = no pulse on x
I1 = pulse on x
States (y1, y2)

A = 00
B = 01
C = 10
D = 11
x
y1
y2
D1=D2
C1
C2
z
Exercise
x
y1
y2
SET
CLR
SET
CLR
D1 = y1 , C1 = xy2
D2 = y1 , C2 = x
z = xy1 y2
We need to construct the K-map

for the State Table.
DFF clock input will see a transition
1 to 0 if the input pulse occurs
From the DFF Characteristics
equation and this observation, the
next state equations are:
Y1 = D1C1 + y1C1
= y1 xy2 + y1 ( x + y2 )
= xy1 y2 + x y1 y2 + y1 y2
Y 2= D2C2 + y2C2
= xy1 + x y2
Y1 = D1C1 + y1C1
Exercise
D1
D2
y1y2\x
Y 2= D2C2 + y2C2
C1
00 1
00 0
01 1
01 0
11 0
10 0
y1y2\x 0
00 1
C2
y1y2\x
D1C1
1
y1y2\x
00 10 10
00 0
01 10 11
01 0
11 0
11 00 01
11 1
10 0
10 00 00
10 1
y1y2\x 0
00 0
01 1
01 0
11 0
10 0
D2C2
y1y2\x
Y1
Y2
y1y2\x
y1y2\x
00 10 11
00 0
01 10 11
01 1
11 0
11 00 01
11 1
10 0
10 00 01
10 0
Y1 = D1C1 + y1C1
Exercise
Y1
Y2
y1y2\x
Y 2= D2C2 + y2C2
Y1Y2
y1y2\x
00 0
00 00 01
01 0
01 01 11
11 1
11 11 00
10 1
10 10 10
Y1Y2/z
y1y2\x
00 0
01 1
y1y2\x
z = xy1 y2
Y1Y2/z
y1y2\x
00
00/0
01/0
01
01/0
11/0
11 1
11
11/0
00/1
10 0
10
10/0
10/0
I0
I1
00
00/0
01/0
01
01/0
11/0
11
11/0
00/1
10
10/0
10/0
Y1Y2/z
y1y2\x
00
01/0
01
11/0
11
00/1
10
10/0
Exercise
x
y1
y2
SET
Y1Y2/z
y1y2\x
I1
A/0
B/0
B/0
D/0
C/0
C/0
D/0
A/1
I0/0
CLR
SET
I0
I0/0
CLR
I1/1
D
I0/0
I1/0
I1/0
B
I0/0
I1/0
Design of Pulse-Mode Circuit
Step 1. Derive state diagram or state table

Step 2. Minimize the state table
Step 3. Choose state assignment and generate the
transition output table
Step 4. Select type of latch or flip-flop to be used and
determine excitation equation
Step 5. Determine the output equation
Step 6. Draw the circuit
Do it yourself
Design a pulse-mode circuit having two input lines x1 and

x2, and one output line z. The circuit should produce an
output pulse coincide with the last input pulse in the
sequence x1-x2-x2. No other input sequence should
produce an output pulse. (Sequence detector x1-x2-x2)
Use T-FF: T = 1, C acts as input
Step 1
States
A : indicates that the last input was x1
B : indicates that the sequence x1-x2 occurs
C : indicates that the sequence x1-x2-x2 occurs
Present
State
x1
x2
A/0
B/0
A/0
C/1
A/0
C/0
x1/0
x1/0
A
x1/0
C
x2/0
x2/0
x2/1
Step 2 and 3
Step 2. State table is minimize as given

Step 3. State assignment A=00, B=01, and C=10
Y1Y2/z
y1y2
x1
x2
00
00/0
01/0
01
00/0
10/1
10
00/0
10/0
Step 4 and 5
Y1
Use T-FF: T = 1
y1y2
Y1Y2/z
y1y2
x1
x2
00
00/0
01/0
01
00/0
10/1
10
00/0
10/0
z
y1y2
x1 x2
C1
Y2
x1 x2
y1y2
x1 x2
00
00
01
01
11
11
10
10
y1y2
x1 x2
C2
y1y2
x1 x2
00
00
01
01
11
11
10
10
00
01
11
C1 = x1 y1 + x2 y2
10
C2 = x1 y2 + x2 y1
z = x2 y 2
Step 6
C1 = x1 y1 + x2 y2
C2 = x1 y2 + x2 y1
z = x2 y 2
y1
x1
Q
Q
z
1
x2
Q
Q
y2
Do it yourself
Design a pulse-mode circuit with inputs x1,x2, x3 and

output z. The output must change from 0 to 1 iff the input
sequence x1-x2-x3 occurs while z = 0. The output must
change from 1 to 0 only after an x2 input occur.
Use SR Latch
Step 1
Moore machine because output must remain high

between pulses
x2,x3
Present
State
x1
x2
x3
x1
x1
A/0
B/0
x3
x2
x1
x2
x2
D/1
x1,x3
C/0
x3
Step 2 and 3
Step 2. State table is minimize as given

Step 3. State assignment A=00, B=01, C=11, and D =10
Y1Y2
y1y2
x1
x2
x3
00
01 00 00
01
01 11 00
11
01 00 10
10
10 00 10
Y1Y2
y1y2
Step 4
Use SR Latch
Y1
S1
y1y2
x1 x2 x3
R1
y1y2
x1 x2 x3
y1y2
x1
x3
00
01 00 00
01
01 11 00
11
01 00 10
10
10 00 10
x1 x2 x3
00
00
00
01
01
01
11
11
11
10
10
10
Y2
S2
y1y2
x1 x2 x3
x2
S1 = x2 y1 y2
R1 = x1 y2 + x2 y1
R2
y1y2
x1 x2 x3
y1y2
x1 x2 x3
00
00
00
01
01
01
11
11
11
10
10
10
S 2 = x1 y1
R1 = x2 y1 + x3
Step 5
Y1Y2
y1y2
x1
x2
x3
00
01 00 00
01
01 11 00
11
01 00 10
10
10 00 10
z = y1 y2
Step 6
S1 = x2 y1 y2
S 2 = x1 y1
R1 = x1 y2 + x2 y1
R1 = x2 y1 + x3
z = y1 y2
SET
CLR
x1
x2
S
x3
SET
CLR
Analysis Fundamental-Mode Asynch. Circuit
Assumptions
Fundamental Mode Input changes only when the machine is

in a stable state.
Normal Fundamental Mode A single input change occurring
when the machine is in a stable state produces a single output
change
This type of circuit is most difficult to analyze
Introduction to Fundamental mode

x1
z1
xn
zm
Combinational
logic
y1 yr
Yr Y1
Delay, t
z = g(x , y )
t
Y = h( x , y )
t
t + t
=Y
Fundamental Mode circuit model
x=(x1, , xn) : input state

y =(y1, , yr) : secondary state
z=(z1, , zm) : output state
Y=(Y1, , Yr) : excitation state
(x,y) : total state
Example
x1
Set of equations
z t = g ( x1t , x2t , y t ) = x1t x2t + x2t y t
x2
Y t = zt
y
t + t
=Y
Delay
dt
x1
x2
y
z=Y
t1
t2
t3 t4
t5 t6 t7
Unstable at t3 (y Y)
t8
t9 t10
t11
t12
t13 t14 t15
Tabular Representation
Excitation Table
Excitation state and output

It is a function of total space (x1, ,xn, y1, , yr)
K-map of
Row of secondary state

Column of unique input state
z t = g ( x1t , x2t , y t ) = x1t x2t + x2t y t

Y t = zt
y
t + t
=Y
y\x1x2
00
01
11
10
0 0/0 0/0 1/1 0/0

1 1/1 0/0 1/1 1/1
Flow Table
Replace the secondary state and excitation state by letters or

nonbinary characters
It represents the behavior of the circuit but does not specify
the realization of the circuit
y\x1x2
00
01
11
10
y\x1x2
00
01
11
10
a/0
0 0/0 0/0 1/1 0/0
a a/0
a/0 b/1
1 1/1 0/0 1/1 1/1
b b/1
a/0 b/1 b/1
Flow Table
Can be used to determine

the output behavior given
an input sequence
Input change produce
horizontal movement
State changes produce
vertical movement
y\x1x2
00
t1
a
01
t6
t7
a/0
a/0
t5
b/1
a/0
11
10
t3
t2
b/1
a/0
t4
b/1
b/1
x1
x2
y
z=Y
t1
t2
t3 t4
t5 t6 t7
t8
t9 t10
t11
t12
t13 t14 t15
Analysis of Fundamental-Mode Asynch. Circuit
Determine the excitation and output equations from the

circuit diagram
Plot the excitation and output K-map for Y and z and from
these K-map construct the excitation table
Locate and circle all stable state in the excitation table
Assign a unique nonbinary symbol for each row of the
excitation table.
Construct the flow table
Example
Step 1
Y1 = x y2
Y2
Y2 = xy1
Y1
z = x y1
Delay
dt
y1
y2
Delay
dt
Example
Step 2
Y1
Y1 = x y2
y1y2\x
00
01
Y2 = xy1
z = x y1
Y2
z
y1y2\x
y1y2\x
00
00
01
01
11
11
11
10
10
10
Y1 Y2/z
Y1 Y2/z
Y1 Y2/z
y1y2\x
y1y2\x
y1y2\x
00
10/0
01/0
3/0
2/0
3/0
2/0
01
00/0
01/0
1/0
2/0
1/0
2/0
11
00/1
00/0
1/1
1/0
3/1
1/0
10
10/1
00/0
3/1
1/0
1/1
1/0
Example
Timing Diagram
Y1 Y2/z
y1y2\x
00
10/0
01/0
01
00/0
01/0
11
00/1
00/0
10
10/1
00/0
Start from (2) and input changes from 1 to 0

State (2) 1 (3)
dt
x
y1
Y1 Y2/z
y1y2\x
y2
00
10/0
01/0
Y1
01
00/0
01/0
11
00/1
00/0
Y2
10
10/1
00/0
dt
Example
Step 1
Let Q0 be state when y1 = 0 and Q1 be state when y1 = 1.
x1
z1
x2
z2
y1
Delay
dt
Y1
Y1 = ( x2 + ( x1 + y1 )) = ( x2 + x1 y1 )
= x2 ( x1 + y1 ) = x1 x2 + x2 y1
z1 = x1 y1
z 2 = y1
Example
Step 2 through 5
Let Q0 be state when y1 = 0 and Q1 be state when y1 = 1.
Y1
x1
y1\x1 x2 00 01 11 10
z1
x2
z2
Y1
Input x1,x2
Q0
Q0,10 Q0,10 Q0,00 Q1,00
Q1
Q1,01 Q0,01 Q0,01 Q1,01
01
y1\x1 x2 00 01 11 10
Present
State
00
z1
Delay
dt
y1
11
z2
10
z1z2
y1\x1 x2 00 01 11 10
0
Do it Yourself
x1
x1
R
S
x1
x2
Analyze this circuit!
Q1
z
x1
x2
x1
SET
CLR
SET
CLR
x1
Q
Q
Q2
Example (Excitation Table)

=
z Q1Q2 + x1Q2
S1 = x1Q2
R1 = x1Q2
S 2 = x1 x2Q1
=
R1 x1 x2 + x1Q1
Present State
(Q1Q2)
00
Excitation
(S1R1,S2R2)
Output
(z)
Inputs State (x1x2)
Inputs State (x1x2)
01
10
11
00
01
10
11
00 00,01
00,01
10,00
10,00
01 00,01
00,01
01,00
01,00
10 00,01
00,10
10,00
10,00
11 00,01
00,10
01,00
01,00
Example (Transition Table)

Present State
(Q1Q2)
Next State
(Q+1Q+2)
Output
(z)
Inputs State (x1x2)
Inputs State (x1x2)
00
01
10
11
00
01
10
11
00
00
00
10
10
01
00
00
01
01
10
10
11
10
10
11
10
11
01
01
Example (State Table)

Present State
(Q1Q2)
Next State
(Q+1Q+2)
Output
(z)
Inputs State (x1x2)
Inputs State (x1x2)
00
01
10
11
00
01
10
11
00 A
01 B
10 C
11 D
Example (Flow Table)

Present State
(Q1Q2)
Next State
(Q+1Q+2)
Output
(z)
Inputs State (x1x2)
Inputs State (x1x2)
00
01
10
11
00
01
10
11
Tables, tables and tables.
Excitation table
Transition Table
State Table
Flow Table
Careful with unreachable state because input is restricted

Output only at stable state
Design of Fundamental-Mode Circuit
Step 1. Construct a primitive flow table from word

description of the problem
Step 2. Derive a reduced primitive flow table
Step 3. Make secondary state assignment
Step 4. Construct excitation table and output table
Step 5. Determine the logic equations for each state
variable and output state variable
Step 6. Realize the logic equation with the appropriate
logic devices
A primitive flow table is a flow table that contains only
one stable state per row
Example
A two input (x1,x2) and one output (z) asynchronous sequential

circuit is to be designed to meet the following specifications.
1.
2.
3.
Whenever x1 = 0, z = 0.
The first change to input x2 that occurs while x1 = 1 must cause the
output to become z = 1.
A z = 1 output must not change to z = 0 until x1 = 0.
A typical input-output response of the desired circuit is

shown below.
x1
x2
z
Example
Step 1. Create a primitive table that satisfy the

requirement of the circuit.
Note:
Given only one stable state then we can only have 2 other
unstable state and one unspecified state.
x1
x2
z
Example
Next State, Output
Present
State
00
a,0
01
10
11
Possible input x1x2 = 00
Since the circuit is operating

on fundamental mode, then
there must be a stable state
at x1x2 = 00
Create a state a in the next
state at 00 column.
Circle it because it must be
stable.
Since z = 0 when x1 = 0, then
the output is set to 0
Example
Present
State
00
01
10
11
a,0
b,-
c,-
-,-
When x1x2 = 10,
At state (a),
b,0
Next State, Output
c,0
the next state must be an

unstable state, named c with
output.
We must add a new row for
state b, where c is stable for
x1x2 = 10
For x1 = 1, x2 must change
thus the output is 0
Since there can be only one

stable state in each row, this
implies that x1x2 = 11 can not
follow x1x2 = 00.
Place -,- at column x1x2 = 11
When x1x2 = 01,

unstable state, named b with
output.
state b, where b is stable for
x1x2 = 01
Since z = 0 for x1 = 0 then the
output is zero
Example
Present
State
00
01
10
11
a,0
b,-
c,-
-,-
a,-
b,0
-,-
d,-
c
d
Next State, Output
When x1x2 = 11,
c,0
d,0

unstable state, named d with
output.
state d, where d is stable for
x1x2 = 11
For x1 = 1, x2 must change
thus the output is 0
At state (b),
x1x2 = 10 can not follow x1x2
= 01.
When x1x2 = 00,

unstable state
For x1x2 = 00, we already
have a stable state (a). We
must consider this.
From specification, z=0
when x1 = 0, thus go to a
with - output
Example
Next State, Output
Present
State
00
01
10
11
a,0
b,-
c,-
-,-
a,-
b,0
-,-
d,-
a,-
-,-
c,0
e,-
At state (c),
d,0
e,1
When x1x2 = 00,
x1x2 = 01 can not follow x1x2 = 10.

From specification, z=0 when x1
= 0, thus go to a with - output
When x1x2 = 11,
Already have a stable state (d),

we must consider this.
For x1 = 1, x2 changes from 0 to 1
thus the output must be 1. Thus
we can not go to state (d)
the next state must be a new
unstable state, named e with
output.
We must add a new row for state
e, where e is stable for x1x2 = 11
and the output is 1
Example
Next State, Output
Present
State
00
01
10
11
a,0
b,-
c,-
-,-
a,-
b,0
-,-
d,-
a,-
-,-
c,0
e,-
-,-
b,-
f,-
d,0
e
f
At state (d),
When x1x2 = 01,
From specification, z=0 when x1

= 0, thus go to b with - output
When x1x2 = 10,
e,1
f,1
x1x2 = 00 can not follow x1x2 = 11.

Already have a stable state (c),

we must consider this.
For x1 = 1, x2 changes from 1 to 0
thus the output must be 1. Thus
we can not go to state (c)
the next state must be a new
unstable state, named f with
output.
We must add a new row for state
f, where f is stable for x1x2 = 10
and the output is 1
Example
Next State, Output
Present
State
00
01
10
11
a,0
b,-
c,-
-,-
a,-
b,0
-,-
d,-
a,-
-,-
c,0
e,-
-,-
b,-
f,-
d,0
-,-
b,-
f,-
e,1
f,1
At state (e),
When x1x2 = 01,
x1x2 = 00 can not follow x1x2 =

11.
From specification, z=0 when
x1 = 0, thus go to b with output
When x1x2 = 10,
Already have a stable state (c)

and (f), we must consider this.
For x1 = 1, x2 changes from 1 to
0 thus the output must be 1.
Thus we can not go to state (c)
the next state must be unstable
state f with output.
Example
Next State, Output
Present
State
00
01
10
11
a,0
b,-
c,-
-,-
a,-
b,0
-,-
d,-
a,-
-,-
c,0
e,-
-,-
b,-
f,-
d,0
-,-
b,-
f,-
e,1
a,-
-,-
f,1
e,-
At state (f),
When x1x2 = 00,
x1x2 = 01 can not follow x1x2 =

10.
From specification, z=0 when
x1 = 0, thus go to a with output
When x1x2 = 11,
Already have a stable state (d)

and (e), we must consider this.
For x1 = 1, x2 changes from 0 to
1 thus the output must be 1.
Thus we can not go to state (d)
the next state must be unstable
state e with output.
Example
Step 2. Reduce primitive flow table

It is an incompletely specified machine.
Start with implication chart to produce compatible pairs
Determine maximal compatibles
Determine minimal collection of maximal compatibles
Reduction of input-restricted flow table
Dashed entries are allowed to take different values
Implication chart
Find compatible pairs

Next State, Output
Present
State
00
01
10
11
a,0
b,-
c,-
a,-
b,0
a,-
-,-
-,-
d,-
cf
-,-
c,0
e,-
-,-
b,-
f,-
d,0
cf
cf
de
de cf
-,-
b,-
f,-
e,1
cf
de
a,-
-,-
f,1
e,-
de
de
Implication chart
Determine Maximal Compatible

Column
List of Compatible Classes
{e,f}
{e,f}
cf
de
{e,f}
{e,f}, {b,d}
cf
cf
de
de cf
{e,f}, {b,d},{a,b},{a,c}
cf
de
No single state is added since

every state already appear at least
once.
de
Implication chart
Determine minimal collection of maximal compatible

Apply the concept of prime-implicant to reduce flow table
Column
List of Compatible Classes
{e,f}
{e,f}
{a,b}
{e,f}
{a,c}
{e,f}, {b,d}
{b,d}
{e,f}, {b,d},{a,b},{a,c}
{e,f}
x
x
*
x
*
x
Minimal collection of MC is {a,c} {b,d} {e,f}
Constructing Minimal Row Flow Table
Next State, Output
Present
State
00
01
10
11
a,0
b,-
c,-
-,-
a,-
b,0
-,-
a,-
-,-
-,-
e
f
Present
State
Next State
00
01
10
11
{a,c} :
,0
,-
,0
,-
d,-
{b,d} :
,-
,0
,-
,0
c,0
e,-
{e,f} :
,-
,-
,1
,1
b,-
f,-
d,0
-,-
b,-
f,-
e,1
a,-
-,-
f,1
e,-
Secondary State Assignment
Step 3. State Assignment

The goal is to avoid race
Present
State
Next State
State Assignment Possibility

(,) (,) (,)
Choose!
(,) (,)
00
01
10
11
{a,c} :
,0
,-
,0
,-
y1\y2
{b,d} :
,-
,0
,-
,0
{e,f} :
,-
,-
,1
,1
Assignment
: 00
: 11
: 10
Constructing State Transition Table (Step 4)

Present
State
Next State
00
01
10
11
{a,c} :
,0
,-
,0
,-
{b,d} :
,-
,0
,-
,0
{e,f} :
,-
,-
,1
,1
Assignment
: 00
: 11
: 10
Replace all stable state with its assignment
Present
State
: 00
: 11
: 10
Next State
00
01
00,0
10
11
00,0
11,0
11,0
10,1
10,1
Constructing State Transition Table

Present
State
Next State
00
01
10
11
{a,c} :
,0
,-
,0
,-
{b,d} :
,-
,0
,-
,0
{e,f} :
,-
,-
,1
,1
Assignment
: 00
: 11
: 10
Now we need to replace the unstable states
Present
State
Next State
00
: 00
00,0
: 11
10,-
: 10
00,-
01
10
11
00,0
11,0
Input 00:
Total State (00,11) (00,00)
Create a cycle
(00,11) (00,10) (00,00)
11,0
10,1
10,1
Remember if a state changes

more than 1 bit at a time we have a race

Present
State
Next State
00
01
10
11
{a,c} :
,0
,-
,0
,-
{b,d} :
,-
,0
,-
,0
{e,f} :
,-
,-
,1
,1
Assignment
: 00
: 11
: 10
Present
State
Next State
00
01
10
: 00
00,0
10,-
00,0
: 11
10,-
11,0
: 10
00,-
11,-
11
Input 01:
Total State (01,00) (01,11)
Create a cycle
(01,00) (01,10) (01,11)
11,0
10,1
10,1


Present
State
Next State
00
01
10
11
{a,c} :
,0
,-
,0
,-
{b,d} :
,-
,0
,-
,0
{e,f} :
,-
,-
,1
,1
Assignment
: 00
: 11
: 10
Present
State
Next State
00
01
10
11
: 00
00,0
10,-
00,0
: 11
10,-
11,0
10,-
11,0
: 10
00,-
11,-
10,1
10,1
Input 10:
Total State (10,11) (10,10)
No problem here!
Only 1 bit need to change


Present
State
Next State
00
01
10
11
{a,c} :
,0
,-
,0
,-
{b,d} :
,-
,0
,-
,0
{e,f} :
,-
,-
,1
,1
Assignment
: 00
: 11
: 10
Present
State
Next State
00
01
10
11
: 00
00,0
10,-
00,0
10,-
: 11
10,-
11,0
10,-
11,0
: 10
00,-
11,-
10,1
10,1
Input 11:
Total State (11,00) (11,10)
No problem here!
Only 1 bit need to change

Constructing State Transition Table (variant 1)

Present
State
Next State
00
01
10
11
{a,c} :
,0
,-
,0
,-
{b,d} :
,-
,0
,-
,0
{e,f} :
,-
,-
,1
,1
Assignment
: 00
: 11
: 10
Used the unused state 01
Present
State
Next State
00
: 00
00,0
: 11
01,-
: 10
00,-
01
00,-
01
10
11
00,0
11,0
11,0
10,1
10,1
Input 00:
Total State (00,11) (00,00)
Create a cycle
(00,11) (00,01) (00,00)

Present
State
Next State
00
01
10
11
{a,c} :
,0
,-
,0
,-
{b,d} :
,-
,0
,-
,0
{e,f} :
,-
,-
,1
,1
Assignment
: 00
: 11
: 10
Used the unused state 01
Present
State
Next State
00
01
10
11
: 00
00,0
01,-
00,0
10,-
: 11
01,-
11,0
10,-
11,0
: 10
00,-
11,-
10,1
10,1
01
00,-
11,-
Input 01:
Total State (01,00) (01,11)
Create a cycle
(01,00) (01,01) (01,00)
All other inputs are the same as
before!

Present
State
Next State
00
01
10
11
{a,c} :
,0
,-
,0
,-
{b,d} :
,-
,0
,-
,0
{e,f} :
,-
,-
,1
,1
Assignment
: 00
: 11
: 10
Create non-critical race
Present
State
Next State
00
: 00
00,0
: 11
00,-
: 10
00,-
01
00,-
01
10
11
00,0
11,0
11,0
10,1
10,1
Input 00:
Total State (00,11) (00,00)
Non critical race
(00,11) (00,01) (00,00)
(00,11) (00,10) (00,00)

Present
State
Next State
00
01
10
11
{a,c} :
,0
,-
,0
,-
{b,d} :
,-
,0
,-
,0
{e,f} :
,-
,-
,1
,1
Assignment
: 00
: 11
: 10
Create non-critical race
Present
State
Next State
00
01
10
11
: 00
00,0
11,-
00,0
10,-
: 11
00,-
11,0
10,-
11,0
: 10
00,-
11,-
10,1
10,1
01
00,-
11,-
Input 01:
Total State (01,00) (01,11)
Non critical race
(01,00) (01,01) (01,11)
(01,00) (01,10) (01,11)
All other input are the same!
Constructing State Transition Table (output)
Now we need to set the output of the unstable states

If for some stable state the output is 0 and after input
changes the resulting stable state the output is 0, then all
unstable state that might be encountered during the time
between the two stable state must have an output of 0.
The same for stable state with output of 1.
Present
State
Next State
00
01
10
11
: 00
00,0
10,0
00,0
10,-
: 11
10,0
11,0
10,-
11,0
: 10
00,0
11,0
10,1
10,1
The unstable state (01,00) is

reachable from (00,00) having an
output 0 and eventually reaches
(01,11) which also have an output
of 0 then (01,00) must have an
output of 0.
The same for (00,11), (00,10) and
(01,10)
Constructing State Transition Table (output)
What about the others?

Consider (11,11) (10,11) (10,10)
(11,11) have an output of 0

(10,10) have an output of 1
The output of (10,11) can be left unspecified (dont care) as it
provides more flexibility in implementation as it does not violates
that no more than a single output can change.
Present
State
Next State
00
01
10
11
: 00
00,0
10,0
00,0
10,-
: 11
10,0
11,0
10,-
11,0
: 10
00,0
11,0
10,1
10,1
Note: no more than a single output

can change at a time!
You can do the same for variant 1
and 2
Determine Logic Equations (Step 5)

Present
State
y1y2
Next State
Y1Y2,z
y1y2\x1x2
00 01 11 10
00
01
10
11
00
: 00
00,0
10,0
00,0
10,-
01
: 11
10,0
11,0
10,-
11,0
11
: 10
00,0
11,0
10,1
10,1
10
Y1
Y2
y1y2\x1x2
00 01 11 10
y1y2\x1x2
00 01 11 10
00
00
01
01
11
11
10
10
Y1 = x2 + y2 + x1 y1
Y2 = x2 y2 + x1 x2 y1
z = x1 y1 y2
Realize logic equation (Step 6)

Y1 = x2 + y2 + x1 y1
Y2 = x2 y2 + x1 x2 y1
z
x1
Y1
z = x1 y1 y2
x2
Y2
y2
Delay
dt
y1
Delay
dt
With SR Latch?
Y1 = x2 + y2 + x1 y1
Y2 = x2 y2 + x1 x2 y1
z = x1 y1 y2
SR Excitation Property
00 SR 0d
01 SR 10
10 SR 01
11 SR d0
Next State
Y1Y2,z
Present
State
y1y2
00
01
10
11
: 00
00,0
10,0
00,0
10,-
: 11
10,0
11,0
10,-
11,0
: 10
00,0
11,0
10,1
10,1
Present
State
y1y2
Next State
(S1R1,S2R2),z
00
01
10
11
: 00
(0d,0d),0
(10,0d),0
(0d,0d),0
(10,0d),d
: 11
(d0,01),0
(d0,d0),0
(d0,01),d
(d0,d0),0
: 10
(01,0d),0
(d0,10),0
(d0,0d),1
(d0,0d),1

Next State
(S1R1,S2R2),z
Present
State
y1y2
00
01
10
11
: 00
(0d,0d),0
(10,0d),0
(0d,0d),0
(10,0d),d
: 11
(d0,01),0
(d0,d0),0
(d0,01),d
(d0,d0),0
: 10
(01,0d),0
(d0,10),0
(d0,0d),1
(d0,0d),1
S1
R1
y1y2\x1x2
00 01 11 10
y1y2\x1x2
00 01 11 10
00
00
01
01
11
11
10
10
S1 = x2
R1 = x1 x2 y2

Next State
(S1R1,S2R2),z
Present
State
y1y2
00
01
10
11
: 00
(0d,0d),0
(10,0d),0
(0d,0d),0
(10,0d),d
: 11
(d0,01),0
(d0,d0),0
(d0,01),d
(d0,d0),0
: 10
(01,0d),0
(d0,10),0
(d0,0d),1
(d0,0d),1
S2
R2
y1y2\x1x2
00 01 11 10
y1y2\x1x2
00 01 11 10
00
00
01
01
11
11
10
10
S 2 = x1 x2 y1
R2 = x2

S1 = x2
R1 = x1 x2 y2
S 2 = x1 x2 y1
R2 = x2
z = x1 y1 y2
x1
x2
z
S
SET
CLR
SET
CLR
Do it yourself
Design a two input (x1, x2) and two output (z1,z2) circuit
where,
z1z2 =00 when x1x2=00

Output 10 will be produced following the occurrence of 00-0111 input sequence, and the output goes back to 00 after a 00
input.
Output 01 will be produced following the occurrence of 00-1011 input sequence, and the output goes back to 00 after a 00
input.
Step 1: Construct Primitive Flow Table

Present
State
00
01
11
10
Present
State
a/00
b/--
-/--
c/--
a/--
b/00
d/--
-/--
a/--
-/--
e/--
-/--
f/--
-/--
Input State (x1 x2)
Input State (x1 x2)

00
01
11
10
a/00 b/00
-/--
c/00
a/00 b/00
d/-0
-/--
c/00
a/00
-/--
e/0-
c/00
d/10
g/--
-/--
f/10
d/10
g/10
h/--
e/01
i/--
-/--
h/01
e/01
i/01
a/--
f/10
d/--
-/--
a/-0
f/10
d/10
-/--
a/--
-/--
d/--
g/10
a/-0
-/--
d/10
g/10
a/--
h/01
e/--
-/--
a/0-
h/01
e/01
-/--
a/--
-/--
e/--
i/01
a/0-
-/--
e/01
i/01
It might be easier if we assigned the output of the unstable states.

So that we correctly reduced the flow table.
Step 2: Construct Implication chart

Present
State
Input State (x1 x2)

00
01
11
10
a/00 b/00
-/--
c/00
a/00 b/00
d/-0
-/--
a/00
-/--
e/0-
c/00
-/--
f/10
d/10
g/10
-/--
h/01
e/01
i/01
a/-0
f/10
d/10
-/--
a/-0
-/--
d/10
g/10
a/0-
h/01
e/01
-/--
a/0-
-/--
e/01
i/01
de
Step 2: Find Maximal Compatibles

b
column List of Maximal Compatible

de
d
e
f
{h,i}
{h,i}
{h,i}{f,g}
{e,h,i}{f,g}
{e,h,i}{d,f,g}
{e,h,i}{d,f,g}{c,h}
{e,h,i}{d,f,g}{c,h}{b,g}
{e,h,i}{d,f,g}{c,h}{b,g}{a,b}{a,c}
Step 2: Merger Diagram

a
column List of Maximal Compatible

h
{h,i}
{h,i}
{h,i}{f,g}
{e,h,i}{f,g}
{e,h,i}{d,f,g}
{e,h,i}{d,f,g}{c,h}
{e,h,i}{d,f,g}{c,h}{b,g}
{e,h,i}{d,f,g}{c,h}{b,g}{a,b}{a,c}
Minimal cover : {e,h,i}{d,f,g}{a,b}{a,c}
Reassignment: {a,b}
{d,f,g}
{a,c}
{e,h,i}
i
b
h
c
g
d
f
Step 2: Reduced Flow Table

Reassignment:
Present
State
{a,b}
{d,f,g}
{a,c}
{e,h,i}
Present
State
00
01
11
10
/00
/00
/-0
/00
/-0
/10
/10
/10
/00
/00
/0-
/00
/0-
/01
/01
/01
Input State (x1 x2)
Input State (x1 x2)

00
01
11
10
a/00 b/00
-/--
c/00
a/00 b/00
d/-0
-/--
a/00
-/--
e/0-
c/00
-/--
f/10
d/10
g/10
-/--
h/01
e/01
i/01
a/-0
f/10
d/10
-/--
a/-0
-/--
d/10
g/10
a/0-
h/01
e/01
-/--
a/0-
-/--
e/01
i/01
Row 1 includes two states and .

Any unstable state could go to either one of them.
Step 3: Secondary State Assignment

Present
State
00
01
11
10
/00
/00
/-0
/00
/-0
/10
/10
/10
/00
/00
/0-
/00
/0-
/01
/01
/01
Present
State
Input State (x1 x2)
Input State (x1 x2)

00
01
11
10
/00
/00
/-0
/00
/-0
/10
/10
/10
/00
/00
/0-
/00
/0-
/01
/01
/01
Assignment:
00
01
10
11
Look at row 4 column 1,

transition from (11 00)
Need to change (11 10)
Step 4: Constructing Transition Table

Present
State
00
01
11
10
/00
/00
/-0
/00
/-0
/10
/10
/10
/00
/00
/0-
/00
/0-
/01
/01
/01
PS
(y1 y2)
Input State (x1 x2)
Input State (x1 x2)

00
01
00
00/00 00/00
01
00/-0
10
10/00 00/00
11
10/0-
11
10
01/-0
10/00
01/10 01/10 01/10

11/0-
10/00
11/01 11/01 11/01
Assignment:
00
01
10
11
Step 4: Constructing Excitation and Output Table

PS
(y1 y2)
00
01
11
10
00
01
11
10
00
00
00
01
10
00
00
-0
00
01
00
01
01
01
-0
10
10
10
10
10
00
11
10
00
00
0-
00
11
10
11
11
11
0-
01
01
01
Next State (Y1 Y2)
Output (z1 z2)
Step 5: Next State and Output Equations

x1x2
x1x2
y1y2
y1y2
00
01
11
10
00
01
11
10
00
01
11
10
00
01
11
10
Y2
Y1
x1x2
y1y2
Y1 = y1 y2 + x1 y1 + x2 y1 + x1 x2 y2
Y2 = x1 x2 + x1 y2 + x2 y2
x1x2
00
01
11
10
00
01
11
10
z1
y1y2
00
01
11
10
00
01
11
10
z2
z1 = y1 y2
z2 = y1 y2

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Asynchronous Machine

Types of Asynchronous Sequential Machines

Pulse will not occur simultaneously on two or more inputs

Types of Asynchronous Sequential Machines

Level inputs and unclocked memory element

In reality often not necessary

Only one input is allowed to change at any instant of time

Types of Asynchronous Sequential Machines

In all types: State must be stable before input can be

Behavior is unpredictable (nondeterministic) if circuit not

Machine may pass through none or more intermediate

Machine never stabilizes in a single state

A Race Occurs in a Transition From One State to the Next

Present State : PS (Y1Y2)

Machine stabilizes in desired state, but may transition through

Machine does not stabilize in the desired state

Present State : PS (Y1Y2)

Asynchronous FSM Benefits

No need for clock generator

Output Changes When Signals Change, Not When Clock

Asynchronous FSM Example

Next State Variables

Asynchronous State Tables

States are either Stable or Unstable.

Stable states encircled with

Next state, output

Oscillations occur if all states are unstable for an input value.

Constraints on Asynchronous Networks

If the next input change occurs before the previous

Thus, constraints are needed to insure proper

Fundamental Mode Input changes only when the

Normal Fundamental Mode A single input change

Analysis Pulse-Mode Asynch. Circuit

Pulse do not occur simultaneously on two or more input lines

Analysis Pulse-Mode Asynch. Circuit

Analysis Pulse-Mode Asynch. Circuit

Analysis Pulse-Mode Asynch. Circuit

Analysis Pulse-Mode Asynch. Circuit

Analysis Pulse-Mode Asynch. Circuit

0 0/0 0/0 1/0

1 1/0 0/0 1/1

States (y1, y2)

States (y1, y2)

We need to construct the K-map

Design of Pulse-Mode Circuit

Step 1. Derive state diagram or state table

Design a pulse-mode circuit having two input lines x1 and

Use T-FF: T = 1, C acts as input

Step 2. State table is minimize as given

Design a pulse-mode circuit with inputs x1,x2, x3 and

Moore machine because output must remain high

Step 2. State table is minimize as given

Analysis Fundamental-Mode Asynch. Circuit

Fundamental Mode Input changes only when the machine is

This type of circuit is most difficult to analyze

Introduction to Fundamental mode

Fundamental Mode circuit model

x=(x1, , xn) : input state

t13 t14 t15

Excitation state and output

Row of secondary state

z t = g ( x1t , x2t , y t ) = x1t x2t + x2t y t

0 0/0 0/0 1/1 0/0