CAD Slides 05

F.
Maloberti
DATA CONVERTERS
Springer
2007
Chapter 5
CIRCUITS FOR DATA CONVERTERS
Slide Set
Data Converters
Circuits For Data Converters
F. Maloberti
DATA CONVERTERS
Springer
2007
Chapter 5
Summary
Sample-and-Hold
Diode Bridge S&H
Switched Emitter Follower
Features of S&H with BJT
CMOS Sample-and-Hold
CMOS Switch with low Voltage Supply
Folding Amplifiers
Voltage-to-Current Converter
Clock Generation
F. Maloberti
DATA CONVERTERS
Springer
2007
Chapter 5
SAMPLE-AND-HOLD
The S&H uses two phases, one for sampling and the other for retaining and
making the signal available during the hold phase. If the output is available
during the sampling period we have a track and hold (T&H).
Vin
Fs
Aout .
Ain .
Input
Buffer
Cs
VS&H
Output
Buffer
F. Maloberti
DATA CONVERTERS
Springer
2007
Chapter 5
DIODE BRIDGE S&H
I1
D1 D2
VS&H
Vin
D3 D4
1.
IC
SAMPLE
A
HOLD
QH
QS
I2
Cs
SAMPLE
t
HOLD
F. Maloberti
DATA CONVERTERS
Springer
2007
Chapter 5
Diodes in the bridge
If you want ultra-speed use ... xxxxxxx
The speed of the diodes

establishes the speed of the
diode-bridge S&H.
The use of Sckottly diodes
makes the scheme very fast
and suitable for mediumresoluton samplers running at
multi-GHz frequencies.
F. Maloberti
DATA CONVERTERS
Springer
2007
Chapter 5
Diode Bridge Imperfections

Aperture distortion
IC =
Hold Pedestal:
Track-mode Distortion
Hold feed-through
1 dVin
Cs dt
(1)
F. Maloberti
DATA CONVERTERS
Springer
2007
Chapter 5
Improved Diode Bridge

VB
I1
RB
Vin
CD1
D1
CD2
CD4
RA
VA
D2
D3
1 .
D4
Cs
VS&H
A
Cs
H
QH
I2
(a)
DB
Vin
CD3 A
Ix
QS
DA
S
Ix
(b)
VS&H
F. Maloberti
DATA CONVERTERS
Springer
2007
Chapter 5
SWITCHED EMITTER FOLLOWER

CLK
CLK
I1
Vin
I1
CLK
I1
1 .
D1 D2
VS&H
Vin
Q1
Cs
CLK
2I1
(a)
D2
1 .
VS&H
Cs
2I1
(b)
Fig. (a) reduces this by 0.7 V. A more convenient scheme is Fig. (b)
F. Maloberti
DATA CONVERTERS
Springer
2007
Chapter 5
Observation
But you have to remember the ...
The bipolar or diode based

switch must simultaneously
turn off all the currents flowing
in the sampling capacitance
connection. A 1 psec delay
with 1mA and 1 pF gives rise
to an offset of 1mV!
F. Maloberti
DATA CONVERTERS
Springer
2007
Chapter 5
How to fix the problem ...
Vin
1 .
Rb
VB
QE
VE
1
FH
QH
QS
Ibias
FS
Cs
VT&H
F. Maloberti
DATA CONVERTERS
Springer
2007
Chapter 5
10
Circuit Implementation of the buffer
Q3
Q4
Ibias/2
Vout1
Vin1
R3
R4
Q1
Q2
R1
Vout2
Vin2
Ibias/2
Vout1
Vout2
Q3 Q1
R2
Ibias
(a)
Ibias
Q2 Q4
Vin1 Vin2
(b)
Ibias
F. Maloberti
DATA CONVERTERS
Springer
2007
Chapter 5
11
Improvements
QC
Vin
QC
1
Vin
QE
S
QH
QS
(a)
D2
Vout-
QE
Vout+
QD1
Cs
H
Ibias
D1
QH
QS
S
QD2
Ibias
(b)
F. Maloberti
DATA CONVERTERS
Springer
2007
Chapter 5
12
Complementary Bipolar S&H

I2
QS2 QH2
VH
I2
Vin
Vout Vin
Q1
Q1
Q3
Q2
A
A
Vout
(b)
Vout
Cs
Q2
QS1 QH1
VS
VH
I1
(a)
Q4
CL
Q3
Q4
Q2
I1
I1
Vin Q1
I2
VS
(c)
F. Maloberti
DATA CONVERTERS
Springer
2007
Chapter 5
13
Observe that
Complementary schemes are good but ...
Complementary bipolar
S&H requires a comparable
fT for the npn and the
pnp devices. The feature
is not granted by many
technologies.
F. Maloberti
DATA CONVERTERS
Springer
2007
Chapter 5
14
FEATURES OF S&Hs WITH BJT

Input range
Vin(nT ) VD < Vin(t) < Vin(nT ) + VD
(2)
Linearity issues:
The VBE depends on the emitter current
I
VBE ' VBE0 + VT ln E
Ibias
(3)
dVin
IE = Ibias + CS
.
dt
(4)
F. Maloberti
DATA CONVERTERS
Springer
2007
Chapter 5
Vout+ = Vin+ VBE0 VT ln
Vout = Vin VBE0 VT ln
in
Ibias + CS dV
dt
Ibias
Ibias CS dV,in dt
Ibias
dVin
Ibias + CS dt
;
Vout,d = VT ln
dVin
Ibias CS dt
15
(5)
(6)
"
(7)
Ibias + AinCS cos(int)

Vout,d = VT ln
.
Ibias AinCS cos(int)
(8)
F. Maloberti
DATA CONVERTERS
Springer
2007
Chapter 5
Example 5.1
110
105
100
95
SFDR [dB]
90
85
80
75
70
65
60
6
Ibias/IC
10
16
F. Maloberti
DATA CONVERTERS
Springer
2007
Chapter 5
17
Features of S&H s With BJT

dVin
IQ2 = Ibias CS
;
dt
(9)
2 4kT
+ 4kT rbb0
3 gm
(10)
4kT
2 4kT
4kT
=
+ 4kT rbb0 +
2
gm
3 gm
R 0 gm
(11)
2
vn,in
=
2
vn,eq
=
dVin
IQ4 = Ibias + CS
,
dt
F. Maloberti
DATA CONVERTERS
Springer
2007
Chapter 5
18
kT
2
Vn,CS =
CS
(12)
kT + gmRS
2
Vn,CS =
CS 1 + gmRS
(13)
F. Maloberti
DATA CONVERTERS
Springer
2007
Chapter 5
v2
n,in
1/gm
Vin
Ibias
R0
i2
n,0
v2
n,in
(a)
R0
2
i n,0
(b)
1/gm
1/gm
4kT
=
g
n,eq
gm
v2
(c)
Vout
CS
RS
v2
4kT RS
CS
n,eq
(d)
19
F. Maloberti
DATA CONVERTERS
Springer
2007
Chapter 5
Trade-off
A resistance in series
with a S&H slows down
its speed but reduces the
excess noise caused by
the rbb0 base resistance
and the current source,
bringing the noise power
close to the fundamental
kT/C limit.
20
F. Maloberti
DATA CONVERTERS
Springer
2007
Chapter 5
21
CMOS SAMPLE-AND-HOLD
L
Ron =
CoxW (VGS VT h)
on
VDD
clk
clk
off
clk
GND
clk
(14)
IB
Vin+
Vin
Vout
Vout+
MS
MD
1.
CS
CS
MB
Vin,d
Ron
Vout,d
(a)
clk
clk
Vin
Vout
1.
CS
clk
Vin-
VoutMS
MD
CS
clkb
(b)
IB
(c)
MB
F. Maloberti
DATA CONVERTERS
Springer
2007
Chapter 5
22
Clock Feed-through
Qch = (W L) Cox(VG,on VT h)
(15)
v
u
u CoxW/L
B = Vov t
.
||CS
(16)
F. Maloberti
DATA CONVERTERS
Springer
2007
Chapter 5
VG
VS
Vin
Rin
Rin
Cin
dt
VG (on)
toff
Vout
CS
VTh
Vin
VG (off)
ON
OFF
23
F. Maloberti
DATA CONVERTERS
Springer
2007
Chapter 5
DQS
Qch
CS>>Cin
3CS=Cin
CS=Cin
0.5
CS=3Cin
CS<<Cin
0
0.01
0.1
1
B
10
24
F. Maloberti
DATA CONVERTERS
Springer
2007
Chapter 5
25
Example 5.2
Vos =
1 CG
Vov = 0.64 mV
2 Cs
(17)
F. Maloberti
DATA CONVERTERS
Springer
2007
Chapter 5
Clock Feed-through Compensation

Keep in Mind
The effectiveness of the clock
feed-through compensation depends on symmetric working
conditions and the matching of
elements. She expected maximum cancellation is about 90%,
the best to do is to obtain a dc
(signal independent) term.
26
F. Maloberti
DATA CONVERTERS
Springer
2007
Chapter 5
27
Two-stage OTA as T&H
Vout(nT )
V1(nT ) =
A2
[Vin(nT ) + Vos]A1A2
;
Vout(nT ) =
1 + A1 A2
CS
F1
Vin,d
Vin
-+
Vout,d
+-
S1
CS
S4
F2
F1d
F2 S2 F1 S3
F1
F1d
_
+
+
Vout
F1
F2
CS
(a)
(b)
(c)
(18)
F. Maloberti
DATA CONVERTERS
Springer
2007
Chapter 5
Rz
Vos
+
-
Vin
-A2
A1
(a)
Cc
Vout
Vos
+
-
Vin
[Vin(nT ) + Vos]A1A2
Vout(nT ) =
;
1 + A1 A2
FS
A1
Rz
Cs
28
Vout
-A2
(b)
Vout(nT )
V1(nT ) =
A2
(19)
F. Maloberti
DATA CONVERTERS
Springer
2007
Chapter 5
Use of this T&H

The use of a two stages
OTA T&H is conveniently
when input buffering is required. The second stage
gain must be large enough
to ensure a constant clock
feed-through.
29
F. Maloberti
DATA CONVERTERS
Springer
2007
Chapter 5
Use of the Virtual Ground in CMOS S&H

CS
VinA
FS
FH
FH
VCM,in
VinB
CH
- +
VoutB
FS
FS
CS
VoutA
CH
FS
VCM,in
FS
VinB
FS
VCM,out
CL
CL
FH
FS
FS
FH
FS
(a)
CS
VinA
VCM,out
FS
VoutA
+ -
VoutB
FH
CS
(b)
CL
CL
30
F. Maloberti
DATA CONVERTERS
Springer
2007
Chapter 5
31
Noise Analysis
v2
v2
n
v2
CS Ron
Ron CS
Ron
-
v2
n,op
+ -
CL
+
-
(b)
(a)
2 =
vout
4kT Ron
1 + (/T )2
(20)
F. Maloberti
DATA CONVERTERS
Springer
2007
Chapter 5
kT
kT
kT
2
+ gmRon
+
.
Vn,f lip =
CS
CL
CL
v2
Ron CS
(1)
vn2
32
CH Ron
vn2
v2
(2)
(4)
Ron CS
CH Ron
(21)
vn2
(5)
Ron
- +
(3)
(a)
v2
- +
n,op
(b)
CL
F. Maloberti
DATA CONVERTERS
Springer
2007
Chapter 5
Heq (s) = HCS (s) HCH (s) =
2
Vn,ch
=
tr
1
;
1 + 3sRonCS
if CS = CH
2kT
2kT
kT
+ +gmRon
+
3CS
CL
CL
33
(22)
(23)
F. Maloberti
DATA CONVERTERS
Springer
2007
Chapter 5
Intuitive Conclusions
The noise power of a sample and hold is inversely proportional to the used capacitances (sampling and load)
through the kT/C relationship.
The use of noisy op-amp can
significantly worsen the noise
performance.
34
F. Maloberti
DATA CONVERTERS
Springer
2007
Chapter 5
Example 5.3
Vin
v2
n,f
FH
CS
v2
FS
FS
-
n,i
Vout
os
(a)
Ron
Ron CS
vd
CL
v2 n,op
gmvd
(b)
vout
CL
35
F. Maloberti
DATA CONVERTERS
Springer
2007
Chapter 5
vout = vn,i + vn,f + vn,CS (1 + 2sRonCS )

vd = vn,op vout + vn,f + vn,CS sRonCS
gmvd = vout sCL + vn,CS sCS
36
F. Maloberti
DATA CONVERTERS
Springer
2007
vn,CS =
Chapter 5
37
vn,i(gm + sCL) + vn,f sCL vn,opgm

gm + s{CL + CS (1 + gmRon)} + 2s2CLCS Ron
2
2 H 2 (f ) + v 2 H 2 (f ) + v 2 H 2 (f ).
vn,C
=
v
n,op n,op
n,i n,i
n,f n,f
S
4kT
kT
4kT Ron (0.51 + 0.45) +
2
0.05
=
1.14
vn,C
= 2R
gm 2Ron CS
CS
on CS
S
(24)
F. Maloberti
DATA CONVERTERS
Springer
2007
Chapter 5
10
10
H n,i
10
H n,f
|Hn(f)|
10
H n,op
10
H n,ref
10
10
10
10
10
10
10
10
10
f (2R onCS )
10
10
10
38
F. Maloberti
DATA CONVERTERS
Springer
2007
Chapter 5
CMOS Switch with Low Voltage Supply

VDD
Vin
GND
(a)
gon
gon
gon
NMOS
NMOS
PMOS
PMOS
PMOS
NMOS
VDD
Vin
VTh,N
VTh,P
(b)
VTh,P
VTh,N
(c)
VDD
VDD
Vin
Vin
VTh,P
VTh,N
(d)
39
F. Maloberti
DATA CONVERTERS
Springer
2007
Chapter 5
W
W
Gon,n = nCox
Vov,n + pCox
Vov,p,
L n
L p

Vov,n = VDD Vin VT h,n;
40
Vov,p = Vin VT h,p.
(25)
(26)
W
W
= p
n
L n
L p
(27)

W
Gon,sw = nCox
VDD VT h,n VT h,p .
L n
(28)
F. Maloberti
DATA CONVERTERS
Springer
2007
Chapter 5
CS
Sin
Vin
FB
F
-
VT&H
Sb
Vlow
F
second
push-pull stage
41
F. Maloberti
DATA CONVERTERS
Springer
2007
Chapter 5
Switch bootstrapping
VDD
FOFF
S1
FOFF
S2
FON
CB
GS
S3
FON
S4
Cp
MS
IN
FOFF
SOFF
FON
OUT
FOFF
42
F. Maloberti
DATA CONVERTERS
Springer
2007
Chapter 5
VGS = (Vin + VDD )
CB
CB + Cp
(29)
CB
Cp
VGS,MS = VDD
Vin
CB + Cp
CB + Cp
"
CB
Cp
W
Gon = nCox
VDD
Vin
VT h,n
L MS
CB + Cp
CB + Cp

43
(30)
(31)
F. Maloberti
DATA CONVERTERS
Springer
2007
Chapter 5
44
S1 must be able to switch on and off VDD ;

the switch S3 must sustain the boosted voltage during the on phase;
the switch S4 must operate under the same conditions as the main
switch;
SOF F must be able to swing from the boosted voltage to zero.
F. Maloberti
DATA CONVERTERS
Springer
2007
Chapter 5
VDD
Md1
Md2
S1
FOFF
S3
M1
M3 GS
Mpo
C1
CB
C2
FON
S2
FOFF
M2
Mo
SOFF
Mi2
Mi1 Mi3
M4
S4
MS
IN
OUT
45
F. Maloberti
DATA CONVERTERS
Springer
2007
Chapter 5
FOLDING AMPLIFIERS - Current Folding

VCC
RL
RL
+
- Vout,d
Q1
Q2
D1
Iin
IE
Q3
D2
IE
Q4
D3
IE
VA
D4
IE=IFS/4
(a)
VDD
RL
RL
+
- Vout,d
M1
M2
M3
M4
M5
M6
M7
M8
VA
Iin
+
VB
IS
IS
IS
IS
IS
IS
IS
IS=IFS/8
(b)
46
F. Maloberti
DATA CONVERTERS
Springer
2007
Chapter 5
47
Vout,d = RLIin.
(32)
Vout,d = RLIE RL(Iin IE ) = RLIin
(33)
F. Maloberti
DATA CONVERTERS
Springer
2007
Chapter 5
FOLDING AMPLIFIERS - Voltage Folding

VDD
RL
RL
+
- Vout,d
MP,1 MN,1
Vin
IS
RD
VR1
IS
MP,1 MN,1
IS
RD
VR2
IS
MP,1 MN,1
IS
RD
VR3
IS
MP,1 MN,1
IS
RD
VR4
IS
(a)
VR2
2ISRL
2ISRL
VR1
(b)
Vin
VR1
VR3
2ISRD
(c)
VR4
48
F. Maloberti
DATA CONVERTERS
Springer
2007
Chapter 5
49
VOLTAGE-TO-CURRENT CONVERTER
VDD
Iout+
IB
IB
Vin
+
M1
Iout
Vin+
Vin-
(a)
M2
Iout+
Vin-
Vin+
M1
R
Iout-
Iout-
+
_
R
IB
IB
(b)
V
Vin+
Iout ' IB in+
R
(c)
(34)
F. Maloberti
DATA CONVERTERS
Springer
2007
Chapter 5
Example 5.4
RT = R +
Vov
Vov
+
2(IB + Iout)
2(IB Iout)
Vov IB
RT = R + 2
.
2
IB (Iout)
Vov IB Iout
Vin = RIout + 2
IB (Iout)2
50
F. Maloberti
DATA CONVERTERS
Springer
2007
Chapter 5
k2 = 5.95 1018;
k3 = 3.78 1004;
k4 = 4.02 1018;
k5 = 1.55 1006;
k6 = 7.83 1020;
k7 = 4.92 1008.
51
F. Maloberti
DATA CONVERTERS
Springer
2007
Chapter 5
Differential Input Voltage [V]
!1
!2
!3
!1.5
!1
!0.5
0
0.5
Differential Output Current [A]
1.5
!3
x 10
52
F. Maloberti
DATA CONVERTERS
Springer
2007
Chapter 5
VB
M7
Vin+
M1
A
M5
IB
53
M8
R
M3 M4
Vin-
M2
B
M6
IB
R/2
Aloop = gM3
gM1 Rout,A
1 + gM1 R/2
(35)
F. Maloberti
DATA CONVERTERS
Springer
2007
Chapter 5
CLOCK GENERATION
F
F1
F2
F2
1
1
F1
0
(a)
3t
3t
3t
3t
F1
1
F
F2
0
0
F2
0
(b)
F1
54

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F.

CIRCUITS FOR DATA CONVERTERS

Circuits For Data Converters

CIRCUITS FOR DATA CONVERTERS

CIRCUITS FOR DATA CONVERTERS

CIRCUITS FOR DATA CONVERTERS

DIODE BRIDGE S&H

CIRCUITS FOR DATA CONVERTERS

Diodes in the bridge

If you want ultra-speed use ... xxxxxxx

The speed of the diodes

CIRCUITS FOR DATA CONVERTERS

Diode Bridge Imperfections

CIRCUITS FOR DATA CONVERTERS

Improved Diode Bridge

CIRCUITS FOR DATA CONVERTERS

SWITCHED EMITTER FOLLOWER

CIRCUITS FOR DATA CONVERTERS

But you have to remember the ...

The bipolar or diode based

CIRCUITS FOR DATA CONVERTERS

How to fix the problem ...

CIRCUITS FOR DATA CONVERTERS

Circuit Implementation of the buffer

CIRCUITS FOR DATA CONVERTERS

CIRCUITS FOR DATA CONVERTERS

Complementary Bipolar S&H

CIRCUITS FOR DATA CONVERTERS

Complementary schemes are good but ...

CIRCUITS FOR DATA CONVERTERS

FEATURES OF S&Hs WITH BJT

CIRCUITS FOR DATA CONVERTERS

Vout+ = Vin+ VBE0 VT ln

Vout = Vin VBE0 VT ln

Ibias + AinCS cos(int)

CIRCUITS FOR DATA CONVERTERS

CIRCUITS FOR DATA CONVERTERS

Features of S&H s With BJT

CIRCUITS FOR DATA CONVERTERS

CIRCUITS FOR DATA CONVERTERS

CIRCUITS FOR DATA CONVERTERS

CIRCUITS FOR DATA CONVERTERS

CIRCUITS FOR DATA CONVERTERS

CIRCUITS FOR DATA CONVERTERS

CIRCUITS FOR DATA CONVERTERS

CIRCUITS FOR DATA CONVERTERS

CIRCUITS FOR DATA CONVERTERS

Clock Feed-through Compensation

CIRCUITS FOR DATA CONVERTERS

Two-stage OTA as T&H

CIRCUITS FOR DATA CONVERTERS

CIRCUITS FOR DATA CONVERTERS

Use of this T&H

CIRCUITS FOR DATA CONVERTERS

Use of the Virtual Ground in CMOS S&H

CIRCUITS FOR DATA CONVERTERS

CIRCUITS FOR DATA CONVERTERS

CIRCUITS FOR DATA CONVERTERS

Heq (s) = HCS (s) HCH (s) =

CIRCUITS FOR DATA CONVERTERS

CIRCUITS FOR DATA CONVERTERS

CIRCUITS FOR DATA CONVERTERS

vout = vn,i + vn,f + vn,CS (1 + 2sRonCS )

CIRCUITS FOR DATA CONVERTERS