EECS 478 Winter 2017 Homework No.

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University of Michigan, EECS Department
EECS 478: Logic Synthesis and Optimization
Professor John P. Hayes

Distribution Date: Wednesday, January 11, 2017

Due Date: Wednesday, January 18, 2017 at 5:00 pm in the 478 dropbox in BBB 1637

First Name (print) ___________________ Last Name (print) ____________________________

Unique name: ____________________ Student ID: ___________________________

Honor Pledge: I have neither given nor received unauthorized aid on this homework,
nor have I concealed any violations of the Honor Code.

Signature: ____________________________________________________________

INSTRUCTIONS:
1. Solutions should be written on a copy of these sheets, with each answer following the corresponding
question. Insert extra pages as needed, but keep your answers with the corresponding questions.
Computer-printed work is preferred, but not required. Neatness counts!
2. Put a copy your solutions in the dropbox marked EECS 478 in 1637 BBB no later than 5:00pm on the due
date. If you have a time conflict with the due date because of work, travel, job interview, etc., submit your
homework earlier. Late work will not be accepted without a serious reason and a valid written excuse,
such as a letter from your doctor in the case of illness.
3. To ease handling, fill in all the requested information in the box above. Print your name clearly since
students may have the same first or last names. Staple all your sheets together and do not fold them.
4. Explain all your reasoning (show your work) and state any non-obvious assumptions you make. Also
identify any special references you use, such as Internet sites, books or papers.
5. You should not work in groups on the EECS 478 homework; these are all individual assignments.
You should not discuss your solution methods or your answers with other students. You should
not copy solutions from any sources. The solutions you submit must be your own. Any suspected
violation of this instruction will be reported to the CoE Honor Council.
6. Complete homework solutions will be provided after the graded homework is returned. Any request to
have your homework regraded must be submitted with a full written explanation within one week from the
date on which the graded homework is returned.

GRADES

P1 ____; P2 ____; P3 ____; P4 ____; P5 ____; Max. 100 points

Your Grade: ____________

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This homework assignment focuses on prerequisite material for EECS 478.
Problem 1 [20 points] CMOS logic

(a) [10 points] Consider the CMOS transistor circuit C in Fig. 1 below, where only the internal structure
of the pull-up subcircuit NPU is shown. Using any method, determine the logic function z(a,b,c,d,e)
implemented by C. Give your answer by filling in the truth table for z.

1 a b c d e z a b c d e z
0 0 0 0 0 0 16 1 0 0 0 0
NPU 1 0 0 0 0 1 17 1 0 0 0 1
2 0 0 0 1 0 18 1 0 0 1 0
d 3 0 0 0 1 1 19 1 0 0 1 1
4 0 0 1 0 0 20 1 0 1 0 0
a
5 0 0 1 0 1 21 1 0 1 0 1
c 6 0 0 1 1 0 22 1 0 1 1 0
e
7 0 0 1 1 1 23 1 0 1 1 1
8 0 1 0 0 0 24 1 1 0 0 0
9 0 1 0 0 1 25 1 1 0 0 1
10 0 1 0 1 0 26 1 1 0 1 0
e 11 27
0 1 0 1 1 1 1 0 1 1
b 12 0 1 1 0 0 28 1 1 1 0 0
13 0 1 1 0 1 29 1 1 1 0 1
c d 14 0 1 1 1 0 30 1 1 1 1 0
15 0 1 1 1 1 31 1 1 1 1 1
z
NPD

Fig. 1
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(b) [10 points] Design Cs pull-down subcircuit NPD, assuming it is composed entirely of NMOS
transistors. Use as few transistors as you can; for maximum grade you must use the minimum number of
transistors. Your answer should be a transistor circuit diagram for NPD in the same style as NPU above.

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Problem 2 [20 points] Combinational logic design [Based on Kohavi & Jha Prob. 5.17]

Fig. 2

Fig. 2 shows a circuit M for multiplying two unsigned two-digit binary numbers. The digits of the input
numbers are designated a0, a1 and b0, b1, while c0, c1, c2 and c3 designate the digits of the product. Thus
C = A B.
(a) [10 points] This problem is to design a logic circuit that implements M. Assume that the gates available
are AND, OR and NOT gates, and that a gates cost is equal to its fanin. Thus, an inverter has cost 1, a
two-input AND has cost 2, etc. Design a suitable circuit for M whose cost is as low as possible. Your
answer should include a circuit diagram and minimal sum-of-products Boolean expressions for each of
the four output functions. Also specify the circuits total cost Cost.

(b) [10 points] Now suppose that you have an additional design component available in the form of a
half-adder HA. A half-adder has two inputs a and b, and two outputs s (sum) and c (carry). Assume that
HA has cost 8. Now find the lowest-cost design for the multiplier with ANDs, ORs, NOTs and HAs as
your components. Give the corresponding circuit diagram and specify its Cost.

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Problem 3 [20 points] Boolean algebra
(a) [12 points] For each of the following Boolean functions:
(i) (a b)c
(ii) (a + b) + c
(iii) a + b + c + d
(iv) a + (b + c ) + d
determine all its minterms and list them as a sequence of decimal numbers i,j,k,... .

(b) [8 points] Consider again the Boolean functions defined in Part(a). Express each of these functions in canonical
product-of-sums (POS) form.

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Problem 4 [30 points] Sequential circuit design
Lecture 3 outlines the design of a sequential circuit SM3 that multiplies an unsigned binary number N of
arbitrary length by 3, where N is entered serially on input line x, least significant bit first. The result 3N
emerges serially on the output line z. This problem is to design a similar serial multiplier SM5 that
multiplies N by 5 instead of 3. The final circuit should use D flip-flops and NAND gates only, and should
have as few D flip-flops and NAND gates as possible. For simplicity, assume that all NAND gates have
the same cost, independent of the number of inputs. Use the classical low-level design approach.

(a) [5 points] Construct a neat state-transition graph (state diagram) for SM5. Label your states S0, S1,
S2, On the side, write down the meaning of each state, i.e., what circuit condition does in represent?
Add comments if needed to make the state behavior very clear.
(b) [10 points] Construct an excitation table for your design in the same style as SM3.
(c) [10 points] Derive a two-level design for the combinational part of SM5 that uses a minimal number
(or for slightly less credit, a near-minimal number) of NAND gates. Show all your work.
(d) [5 points] Construct a neat logic circuit for SM5.

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Problem 5 [10 points] Programming prerequisites
This problem is to implement in C++ a function path_sum_equal_to(Node* root, int value) that checks, in a
binary tree, whether there is a path from root to leaf where the sum of values of all nodes along this path equals a
specific value. For example, for the following trees root, if we call path_sum_equal_to(&root, 14), for the path
7-4-2-1, the sum is 14, thus the returned value should be true. However, if we call path_sum_equal_to(&root,
13), there is no path that sums to 13, so the function call should return false. You may assume that the sum of
values does not overflow. [Hint: It may be easier to write your solution as a recursion.]

class Node {
public:
Node* left_;
Node* right_;
int value_;
Node(int key) : value_(key), left_(NULL), right_(NULL) {}
Node(int key, Node* left, Node* right) : value_(key), left_(left), right_(right) {}
}

bool path_sum_equal_to(Node* root, int value) {