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    Solutons Gaonkar Microprocessor PDF

    Uploaded by

    Loki Shaw

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    © All Rights Reserved
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    of 35
    PART I: SOLUTIONS CHAPTER (Components of a computer: ALU and Control Unit (CPU), Memory, Input, ané Output. Functions of various components: CPU: It processes and stores binary data, wansfers data from and to memory and VO devices, and provides timing to all the operations. It includes ALU, register arrays, and control unit. ‘The ALU performs the arithmetic and logic operations, and the control unit provides timing. ‘Input - provides binary data as an input to the CPU. Output - accepts binary data from the CPU. A microprocessor functions as the CPU of a microcomputer, and includes the ALU, register arrays, and the control unit on one chip; it je manufactured using the LSL technology. On the Sther hand, the CPU is designed with various discret boards, Functionally, both are simian: however, technology and processes used for designing is different A microprocessor is one component of a microcomputer, and the microcomputer is complete computer consists of a microprocessor, memory, input, and output ‘See Summary: Scale oF Totagration Four bytes. “The machine language of the 8085 are the comamands to the microprocessor given in binary. ‘These are the binary instructions the processor can uncerstand and execute. ‘The assembly Ianguage comprise ef mnemonics (group of letters (o represent commands) assigned by the manufacturer For the convenionee of the users, 9, 10, 11. See Summary: Computer Languages 12. ‘The assembly language mnemonics represent instructions to the microprocessor; therefore, ‘hen they are wanslated into machine language. there is one-to-one correspondenc= between the mnemonics and the machine code. The assembly language programs are compact, require less memory space, and are efficient. ‘The high level languages arc written, in English- like statements, and when these statements are translated in machine language. the ‘object code tends to be large, and requires large memory. ‘The execution of the programs ‘written in high level languages is less efficient than that of assembly language programs 15, 14, See Summary: Computer Languages 15. 16. ASCII codes in Hex: A= 41, 5A, snd m=6D s Summary: Computer Languages CHAPTER? is 2 10 12 ‘Memory Read, Memory Write, VO Read, and YO Write A bus is group of lines (wires or conductors) which carry digital information. “The fiction of the address bus sto camry binary adress of a memory Jocation or an YO device. The address bur ig unidirectional, and the inforaation flows from the MPU to peripherals and memory “A microprocessor with 14addeeas lines is capable of addressing 16K (2) memory ovations 21 adress Lines, ‘Data bytes are transfered in both directions between the MPU and memory/peripherals, TOR (VO Read), IOW (VO Write), MEMR (Memory Read, sad MEMW (Memory Write) 1m memory write operation, the control siznal required is MEMW, and the direotion of the data flow is fom the MPU to memory. “The accumulators an §-bit register anditiea partof the ALU. All8-bit arithmetic and logic ‘operations are performed in relation to the accumulator conient, and thereeult is storedinthe steurnulator (with a few exceptions) A fing is the output of a given Mip-flop to indieate certain data conditions. ‘The program counter and the stack pointer store memory sddzesees of 16 bits. ‘The program counter always points to the next memory location; thersfore, the content of the program counter will be 2058H, 128 registers and 128 X 4 = 512 memory cells 1024 bits are can be stored by this chip; however, it can not be specified as a 128-byte _memary chip because the byte indicates S-bit memory repisters; this chip has 4bit registers. 1s, 16. 16 18. 21 2, Fs 24, 2s. 26. 28 29, 30, 3. 32. 33, 34. S-bit word size 8 chips. A chips. 32 chips. ‘The WR signal enables the input bulfer of s memory chip 90 that information ean be stored (oritton) in the Selected memory register 1 adress Hines, 16 pages and the last location is 2FFFH. ‘The stating address is FBOOH, end the memory map is PROOKT to FRFPEL “The staring address ie: EOOOH, ‘The address ranges ftom FFOOH to FEFFEL “The address ofthe selected register: 1000 0000 0100 0111 = 047H ‘The memory map ranges fkom 200011 to 23FFH. ‘The address of the selected register: 0010 0000 1111 1000 = 20% 8 adress lines are required for a peripheral VO port, and 16 address lines are required for 8 memory-mapped VO port ‘Tri-state dovicos are logle devieet with three states; the ted tate ie high impedance. Ina ‘bus-orlented system, devices are connected in parallel, and the buses are capable of driving fone TTL logic device. The MPU communicates with one peripheral st a time, and odor ‘penpherals are placed in igh impedance to svoid bus loading, “High impedance tae From to. ‘None. The decoder is not enabled: all outpet lines will be high, “The line 6 (0 (001 (Complement of 10) 35 36. 3. 38. ‘A transparent latch ga flip-flop; its ourput changes according to input when the clock signal ig high, and it latches the input when the clock goes low. The latch [s necessary for output dovicos to rotain the result otherwise, the resue will disappear. “The high-order address lines: A12-A1S, the low-order address lines: AO-A10, and the don't care line: ALL ‘This answer assumes the memory chips are 2048 X 4 AIS AIA AI3 AIZ ALL ALO AS ASAT AG AS A4.A3 AZ. AL AG 1 1 1 10 000000000 0 o=F000H 1 1 bop bo bp aad dab td PRR ‘The memory occupies the memory space from FOOOH to FFFFH. The don't care line Al ‘generates additional address range. This is a 2K memory chip that oceupies 4K of memory Space in the map, thus wasting 2K of memory space. IF A11 is assured to be at logic O as in @. 27, the address range is: FOOOH to F7FEH and if tis assumed to be at logic 1, the fddress range (also called foldback memory space) is: F800H to FFFFHL, CHAPTER 3 “The ALE signal goes high at the boginning of each machine cycle indicating the availabiliey ‘of an address on the address bus, and the signal is used to latch the low-order address bus. ‘The IO/M signal ie a satus signal indicating whether the machine cycle is VO or memory ‘operation. ‘The TO/M signal is combined with the RD and WR control signals to generate TOR, 1OW, MEMR and MEMW control signals. “The low-order bus AD7-ADO is used for two purposes. In the carlicr part of a machine cele, the bus is used forthe low order address of a memory location the 8085 is accessing. land in the latter part of the cycle the bus is used for data. By demultiplexing the bus, he ‘Midrese and the data are kept separate. {In Fig. 3.22, the input signal RD ané WR cannot be low atthe same time. Therefore, the ‘Valid combinations ofthe input signals are: n 2. 13. 14. OM RD WR Output Signal 2 © 0 invaiia 2 0 3 MEM 2 1 0 Oo, Mew 0 1 1G Erelevant 16 0G nvata 10 1) 6 10R 1 1 6 & Tow P11 Os elevant See the answer of Q3. RD and WR cannot be active simultaneously Mand RD active Mand WR active Both RD and WR are inactive [RD and WR cannot be active simukaneousty TO and RD active 10 and WR active Both RD and WR are inactive In Fig. 3.25, the 7418139 is enabled when IO/M is low. Therefore, the following memory ‘contol signals can be generated. ‘The output of the latch will be OSH; however, it will be not be latched until the ALE goes low. ‘The output of the latch is OSH. At 72, the ALE is low; therefore, the latch will not be ‘enabled, and it will continue to hold the previously latched byte (OSI. ‘The crystal stoquency should be ~ 2.2 MEz because the oscillator logie divides the input Frequency by wo. See the steps on page 66/67, Example 3.1 ‘The sum of 87H 79H = 100K. Therefore, the accumulator will have OOH, snd the flows willbe 0, C¥ = 1.2=1 20601. The program counter always points tothe next mechine code to be fetched. IST X 2 micro-tce = 3.6 micro-see, (AIS-A8) = 2081, (AD7-ADO) [RD and JO/M are asserted low. as 47H, (PC) = 2076 19, 20. a 22, 23, 25, 28. ‘The second machine eycle is Memory Read; the processor reads the contents of memory in register B, apd the contol signal is RD, “The fourth machine cycle is Memory Read; the processor reads the contents of memory in the accuanlator. (A1S-A0) = 20501 (AD7-ADO) as data bus = Contents of location 205014 (Refer to Instruction Sot on pages 696-699) UBB = OF (Opeode Fetch) ‘ADI 47H = OF, MR (Memory Read) STA 205011 = OF, MR, MR, MW (Memory Write) PUSHB = OF, MW, MW. ‘Memory map: 6000H to 6FFFH ‘Memory map: 8000H to SFFFH_ OR gate Connect RD to OF of the memory chip and IOMM to R2 of the decoder AISAISAISAIZ AI] AIO A9 ABA7 AGAS AS AS A2 AL AO 0 0 1 6 1 © 60000 00000 =2800% 1 I boat a aa ata eer ‘Total range 16K. Map = S000H to BFFFEL A data byte entered at location 2100H will be accepted and stored at location 2000H. The ‘adarees lines A 10, AO, and AS aronotbeing used for memory addressing: therefore, they ean ‘assume O oF 1 (dont care) logie state wich sevults into multiple addresses forthe same ‘memory locations ‘Memory address: 0800H-OSFFH, and the foldback memory ranges from 0900 to OF FFE. ‘Memory map: 3800H - 3FFFEL {In Figure 3.19, three lines are dant care which can have (2) eight combinations. This the ‘memory chip Will occupy the memory space equal to citht tes is ize ROMI: 0000H - LFFFE, ROM2: E0001 - FFFFH, R/WMI: 8000 - $3FFH 30, Meimory map: 8000H to 83FFH (Assume all dan care lines at 0) FFoldback Memory: 84001 to SFFFH 31. ‘The address range: O000H to 3FFFH 32, The addvess range: 4000H to 7FFFH 33. The primary address range: 0000H to 1FFFH (Assuines A13 ~0) “The foldback or the misror address range: 2000H to 3FFFH 34. The minor address range: S000H to 9FFFH 35. Theaddress range when 1 is asserted: 4000 10 7FFFHL 36. Thetotal address range is: 4000H to BFFFFH. For a 16K memory chip. when A141, the address ranges ftom 4000H to TFFFH as in Q. 35. When Ald —U. the address ranges 8000H to BFFFH. Fora 32K memory chip, itis accessed either by YI or ¥2; therefore, the address ranges from 4000H to BFFFH, 37. The opcode fetch eyele begine immediately after MEMW signel Ist MEMR —-> opeode fetch of the JMP instruction. 38. The last MEME ie the third byte of the STA instruction. Itseads FFE CHAPTERS 1, Thenumber of output ports in the pripheral VO is restricted to-256 ports because the operand ‘of the OUT instruction is 8 bits it can have only 256 combinations. 2 Yee 3. The 8085 differentiate between the input and the output ports af tae same address by the ‘control signal. The input port requires the RD and the output ports requires the WR contol signals 4. WR Gow) and 10M Ghizh), 5. Pulse going from high to low. 6. Trailing edge. 10. 12 14 15, 16. vy. 18. 19. 20. 22, Each LED roquires 1040 19 mA current for proper illumination. The latch cannot supply the ‘necessary current when the output is logic high, bur it ean sink the necessary current when the logic level is low. RD (low) and JOM ¢high). ‘A latch is necessary to hold the ouput data for display; however, the input data byte is Ghiained by enabling a tri-state buffer and placed in the accumulator. RD, WR, and JOM (low). No 78H, No. An output byte willbe displayed temporarily until dhe WR signal is setive, and then, it ‘will disappear ‘Memory-mapped VO. LE is enabled when 1O/M is low. ‘80000. Assuming A3 ~ 0, port address = FUH. 147 = 0, port addvess = 75H, and IFAT = 1, address = FST, IFIOAMis connected to /E1 (active ow), it will bea memory-mapped VO. The port adress oorsH Replace OUT FSH by STA 0OFSH MYA, COH ;Code for'” OUT FEE BLT tn! 19, replace the code COH by the code for letter T. (Code for = 89H. 1-7 is replaced by 1O/M signa}, the circuit will have dhree don't care adress lines: A7, Ad ‘and AS resulting in eight different addresses, IEAT =O, the addrestes aro: 04H, OCH, 14H and 17 IA? = 1, the addresses are: £41, SCH, 93H, and 9CH (as shown in Section 4.34), “The port will be a memory-mapped UO with an address = 0OFEH. 22. 29. Port A = Memory-mapped Ourput Part ort B = Memory-mapped Input Port Both are memory-mapped VO ports. Assuming the address lines A15-A8 are atlogic 0, Por, A.and Port B will be OO8ST, In Figure 4.10, he ouput OS is enabled by the address which is active for three T-states, On the other hand, she JOW signal requires WR signal which is active for approximately one and half T-states, a Machine Cycles: M1 M2 M3 INBAH OF MR 10RD IMP START OF MR MR b.207 X05 = 10 micro-tee ©. Six times, 4.10 micro-see (from beginning to th next beginning) ‘© Thereisno WR pulse in theroutine. JOM high orIORD can be used to ayne the scope, ‘2 Machine Cycles: Ml M2 M3.MA LDA FFFOH OF MR MR MR STA FFFSH OF MR MR MW MOV B.A oF IMP START OF MR MR b. FFFOH RD =11 times and WR = 1 time, 4. 407 X 0.5 mioro-tee = 20 micro-see. In Figure 4.18, the address line Ad is don't care, ‘Assuming AS ~ 0: Input Port = 2FH and Output Port = SEH ‘Assuming A4 ~ 1; Input Port ~ 3FH and Output Pest = 9FH. START: IN| 2FH Read iaput port ANI 00000011 Masi all bits exeept D1 and DO JNZ START ——f'e switch is open, read azain MVE A.00, {This imstriction i unmocessary ‘Used here for elanty 30. a our srH HLT START) IN 2FH ORI 111111008 MOV B,A cer FR JZ START Mov A.B our sr HLT START) IN aFH ANI 000000118 iz START cua OUT sFH BLT sTum on all LEDs ‘Read input pore |Setall bite from D2 to D7 Save reading in B ‘Check whether both switches are open LIthoth switches are open, read agsin sGet initial reading sTum en corresponding LED Read input port {Mack all bits except DO and D1 {Af both switches are open, read again [Make all voadings 1 except which is open ‘Tum on corresponding LED ‘The address of the atch enabled by Y3 = FSH and the address ofthe latch enabled by Yoo Fath MYIA, 98H Common anode code for"? Our Fst ‘MVIA, FSH ;Common anode code for'™ Our rat BLT PART Il: SOLUTIONS CHAPTERS 1. ‘The foureategories of instructions that manipulate data are: data transfer (copy), arithmetic, logic, and branch. ‘Tae tsk to be performed is called the opcode (operation cod), and the data to be opersted fo is called the operand Which may be specified as data, register of address. Opcode: MOV and Operand: HL 3. ‘Themachine code: 01 100 111 = 6781 4. (@)2647H OPCODE ~ MVI_ OPERANDS =, 4731 (b) COFSH OPCODE = ADI_ OPERANDS ~ A GMPLIED), FSH (©)9IH_ OPCODE = SUB OPERANDS = A (IMPLIED), C 5. (@) HEX ~325020H OPCODE=STA OPERANDS 205011 () HEX =C270208 OPCODE=INZ OPERANDS = 2070H, 6. The SUB A instruction clears the accumulator. Z=1, CY 7. INSTRUCTION ADDRESS HEX MMVI BAFH 2000 o6ar MVE C78 2002 O78. MOV A.C 2004 79 ADD B 2003 80 ‘our o7a 2006 D307 HLT 2008 76 & INSTRUCTION ADDRESS HEX MVI ASEH 2020 sReF MVI BSS 2022 0608 SUB B 3024 90 ANI OFH 2025 E6OF STA 20708 2027 327020 HLT 2mA T6 9, INSTRUCTION ADDRESS HEX 1 12, START: IN. F2H 2000 DRE? CMA. 2002 2F ORA A 2003 BT az START 2004 CAo020 Logical steps to add two Hex numbers: Load A2H! in one register. [Load 18H in second resister. Copy A2H in the accumulator ‘Adi the contents of the second r End of the program. ‘the accumullator. MIB, AH MVIC, 18H MOV A.B ADDC HLT Register contents: Initial: B=28H, A~9THE ‘After the execution : A~28H, B=28H, C=28H InQ. 6, ifthe code O7H (port address) is omitted, the processor assumes the opcode ofthe ‘next inatruction 76H (HLT) as the addresa of the output por: outputs the contents of the Sccumulator to the address 76H, and continues to the next code. After thenext code, results {Bre indeterminate 4s Q. 8, iF the byte OFH is omitted, the processor assumes the opcode 32H of the next {newuction (STA) as the socond byte of the ANI instruction. The processor isa sequential ‘machine, i assumes the aext code 20H (the low-order address of 2070H) as the opcode of ‘the next insction and continues. CHAPTER 6 ‘Section 6.1 Data Transfer (Copy) Operations 1 ApecpDps z cy MvIA.00 00 NA NA NA MVIBFS 00 FS MOVGA 00 FS 00 MOV DB 00 FB 00 FR HLT MYIC. 6511 MVLA, oo OUT PORTI ;Display 9211 MOV'A,C OUT PORTO :Display 65H HLT 4 Nom OUT 00H Display data trom input port O7EL IN 0st MOV B, A ;Store data ftom port O81 HLT sso 6 son 7. Both wit be 80H ‘Section 6.2: Arithmetic Operations 8 ABS Zz cY oo FF Oo 1 oO MVIAF2H 2 FF NA NA NA MVIB.7AH FZ 7A NA NA NA ADDB 6C 7A.0. 0 1 OUTPORTO 6C 7A NA NA NA aur 9. The instruction ADD A will add the content ofthe sccumblator to Steet this is equivalent to multiplying by 2 30. Theinstruction SUB A will clear the accumulator, The flag. status will be: CY -0,2~1. n. Ac szce xx XK 000 0 MVIASEH SE XX NANA NA ADIASE 00 XX OL 13, 14 16 18, MOVC.A 00 09 NANANA HLT MYTA.3AH ADI Asi ‘OUT PORT# HLT MYIA,00H (A)= 90000000 per «’ oo000001 OUT PorT# — BLT x iii a= FFH ‘The instruction DCR does not set the CY flag. A= 95H $=1 CY=0 ‘The flag has no significance when subtracting unsigned numbers. Ifthe the CY fag is ei, it indicates a negative result. AB S Zz cy SUBA 09 o 1 0 MOVB,A 00 00 NA NA NA DCRB’ 00 FF tO NA INRB 000 = s(t ONA SUIOIH «FF 0001 0 7 HLT SUBA Clear acumutator ADLATH sursait our PORTO Display result (47H-928) “ADI 64H our PorTi 471 = 01000111 2Com.= 01101110 tn 1 10110101 ~BSH Borrow flag (CY) is set oat = 01100100 ‘w indicate neganve results, 1 0001 1001 = 19H Borrow Magis deleted by the CY of the result. (PORTO) = BSH and (PORTI)= 19H 29, Ue number is added before clearing the accumulator, the result will include the residual ‘contents of the accumuletor. ‘Section 6.3: Logic Operations 20, The instruction XRA A clears the accumulator, and the Mag status is: CY ~ 0, 2 = 21, The instruction ADD B sets the CY Mag, but the instruction ORA A resets the CY fag, A=00 S=0 Z=1 cY=0 23. The instruction ORA will set the flag without affecting the content of the accumulator 24 ABS zo XRAA 000 1 MVIB4AH 00 4A NA NA NA SulMeH BL aA TDD AXNAB 00 4A 0 1 oT aur 26. MVIC, ABET MOV A.C ANIOFH :Masking byte to mask D7-D4 Sur pore HLT 27, MVID, SEH ANLOFH jMask D7-D4 MOV D, A" :Save ind MVIE, F7EL ANI OFH | ;Mask D7-D4 of tecond byte XRAD "Exclusive OK masked bytes Our Porro BLT 28, MVIB, STH MVIC, 878 MOV A.B ANIOUHT— :Masic all bits of 01H exeept DO MOVB,A Save DO from frst byte MOV A,C ANLOLH — ;Masi all bits of 87H exeept DO NAB AND bits DO of 91H and 87H 20. OUT PORT! ;Turn on/off light connected to BO aN o7H CMa Complement data from port 7H ORAA Set flag iPall switches are open i Continue i i ‘Section 6.4: Branch Operations 30. 3. 2 33, 34, 35. 36. 2st In the following program, explain the range of bytes that will be displayed at PORT2 for various values of BYTEL MVI A, BYTEI MOV 5, A. Sur son JC DELETE, MoV A,B SUI SoH ICDSPLAY DELETE: XRAA OUT Portt DSPLAY: MOV A.B out PoRT2 HLT Jn this problem, all bytes om 5GH to 7FH will be displayed st POPRT2. “The address of the output port ~ F2H, AMl positive signed mumbers and zero will be Sieplayed at port FE. i “This routine displays the absolute value (magnitude) of BYTE son 38. START: MvI D.9BH MVI EAT Mov.AD ADD E. Jc pspay ‘our oon BLT DSPLAY: MVI Aomnt Our oor BLT XRAA Clear CY MVIB, FF INRE MOV A,B INC DSPLAY MMVI, O1n DSPLAY: OUTFORT# — ;Tho output= UH because INR docs not ELT fect CY fing ‘To clear the CY flag, the instructions such as ANA A, SUB A, ORA A can be used instead ofthe instruction XRA A. ORAA Clear CY MVIC, FH MOV A.C Abr ont INC DSPLAY Mavi a, orf, DSPLAY: OUT PORT# The output = OTH because ADI sets CY HLT iaas, MYIB.BYTEr MVIC, BYTE? MOVA.B SUBC JNCDSPLAY Jump if result is postive cua ‘Flake one's complement ADIOMH Find two's complement DSPLAY: OUT PORT! LT ‘Section 6.6: Debugging a Program AL, Reference: Section 6.53 2000 ‘ORG 200011 2000 BFL START: INOFIH 2002.47 MOVE, A 2003 DRE2 IN OF2H 2005 Esso ANI GOH 2007 a Mov c, A 2008 78 MOV A.B 2009 E680 ANT SOH 2008 ai ANAC 200c €21720 xz SHTDWN 200F 78 Mov A.B 2010 oir ANUIFE 2012 DaFa OUT oFsH, 2014 €30020 IMP START 20173540. SHTDWN: MVIA, 40H, 2019 Dara OUT OFS 2018 76 HLT doie END 42, Inthe following program, the instructions IN FI and IN F2 are replaced by loading two data ‘bytes 97H and 85H in registers D and E respectively 2000, ‘ORG 20008 2000 1697 START: MVID,BYTE! ;Simulate data stom pore Fi 2002 1285 MVI ESBYTE? ‘Simulate data from port F2 2004 7B. MOV AE 2005 E680 ANTSOF Mask S6-S0" 2007 SF MOVEA "iSave S7 2008 70, MOV A.D 2009 E680 ANI BOE ‘Mask $6-S0 Doon A3 ANAE, [Check S757 200c €21720 INZSHTDWN —_HIES7.& S7-aro.on, jump to lntiate shut down procedure 200F 7A Mov AD ‘not, get data from port FL 2010 oir. ANLIFL ‘Mask bite D7-DS 2012 DFS ‘our PORT ‘Turn conveyer belts 2o14 c30020 IMP START 2017 3540 SHTDWN: | MVI.AAOH :Secbit Dé=1 3oi9 bars OUT PORT ‘Tues on emergency doin 76 ELT 0097 = BYTEL EQUS7E 28 aoe QU ssH OU OF3H END 43, "This program tums on the LED indicator when the switch S7 ison. 2000 2000 DBF START: 2002.47 2005 E680 2008 78 2009 E680 2008 D3F3 2010.1 2011 €21¢20 201478 TURNON: 2015 Beir 2017 DSF3 2019. C30020 2o1C3B40.— sieTDww: 201E DSF3 2020 76 CHAPTER? ORG 20008 INGFIM. ;Comments are same as illustrative MOVB.A program ~ omitted here IN ora ANI SOE MOVC,A Saves MOV AB ‘Getdata fiom port Fl ANT 80F Jz TURNON IFS? =0. turn on belts OUT OF3H Tum oa LED to incicate $7 is on ANAC Check STand'S7" NZ SHTDWN, MOV AS AND IHL Our ors IMP START MVLAOH jLoad byto to tur off belts end turn on emergency OUT OFS END “The following programs assume the systems R/W memory begins a location 2000H. The symbols 2OK in the assignments are assumes as memory page 204 Section 21 See Figures 71,72, 7.3, & 7. Section 7.2 ps. 81 5, Location 2075H will contain F7H. 10. 12 13. 14, 16. MVE CFE EXT #.2070% LXL_D2070H MOV MC LDAXx D FF A=FFH (20708) = FFE 207SH and 2076H A= 00H D=O00H HL=209FH Clears Loestions 2090H 19 209FH LxI 820908 SUB A MVI_DoFH Loop: Stax INX B eR 'D NZ. LOOP Hr 0 0 ® = - FE 20 70 30 FE 20 70 20 FE 20 70 20 FE 20 70 20 adees Infinite loop. DCX instruction docs not affect Z fag. Times, DCX instruction docs not affect Z flag. START: LXTH, 2055H XID, 20854 MVIB, 0st NEXT: MOVAM STAXD INK, Dex DCRB INZ NEXT HLT START: LXIH, 205FH index for data source fIndex for data destination, starting st last location Byte counter iGet data byte {Store data byte inex location, {Ufeounter is not 0, go back to transfer next byte sIndex pointing to last source byte index for destination 18, START: START Loop: SKIP: START: NEXT: MVIB, 10H MOV A.M STAXD DeXH DCRB NZ NEXT HLT LxIH, 20608, XID, 20808 MV15, ost MOV A.M STAXD INX HL INXH DCRB NZ NEXT HLT MVI BS XI #20508 xt D’2050% MOV AM ORA A INZ SKIP STAXD INx D IN HL Der B INZ LOOP HLT ‘LXI D, 20601, MV1 G. ost MVIB, 00H LDAX'D ADDB MOV B, A INXD. DCR C JNZ. NEXT our PoRTI BLT sNewt count Jndex pointing to low-order reading ‘ndex for storing low-order reading, ‘sCounter for emp. readings sGet reading {Store low-order reading sPoint to next low-order reading sNext count :BYTE COUNT ;SOURCE SDESTINATION IGET BYTE STEST IT FOR ZERO :NOT ZERO, SO STORE IT :GO ON TONEXT. fndex for date !Counter for data {Clear B to store partial sum sAdd data byte [Save partil sum Next count Display sem For the given five bytes, the sum is B7H 20. START: LXTH, 2060 dlndex for data vi cost Counter for data Mv, oon {Clear B to store partial sum NEXT: MOV A.M ADDB 5c CARRY At-sum > FF, display OL MOV, A, Save pardal sum DCR Next count SNZ NEXT our PorTt Display sum BLT CARRY: MVLA, ora Our PORT! ALT First set display = O1HL ‘Second set dsplay = AFH. 21. Clear register D to count the aumber of bytes added and insert the insmiction INE. after the instruction JC CARRY. Display the contents of register D at PORT? at the end, First set display = 3 and Second sct display = 5 Section 2.2: 22, Locations 2070H to 2074H will contain O1H, O24, 03H, 04H, AND 05H 23 A HL SZ CY M20ssH LxI #20554, 2055 NA NA NA MVE MAH 20 55 | | | BA MVI A76H 3 20 $5 | | | BA ADD M 00 20 55 0 1 1 BA STA 2055 00 20 55 NANA NA 00 HLT 25. $=0 Z=1 CY isnotattected CNA), 26. START: LXID, 20501 {Setup index pointer EXT, 2040H ‘Point to counter location in memory MVIM, 06H [Load counter with the count XRA A {Clear acoumulator MOVC,A {Clear C to save partial sum 28. 29. MOV B.A NEXT: LDAXD ADD INC skip INRE SmIP; INXD NX DCRM INZNEXT. our Port: MOV A,B OUT PORT? HLT START: LXID, 2050 (Da, 20608 MVIC, 05, NEXT: LDAX'D MOV 3B, M SUBB JC SHTDWN INXD INK, DER C INZ NEXT Mvr A, ou OUT PORT] BLT SHTDWN: MVIA, OFFH ‘OUT PORT ELT sClear B to save carrye sGer daze :Add previous partial sum Bifne earry, do uot increment CY register nerement carry register Point to next byte fall numbers are not yet added, get the next byte Display sum Display CY register Set pointer for readings of furnace 1 {Set poimter for readings of furnace 2 et Up counter to count five readings {Place temp. reading from furiace Lin A {Place temp. reading from furnace 2 in B E(B) > (A), jump to display emergency Point to next memory locaton Decrement reading count Add, after the statement JC SHTDWN: INZ NOTEQ MMVI A.soH OUT PORTI NOTE: continue START: Ext 1.20701 MVI BA Loop: | MOV AM INx ‘ADD M Dex 1 sf they are not same, skip Uf they are, load byte to tar on D7 Tum oa bitD7, SDATA LOCATION (NUMBER OF PAIRS: SGET FIRST BYTE OF PAIR, SPOINT TO SECOND BYTE [ADD 2ND TO IST. ;POINT TO LOCATION TO STORE SUM SNOTE: DCX AND INX DO NOT AFFECT CARRY ery a START: oor: START: Loop: ‘Section 2.4: 32, (A =6FH, CY=1 33. MOV M.A INX MYL AO ADC A.A MOV M.A INX H DeR B JNZ_ LOOP HLT x1 #20701 XI D.20708 MVE Ba MOV AM INX H. SUB M STAXD INX DCR INZ Loop Lx 4.20708 Da D 20708 MMVI Ba MOV AM INx HE SUB M ae Skip STaxD INx D INX H DCR B INzZ LOOP a MVI AsoH 80. Ona A RAR 80. :STORE suM POINT TO CARRY POSITION SGET CARRY INTO A, !STORE IT TO 2ND LOCATION POINT TO NEXT PAIR INEXT COUNT, HF COUNT IS NOT ZERO, GET NEXT PAIR ‘Data location. {Storage location Inumber of paice [Get fret byte of pair Point to second byte {Subtract 2nd from Tat {Store sum Bump sum pointer Point wo next pair Decrement court Ge back for next operation Data location {Storage location sNumber of paice \Get first byte of pair Point t second byte {Subtract 2nd from Ist ‘Shop if< 0 agaive) unsignes Bump sum pointer ;Point to next pair Decrement count Go back for nent operation () A= 6EH, CY=1 bz icy 1 0 0 o 1 4 24 35 37. 29. @ A cy @ Mvr acs 65 ora ‘A cs 0 RAL sat RRC as 0 A cy MVI AATH AT Oa X a7 0 RAR aE 1 RAL aro ‘These instructions will move the MSD of a BCD number (7 i this cass) ftom 10th to the 1's phce. AWO7 (@) Muniply by? (@) Divide By 4 Mutuply by 20. START: MYID, oan Lr, 20608 MVIC, oor MOV B,C Loop; = MOV ALM JM NEXT ‘ADD.C Mov ca. INC NEXT INRB. NEXT: INXHL Der D INz LOOP, MOV A.C ourrorrt MOV A.B ‘our poRT2 HLT et up counter to count ten seadings {Set pointer to date location Clear resister C to save partial sam Clear register B for cay sGet current reading Set flags HED? = 1, reject the data byte {Ada the current reading. |Save partial sum of the readings ‘If no carry, do not increment (3) JAdd 1 to previous carry count iGo to next data location Next count Go back to gat next reading {Get the final sum Display low-order byte of the sum iGet the carry count Display earry count For the given set of readings in assignment 38, the sum ~ 2A0HI START: MVID, DAH LXLH, 20608, MVIG, OOF MOV B.C MOV E,C. Toor: MOVALM ORAA IM NEXT INRE ADDC {Set up counter to coumt ten readings {Set pointer to data location ‘Clear register C to save partial sum ‘Clear register B for enmry ‘Clear regi. Eto count positive readings iGet current reading Set Tags HED? = 1, reject the data byte Positive reading found; count it JAdd the curtent reading, 40, Moy ©, A, INC NEXT INRB NEXT: INXH DCR D INZ LOOP MoV A.C OUT PORT! MOV A,B. OUT PORT2 MOV AE. OUT PORTS BLT START: LXID, 20608 XI, 2050, MVIC, os Loop: MOV A.M ORAA IM NEXT RRC 3c NEXT Ric STAXD INXD Next: INXHL DER INZ LOOP HLT ‘Save partial sum of the readings fe carry, do not increment (B) TAde | to previous carry count ‘Go to next data location Next count $Go back to got next reading, SGet the final sum Display low-order byte of the sum iGet the carry count Display carry count SGet number for positive readings Display number for positive reading {Set pointer to data storage location {Set pointer to data location {Set counter t0 count cight bytes [Get the byte Set flag ifD7 = 1 lump to increment data pointer Place DO in CY position Slump to increment data pointer Restore original byte {Save the byte at storage location Next storage location Next data location Next count Hurap back to get next byte Answer: The following memory loestions should have the data bytes as shown, 2060 = 5248 2061 ~ 78H 2062 = 62H Section 7.5: 4 Wiig ze MVI AFH 7F ORA AF Ceraan | 7F cy “oe 36 4s. 48 AS Zcy xt 20708 MVI M64 MVIASFH 8F cMPM —-8F 0 0 0 00, 00, 7, 87, 00, 00 100 (64H) < BYTE <- 200 (C8H) 20, 64, 8F IEPORTI <32 (20K), CY fiag is set or if PORT! ~> 160 (AOHD, Minus flag is set. START: LXE, 20501 ‘Set index vo point to data Mv1 C, oor {Clear register C to save sum MOV B.C iClear (B) to eave carry, MOV D.C {Set register D to compare bytes NXTBYT: MOV AM $Get asta cur D sChesk whether this the last byte JZ. DSPLAY AE "Yes", go 10 display section ‘ADD Cc [Add provious eum, INC SAVE {Af there is no carry, 20 to save the sum INRB [Update cary resister SAVE: MOVCA ‘Save sum INK "Point to next reading JMPNXTRYT ‘Go back to get nent reading DSPLAY: MOV A, C Our PORT! Display low-order byte of the sum MOV A,B :Copy the carry count to accumulator OUT PORT2 sDisplay high-order byte of aura HLT START: LXIH, 2050 sSct index to point w data location MVTD, 40% Byte to be found in data string MVIC; ost [Setup counter NXTBYT: MOVA.M Ger data byte cmp D {ls the byte ~ 4087 JZ DSPLAY ; _ifyes, go to display its location IH {Point to mext data byte DCR ENext count SNZNXTBYT ——_ Jump t get noxt byte 7 49, 50, st DSPLAY: START: 2NXTBYT: NEXT: START: START: Loop: MVIA, FFE OUT PORTH ELT MOV AH our PORT: MOV AL Our PORT2 BLT LX1H, 20508 MvIC, os MVIB, oon MOV A.M cur 5 INC NEXT MOVE, A. INXHT DER JNZ NXTBYT MOV A,B our PoRTL HLT LXIH, 205041 MVIC, ostt MVIB, oo# MOV A.M cup & JC_NEXT MoV B.A, INXEL DCR JNZNXIBYT MOV A.B our dari LX1 #205081 Cal D 20508 MVE B10 MOV AM CPI 60, JC REJECT cer 101 INC REJECT The byte 40H is not im the set sLoad high-order memory address Display memory page number Load low-order memory address Display memory low-order adress {Set index to point to data location {Set up counter ‘Clear (B) to save the highest reading $Getdata byte Is B)> (A)? $f yes, replace (B) with (A) {Save the larges number Point to next data byte INext count Hump fo get next byte ‘Load the largest byte Display the largest byte in the string sy <(A)? Af yes, replace (B) with (A) ‘Save the larger number {Point to next data byte [Next coune Hump fo get next byte $Heoad the largest byte Display the largest byte In the string :SOURCE PORTER ISAVE POINTER sBYTE COUNT. :REIECTIF < 60 SNOTE:IF SUBTRACT 100, WOULD REJECT 100 :REECT IF > 160 52, sa REJECT: START: Loop: REJECT. START: Loop REJECT: ENDS: START: Loop: STAxD Ixx D INX DEeR'B JNZ LOOP EXT #20508 LXE D203 MYT B10 Mv Co Mov AM CPI 66 Jc REJECT crr ior INC RESECT STAXD INX D INR C INX AL DCR B INz LOOP Mov Ac our PoRTL BLT xd 4.2070 xa D2090H MOV AM crt op JZ ENDS Cer sunt JC REFECT ‘CPi san INC REIECT STAXD IXx D INX IMP LOOP, HLT LXI 1.20708 LEXI D/2090H MMVI Co MOV AM :0K, SO SAVE IT SLOOP FOR NEXT ‘SOURCE POINTER (SAVE POINTER SBYTE COUNT SREIECT IF <60. SNOTE: IF SUBTRACT 100, WOULD REIECT 100 IREJECT IF = 100 10K, SO SAVE IT. :AND COUNT IT :LOOP FOR NEXT sDISPLAY COUNT sCHECK FOR END OF STRING HIF ~ODH, THEN END OF SRTING [REIECT IF < 308 INOTE: IF SUBTRACT 39H, WOULD REIECT 39H IREJECT IF > 398 !OK, SO SAVE IT sLOOP FOR NEXT :SOURCE POINTER [SAVE POINTER, REJECT: ENDS. 55, START: Loor: SKIP. ENDS cPI opt JZ ENDS cpr 308 JC REJECT cp 3A INC REJECT sTaxD INX D INR C INK Ht IMP LooP: MOV AC. OUT PORT! HUT Lxr Bpoood mvt Co MOV A.M ora A sz ENDS Cer asH INZ ING INX SMP LOOP HLT {CHECK FOR END OF STRING UF =0DE, THEN END OF SRTING JREJECT IF < 30H | NOTE: IF SUBTRACT 39H, WOULD REJECT 3911 IREIECT IF > 30 JOK, SO SAVE IT sAND COUNT IT sLO0P FOR NEXT sDISPLAY COUNT :SOURCE POINTER FOR SCANNER READINGS !COUNTER TO COUNT SETS \GET SCANNER READING ISET ZERO FLAG. HF BYTE 0, THEN END OF STRING aS IT A 19" SET SKIPuF NO, DO NoT COUNT IP ;COUNT THE SET 56, This assignment is similar to the [Mlustrative Programm 7.53 except that the order is descending ‘and the number of bytes = 10. ‘Therefore, the counter register C should be set for 9 and the insruetion JC NXTBYT ehoutd be replaced by INC NNTBYT. () 20908-20914 (©) 1)A was not initialized to 002) Missing INX Hin loop, ‘Section 2.6: 57. @ 236 58 seri @ Em sET2 (@ DCR B hould be DCR C and add the instruction MOV A.B Just before (STA. 2070H) storing the answer 59. SETI sET2 () o16FEr (a) 039CH, (@) Change INZ 2008H to TNZ 200781 (@) ADC M should be ADD M CHAPTERS 1168 usec 234.67 mSec 468 584575 mSee Count 2FFH = 116 + 2X16» 15X16 + 15X26 =4803, "The delay in the loop: = Testates X Clock Period X Count 64X (33X10) X 4863 ‘The sbove esiculations are based on the assumption that the IMP insiniction takes 10 ‘Tostaes in the Ine: eration, and the inital instraction LXI B is not part ofthe delay loop. TO account for the 7 T-siates in the last iteration, the delay of 0.99 misro-see (x10 X 3-99 310) should be subwacted ‘wom the above delay. 234.1313 msec @4 (©) infinite ©) infinite or ust once ifthe flag is set initially () infinite @) snanite (@) 1 1.405 mSee {ethe system frequency is 3.072 MHz, the clock period will be 325 ns, This will reduce the delay to 325 5. COUNT = oEH 11 BC=34965,, Insignificant difference when the delay is caleulated with INZ ~7 ‘T-states in the last iteration. 12. 12799 GIFFED Note: In the following assignments, the delay calculations are based on the SDK-85 system with the frequency of 2.072 Mil (T= 225.5 ns). Mnemonics (Comments Testates 13, START: MVIB, oH sInitiaize counter DSPLAY: OUT PORTI BDisplsy count 10 LXID, COUNT Load delay count 10 Loop: pexp 6 MOV A,E 4 ORAD Set Z flag if (D) & () -0 4 JNZ LOOP “FZ = 1, repeat the loop 107 INRB sNext count 4 MOV A,B 4 cpr count= 2181? 3 INZDSPLAY “If net, go w display count 107 IMP START Reset counter, start again Calculations for 100 me delay: Delay outside the loop: 14688 ne ‘Delay within the loop: T= 2a T-otates x 325.5 ne x COUNT ‘Total Delay T = To+T 100 me 14648 ne + (26 x 325.5 n8 x COUNT) 100x 10- 14648 x 10 count =~ =12,798 7812 x10 31FEH START: DSPLY1 Loops Loop. DsPLY2, Loops Loops: MVIB, 00H OUT PORTI MVIC. COUNT: LXID,COUNT2 DexD MOV AE ORAB INZ LOOP? DcRC INZLOOP1 INRE. MOV A, B cProar INZDSPLY1 DERB our Port: MVIC, CouNTI LXTD, COUNT: DEXD MOV A, E. ORAD INZLOOPS bere INZ.LOOP3 MOV A,B ORAA INZ DSPLY2 IMP START stare Up-Counter :COUNTI = 10 ICOUNT? should provide 100 me delay Check whether 9 i displayed :COUNT: = 10 :COUNT? should provide 100 me delay Set Z flag it (a) = 0 For delay calculations, see Assignment #7. START: ROTATE, Loop: LoOP2: MVID, oor Mov A.D CMa, MOV D,A ANT 8081 ourProrr: MVIE, COUNT! [EXIB, COUNT? DCXB MOV A.C ORAB INZLO0P2 DCRE INZ LooPL IMP ROTATE sLosd bit patter ‘Tstaies sComplement bit pattern 4 4 ‘Mask D6-Do 7 10 to é 4 107 16, 7, ‘To design S-second delay using the loop within the loop technique, itis assusned that che LOOP? will provide 100'ms delay, and it will be repeated 50 times by using the COUNT! = 22H in the outer loop, LOOP! Delay: = 247 x (225.5ms) x50 =039me Delay Outside the loop: = 39T x (325.5 ns) = 0.0127 ms ‘Total Delay ~ LOOP! ~ LOOP2 x 50 + Outside Delay 5 6.39 ms~ (24 x 325.5.ne x COUNT2) 50 +0128 ms COUNT2 ~ 12799,78 ‘The COUNT2 can be calculated by ignoring all the delays except in the LOOP? as follows: se 00P2 x 50 = (24 325.5 ne x COUNT2) x 50 COUNT2 = 12800 “The difference between the two calculations is 0.22; it is insignificant. START: MVID, 008 Load bit pattem: ROTATE: MOV A.D 4 MA {Complement bit pattem 4 MOV D.A 4 ANIOIH :Mask D7-D1 7 Our port: 10 MVIB, COUNT 7 Loop: DCRB 4 INZ LOOP, 107 IMP ROTATE, 10 ‘otal Delay T =To+T 200 5 =46 x 325.5 ne + 14 x 325.5 nex COUNT COUNT -42.5 = 42 TURNON: MVIA, O11 Bit pater to tum on DO 7 OUT PORTI JOn-period begins 10 18 MYTB, COUNTI :Count for 200 s pulse 7 LOOP: DCRR 4 INZLOOP1 107 MVIA.00H Bit pater to tam off DO 7 OUT PORT! “Oftperiod begins to MYIB, COUNT? ;Count for 400s delay 7 Loor2; DCRR 4 JNZ LOOP? lor IMP TURNON 10 On-poriod Delay: T -To+T 200 = (24 Tx 325.5 ms) + (1b Tx 525.5 ns x COUNTI) 200-781) x19 count:

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