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Kashyap Rahul Anil Kumar RESUME IITJ 12-07-2016
Kashyap Rahul Anil Kumar RESUME IITJ 12-07-2016
74 / A, Dhanpaleshwar Society,
Near Vinzol Railway Colony,
S. L. M Road, Vatva, Ahmedabad-382445
Contact: +91 9429322575
Email: kashyap.rahul260@gmail.com
PROFESSIONAL EXPERIENCE
Organization : INDIAN INSTITUTE OF TECHNOLOGY, JODHPUR
Designation : LAB ENGINEER
Profile : Research
Experience : 01 Months
PROFILE
Accented with the latest trends and techniques of the field; Pursued M.E in VLSI and Embedded
System Design from Gujarat Technological University, Ahmedabad, Gujarat and CDAC,Pune
Pursued B.Tech in Electronics and Communication Engineering from Rajasthan Technical University
KOTA, Rajasthan.
Certified Automation Engineer : Skills include PLC (AB, Siemens, Mitsubishi and GE Fanuc), SCADA
Systems, HMI and DCS Systems (ABB).
Areas of Interest
VLSI Design, Digital Electronics, Control Systems, Basic Electronics and Embedded System Design.
EDUCATIONAL CREDENTIALS
Projects Undertaken
1. M.E. Dissertation
Title: Implementation of Ternary Sequential Elements using CNTFET.
Platform: VLSI with Analog and Mixed Signal Design
Organization: CDAC, PUNE
Duration: 10-12 Months
Abstract: The Aim of this work is to present the Advantages of Ternary Logic over Binary Logic in
terms of Computations and Circuit Designs based on CNTFET, replacing MOSFET reduces the total
power consumption and occupies less area on VLSI Chips.
Papers Published
(1) Rahul Kashyap, Implementation of Ternary Logic Gates using CNTFET in International Journal
for Scientific Research and Development (IJSRD), Vol. 2 Issue 3, 2014, ISSN: 2321-0613, Page 352-
355.
(2) Rahul Kashyap, Radha Tapiawala, Design of Universal Logic Gates based on CNTFET for Binary
and Ternary Logic in IJERT, Vol. 3 Issue 6, June 2014, ISSN: 2278-0181, Page604-609.
Seminars Guided
Sensor based Automation of Greenhouse
Android: Architecture and Development
PAN Sharpening Techniques in Image Processing
Technical Skills
Qualified GATE-2016 Examination recently with Electronics and Communication Engineering.
Qualified GATE-2012, 2013 and 2014 Examination with ECE.
VERILOG, HSPICE, Embedded C, Embedded Linux, C, C++, HTML, JAVA, Perl, Web Designing and
Internet Applications.
Achievement
Credential of being awarded for securing 100% in Mathematics in XII Examination, I.S.C.E Board.
Seminars Delivered
Delivered a Seminar on Surface Computing Technology.
Microsoft Surface Overview with In-Depth Analysis of its working and Components.
MRAM Technology.
Hobbies
PC Games, Reading, Photography, Computer Learning, Riding Bikes, Outing.
Personal Details
Date of Birth : 18th October, 1989
Gender : Male
Nationality : Indian
Marital Status : Unmarried
Languages Known : English, Hindi, and Gujarati.
Declaration:
I hereby declare that the above mentioned Information is Correct and I Bear the Responsibility for the
Correctness of the above mentioned Particulars.