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1:4 Demultiplexer Verilog Code

This document describes a 1:4 demultiplexer circuit. It takes in a single input signal i and two select signals s1 and s2. Based on the values of s1 and s2, the input i is routed to one of the four output signals a, b, c, or d. The module uses assign statements to define the logic that determines which output receives the input signal i based on the states of the two select signals.

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yogi
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32 views1 page

1:4 Demultiplexer Verilog Code

This document describes a 1:4 demultiplexer circuit. It takes in a single input signal i and two select signals s1 and s2. Based on the values of s1 and s2, the input i is routed to one of the four output signals a, b, c, or d. The module uses assign statements to define the logic that determines which output receives the input signal i based on the states of the two select signals.

Uploaded by

yogi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd

1:4 demultiplexer

module demux(

input i,

input s1,

input s2,

output a,

output b,

output c,

output d

);

assign a = s1 ? 0 :(s2 ?
0 : i);

assign b = s1 ? 0 : (s2 ? i :
0);

assign c = s1 ? (s2 ? 0 :
i) : 0;

assign d = s1 ? (s2 ? i :0) : 0 ;

endmodule

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