Low Power Finite State Machines

K N Indraja Ramiz Mahaboob Shruti Narake

Dept. of ECE, MIT Dept. of ECE, MIT Dept. of ECE, MIT
 Abstract Finite State Machines (FSM) are the high-Vth cells that uses fewer cells overall. It is for this
compact way to represent a set of complex rules and reason that these trade-offs should be considered early in
conditions, and to process various inputs. These are the synthesis process. A better approach for synthesis using
used in every digital logic nowadays for efficient logic multi Vth cells is to create a post-logic-synthesis routine
design. But the higher power consumption of latest that replaces low-Vth cells with high-Vth cells as long as
technology nodes has to be rectified by a different the timing constraints and other design rules and
design technique of FSM. In this paper, our focus is on constraints are not violated. A more sophisticated approach
reduction of power consumption by partitioning the used during synthesis incorporates the leakage power as a
FSM and make it into a different instance so that component of the optimizations objective function. Here,
Multiple Threshold Voltage and Multiple Supply it is important to have libraries that have been properly
Voltage for different instances can be easily characterized to perform this type of optimization.
implemented in the synthesis and physical design
stage. II. METHODOLOGY
Index Terms FSM, Multiple Threshold Voltage,
Multiple Supply Voltage, CPF
A. FSM Partitioning
I. INTRODUCTION
FSM can be partitioned into smaller pieces. The idea
The shift in the use of chips to consumer applications and here is to decompose a large FSM into several simpler
the change in the latest process technologies have made FSMs with smaller state registers and combinatorial logic
power one of the primary design criteria for a majority of blocks. Only the active FSM receives clock and switching
the chips worldwide. However, the industrys design inputs. The others are static and do not consume any
infrastructure has not evolved at the same pace. Now the dynamic power. We consider a large FSM that includes a
focus is to reduce both the dynamic and leakage power of small subroutine, which is used very often in a real
the end product. For the commercial success of the device, application scenario. We can easily partition the big FSM
low power design methodologies are very much needed. into two parts and isolate the subroutine loop. Figure 1
Since many of these applications are control-dominated, shows an FSM decomposed into two simpler FSMs. The
efficient low power realization of a controller as an FSM new FSMs are mutually exclusive; when one is operating,
has emerged as a challenging task. the other one remains off. In such a state, clock and inputs
A lot of work has been done in finite state machine can be gated to prevent any dynamic power (power supply
synthesis and state encoding targeting low power in [1,2, 3, could even be switched off to save leakage). The power
4, 5, 6]. Partitioning has been shown to be a very effective savings is even higher if we can isolate very small subsets
technique for reducing power in FSMs. Low power FSM of states where the initial FSM remains most of the time.
partition techniques have been addressed in a number of
references. The principle behind the partition technique is
that a main FSM is partitioned into a number of sub-FSMs
but only one machine is activated while others are disabled,
which could lead to power savings. The Active Sub-FSM
(ASFSM) is in control. When the next input signal comes,
the ASFSM either remains active or it is turned off while
the other one is turned on and set to a correct state.
Silicon foundries have started to offer multiple threshold
devices at the same process node to address the need to
control leakage current and enabling designers to trade off
leakage and performance. From the standard Vth, a low-
and high-Vth transistor may be offered. It is not uncommon
Figure 1: FSM Decomposition
for the low-Vth device to have an order of magnitude
higher leakage than the standard Vth device and the high-
Vth device to have leakage characteristics an order of B. Multiple Threshold voltage
magnitude below the standard. For special applications, a
special low-leakage device may exist that will reduce the
Leakage power is the power dissipated by current
leakage further by another order of magnitude. This
leaks in the transistors. The leakage power is usually
reduction in leakage comes at the expense of the speed of
modelled in the library as a constant. The availability of
the device. A design with a higher percentage of high-Vth
two or more threshold voltages on the same chip (multiple-
cells may appear to be better at first glance, but it could
Vth process) provides the opportunity to make trade-offs
also be inferior to a design with a lower percentage of
between power and performance. If you load multiple
libraries containing cells with different threshold voltages,
the RC-LP engine can make tradeoffs between timing and
leakage power during synthesis.
When multiple threshold voltage (Vth) libraries are
provided, the synthesis tool can further optimize leakage
power by utilizing high Vth cells (low leakage power, slow
timing performance) along the non-critical timing paths,
and low Vth cells (higher leakage power, faster timing
performance) on timing-critical paths. Depending on the
design requirements, you can choose different optimization
effort levels for leakage power optimization with multiple
Vth libraries.
If you set power constraints, Cadence Encounter RTL
Compiler performs timing, area, and power optimization
simultaneously. The tool tries to meet timing constraints,
while balancing area and power. By allowing the area to
increase, you can get better power results. To control the
tradeoff between area and power, the power optimization
effort root attribute can be set.
C. Multiple supply voltage design
One of the techniques to reduce dynamic power
consumption in system on chip is to reduce supply voltage.
Multiple Supply Voltage (MSV) design is one such
technique provided by low power engine in Cadence
Encounter RTL compiler to reduce the power supply. A
Multiple Supply Voltage (MSV) design uses multiple
supply voltages for the core logic and for the different
instances in the design. A portion of the design that
operates at the same operating voltage (that is, uses the
same main power supply) belongs to the power domain
that corresponds to that operating voltage. Standard cell
libraries are characterized based on operating conditions.
The blocks operating on a particular voltage need to use the
libraries characterized for that particular voltage. The
libraries which are operating at the same nominal operating
conditions are grouped under a library set. Figure 2 shows
FSM top module and partitioned instance with respective
power domains.
Figure 2: FSM top module and partitioned instance with
respective power domains
When signals pass between portions of the design that are
operating at different voltages, level shifters are needed.
Level shifter are the interface circuit used when VDD low
cells drive VDD high cells in order to avoid leakage.
The Common Power Format (CPF) file captures the
information described above in a text file. The CPF file is a
power specification file. This implies that the functionality
of the design does not change when sourcing a CPF file.
The CPF file complements the HDL description of the
design and can be used throughout the design creation,
design implementation, and design verification flow.
This design includes partitioned FSM with a top module
and an instance operating in two power domains: PD1
operating at 1.4V & PD2 operating at 1.62V. PD1 includes
the top module and PD2 includes the instance. A suitable
level shifter is placed between these two domains. This
design has 2 input pins clock and reset thus level shifters
are placed in clock and reset pins belonging to different
power domains. A CPF file is written to capture this
information.
III. EXPERIMENTAL RESULTS
A FSM Partitioning
The FSM design was partitioned into top module
and an instance and clock gated accordingly. The synthesis
was carried out using Cadence Encounter RTL Compiler.
The partitioned design achieved 24% power saving without
affecting the design timing constraints in 45nm technology.
Table 1 shows the power report comparison for different
technologies.
Table 1: Power report comparison of Non-partitioned and
Partitioned Design for different technology nodes.
B Multiple Threshold voltage
The partitioned FSM was constrained at 400MHz
(2.5ns time period). Using Cadence Encounter RTL
Compiler, the leakage power was reduced using multiple
threshold voltage cells available in the library at 45nm
technology. The method achieved 50% total power saving
and 77% leakage power saving. Table 2 shows Power
 report comparison with and without Multiple Threshold
Voltage.
Table 2: Power report comparison with and without
Multiple Threshold Voltage
The critical path was analyzed before and after the
method was incorporated. As the slack was positive in the
critical path, the leakage power in the critical path was
reduced by using high Vth cells from library with an
increase in the delay. Table 3 shows the critical path delay
and leakage power comparison.
Table 3: Critical path delay and leakage power
comparison
C Multiple supply voltage design
The proposed method was implemented using
Cadence Encounter RTL Compiler low power engine. The
partitioned design achieved 19% power saving without
affecting the design timing constraints in 180nm
technology. Table 4 shows the power reports. Level shifter
standard cell LVLHLX8 was inserted between clock and
reset pins of the two power domains. Figure 3 shows the
synthesized design after insertion of level shifter cell.
Table 4: Power report comparison with and without
Multiple Supply Voltage
Figure 3: Synthesized design after insertion of level shifter
cell
IV. CONCLUSION
In this work, an effective technique of Multiple supply
voltage considering the problem of partitioning of FSM for
low power has been explored. Significant amount of power
saving has been achieved using this technique. During the
execution of our method, power is being estimated using
Cadence Encounter RTL Compiler which gives leakage
power after the use of Multiple threshold voltage. The
partitioned FSM with separate power domains are
synthesized using Cadence synthesis tool at 45nm
technology and leakage power as well as switching power
for the sequential circuit has been reported. Our method
achieved good leakage power saving also. In this work, the
area overhead is not considered. Our future work will focus
on these aspects with power gating.
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