Programmable Logic Devices

(PLD)
Prepared by:

Amit Joshi

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 Outline

Introduction to PLD

Why CPLD?

Why FPGA?

Comparison of CPLD & FPGA

Gate array Design

Getting started with ISE 7.1i

Different ways of simulation

Flow of Implementation

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 Introduction to PLD
ASIC (Application Specific Integration Circuit)
Circuit)::
- Fixed functionality
- Digital IC 74
74xx
xx series

Concept of PLD (Programmable Logic Device)

Device)::
It is possible to manufacture chips that contain relatively large amounts of
logic circuitry with a structure that is not fixed means we can modify (to
some extent) according to our requirement
requirement..
Such chips are introduced in 1970 and are called PROGRAMMABLE LOGIC
DEVICES..
DEVICES

Evolution of PLD
- PROM ,PLA ,PAL, CPLD, FPGA
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 Advantages of PLD

Advantage of PLD

Ease of design changes

Flexibility
No ASIC re re--spin risk
Easy & faster design Implementation
Shorter time to market

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 Programmable Logic Devices

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 Programmable Array Logic

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 Programmable Array Logic
w= ABC + ABCD
X= A + BCD
Y=AB + CD + BD
Z= ABC + ABCD + ACD + ABCD
= W + ACD + ABCD

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 Programmable Logic Array
F1= AB + AC +ABC
F2= ( AC + BC )

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 Outline
Introduction to PLD

Why CPLD?

Why FPGA?

Comparison of CPLD & FPGA

Gate array Design

Getting started with ISE 7.1i

Different ways of simulation

Flow of Implementation

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 Why CPLD?
CPLD (Complex Programmable Logic Devices)
Features:

Low development cost

Faster time to market
Reduced PCB area
Ease & Simple way to implement a design

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 Structure of CPLD

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 CPLD (Complex Programmable Logic Devices)
Advantages :

- Simplified design process.

- Mostly standard architecture and easy to use.
- Low cost design and development tool
- Deterministic, uniform delays and predictable timing.

Disadvantages :

- Low to moderate density

- Low utilization of internal resources
- Inflexible architecture.

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 Outline
Introduction to PLD

Why CPLD?

Why FPGA?

Comparison of FPGA & CPLD

Gate array Design

Getting started with ISE 7.1i

Different ways of simulation

Flow of Implementation

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 Why FPGA?
FPGA stands for Field Programmable Gate Array
More Gate count to support complex logic CKT
It does not contain AND and OR planes.
They have
- Logic blocks arranged in 2-
2-D.
- Routing channels, programmable switches.
Mostly LUT are there to implement logic.
LUTs of various sizes can be created, they are
limited by number of inputs.

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 Structure of FPGA

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 FPGA
Advantage:----
Advantage: ----
- Ideal for customized design
- High complexity , density and reliability
- Low cost, power consumption, small physical size
- Fast time to market

Disadvantage:----
Disadvantage:----
- High NRE cost, long delay in design and testing

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 FPGA (Field Programmable Gate Array)

What are the limitations of FPGA?

Existence of programmable switches.
Of course they provide programmable feature to
user but, they consume lot of real estate on the chip.
They make reduce the speed of operation.

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 FPGA Generic Flow
Design Entry:
Create your design files using:
schematic editor or
hardware description language (Verilog,
VHDL)

Design implementation on FPGA:

Partition, place, and route to create bit-
bit-
stream file

Design verification:
Use Simulator to check function,
other software determines max clock
frequency.
Load onto FPGA device (cable connects PC
to development board)
check operation at full speed in real
environment.

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 Outline
Introduction to PLD

Why CPLD?

Why FPGA?

Comparison of FPGA & CPLD

Gate array Design

Getting started with ISE 7.1i

Different ways of simulation

Flow of Implementation

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 Comparison Of CPLD & FPGA
CPLD FPGA
Logic gates are less in number Several millions of gates

Number of i/o pins are Number of i/o pins are less

significantly higher
CPLD does not require any
external memory store
program
CPLD consume more power
than FPGA
CPLD are smaller than FPGA
than CPLD
It requires one or more PROM
depend on the size
FPGA consumes less power
than CPLD
FPGA are larger than CPLD

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 Outline

Introduction of PLD

Why CPLD?

Why FPGA?

Comparison FPGA & CPLD

Gate array Design

Getting started with ISE 7.1i

Different ways of simulation

Flow of Implementation

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 Introduction to Gate Array
Gate array is a prefabricated silicon chip circuit.
circuit.

Gate array is an IC chip on which gates are placed in

a matrix form

Gate array contains basic cell as most important

element.. It contains (either CMOS,NAND,NOR or
element
any other active device).
device).

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 Gate Array

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 Gate Array Design
Gate array implementation requires a two step manufacturing
process::
process
- The first phase, which is based on generic (standard) masks,
results in an array of uncommitted transistors on each GA
chip..
chip
- These uncommitted chips can be stored for later
customization, which is completed by defining the metal
interconnects between transistors of arrays
arrays..

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 Switching matrix

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 Configurable Logic Block (CLB)
Consist of look up tables
CLB is able to implement logic function of up to 9 variable
We can implement large function
Increases capacity and speed

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 FPGA Application
In DSP ,software defined radio, defense system,
aerospace
Biomedical instruments, speech recognition
Computer hardware simulation
Image controller
Gate array prototyping
Basically register intensive application

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 CPLD Application
Most common use in industry
CPLDs can realize complex designs, such as
graphic controller,LAN Controller.
High speed glue logic
PAL integration
System video controller
Bus interfacing

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 CAD Technology
Essential for timely development of ICs.

Time consuming and computation intensive parts of

the design can be executed by CAD tools.

Types of CAD tools:

1. High level synthesis
2. Logic synthesis
3. Circuit optimization
4. Layout
5. Simulation
6. Design rules Checking
7. Formal verification
Synthesis tools:
Address the automation of design phase in
the top level of design hierarchy. Ex: HDLs
Logic synthesis and optimization tools are
developed and customized for a particular
design requirement.

Layout tools:
The layout CAD tools include floorplanning,
place and route and module generation.

DRC checking CAD:

This category includes tools for layout rules
checking, electrical rules checking and
reliability rules checking.
Simulation and Verification tools:

Include circuit level, timing level, logic level,

behavioral level, device level and process level
simulation tools.
Aim to determine if the designed circuit meets
required specifications at all stages of the design
process.
Logic simulation is performed to verify functionality
of the circuit. (at gate level of abstraction)
Circuit level or electrical simulation tools determine
the nominal and worst case delays, critical delay
paths, and to predict the influence of parasitic
effects on the circuit behavior.
 VLSI design

Full custom (geometry &

Semi custom
placement of every transistor (such as std cell
design or FPGA)
can be optimized individually)

For economic success of any competitive commercial

product, majority of the design cycle time is
devoted to achieve a certain desired performance
of the chip at an acceptable cost.
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Full custom design:
Requires longer time till design maturity
Adjustment flexibility of almost every aspect improves
the circuit performance
High performance but large cost in terms of design cycle
time.
Semi custom design:
Requires less time till design maturity
In early stage, performance is better to full custom
design because, some components are optimized. But, less
opportunity for improvement in the circuit performance.
Lesser performance but shorter design cycle time.

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 Outline
Introduction to PLD.

Why CPLD?

Why FPGA?

Comparison FPGA & CPLD

Gate array Design

Getting started with ISE 7.1i

Different ways of simulation

Flow of Implementation

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 Design Specification

Design Entry

Schematic HDL VHDL Finite State Machine

Verilog

Verification

Gate Net list

Creation / Synthesis

Functional Verification

Xilinx Device
Implementation

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