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REFERENCES
A REQUEST_
REPLY
C
Fig. 4. Synchronizing voter. DATA
REPLY
would be signaling that the data were valid after such was no longer
the case. The resulting voters for synchronization and data signals
are shown in Figs. 8 and 9. The one-shot and D flip-flop serve for the
synchronizing delay. The rising edge of the signal coming from the
majority voter triggers a low-going pulse on the one-shot. When that
Fig. 6. Synchronizing voter for transition signaling convention with pulse terminates, the D flip-flop triggers, clocking in the value of the
relaxed constraints. voted signal. As the voted signal is attached to the "reset" line of the
flip-flop when a majority of the voter input signals go low, so does the
signal on each cycle. If one of the modules operates so slowly that it output of the circuit. Once again, a simple majority voter suffices for
exceeds the a priori time limit imposed by the synchronizing voter, the data.
it is considered to have failed. The synchronizing delay should be
considerably shorter than the total time required for a single "re PULSE SIGNALING CONVENTION
quest-reply" cycle.
The pulse convention, illustrated in Fig. 10, provides only a mo
mentary signal for "request" and "reply." An alternative design to
TRANSITION SIGNALING CONVENTION
that presented in Davies and Wakerly for the synchronizing voter is
Each signaling convention requires a different voter circuit. The shown in Fig. 11. The special problem posed by the pulse convention
transition convention, illustrated in Fig. 3, signals "requests" and is highlighted by the complexity of the data voter, shown in Fig. 12.
"replies" on all transitions, either from low to high or from high to As the data is valid on each bus for only a short time and the three
low. Assuming the associated data is kept valid from the time of a independent "replies" may not be valid simultaneously, giving valid
"reply" until the next "request," the circuits shown in Figs. 4 and 5 voted data, care must be taken to properly latch the data to ensure
will correctly handle synchronization of control and data signals. As valid setup and hold times for the voted "reply." This is done by
either transition requires synchronization, a simple delay is needed latching the data on each bus when their own "reply" is received and
in the voters for the control signals. (Note that this is the only con holding the data until the specified time after the voted "reply" is
vention for which the simple model of a synchronizer will work released.
properly.) Assuming that the voted data will be valid at least as soon
as two of the "replies" are returned and will stay valid until the next MINIMIZING DELAYS IN T H E SYNCHRONIZING VOTERS
voted "request," only a simple majority voter is required for the
As alluded to in Davies and Wakerly and earlier in Siewiorek et
data.
al. [2], a bypass of the delay in a synchronizing voter can be desirable
The voter shown in Fig. 4 requires that all three systems be ini
when all three signals have arrived. The circuits of Figs. 13-16 show
tialized to the same state, such that each system's control signal such an addition for each of the three signal conventions. In each case
undergoes the same transition (low-to-high or high-to-low) on each the voters for data signals given in the previous examples are still valid.
transaction. If this restriction is lifted, a much more complicated For this new scheme to function properly, additional restrictions may
circuit such as the one shown in Fig. 6 is needed. The latter circuit have to be placed on the specified operation of the system, depending
works by internally changing each transition to a "level" signal for on the particular signaling convention used. Using the level signaling
voting upon. convention as an example, it is necessary that a slow slave be able to
remove its "reply" signal in response to the removal of the voted
LEVEL SIGNALING CONVENTION
"request" signal before the next voted "request" appears. Otherwise,
The level convention (commonly found in computers such as the its lagging "reply" may be misinterpreted.
LSI-11) signals "requests" and "replies" by a transition from low to The circuit shown in Fig. 13 for transition-based signals produces
high, with the request (or reply) being maintained until the level falls LOW (and HI) output whenever all three inputs are LOW (or HI).
low again. This convention is illustrated in Fig. 7. As the data are Thus, when all three input signals have arrived, the voted result is send
specified to be valid until after the "reply" is removed, the voted immediately. The delay occurs only when one of the three inputs lags
control signal cannot be maintained at the high level after the data behind the other two, allowing it to catch up. Fig. 14 shows a modified
have been removed. Thus, the delay following the voter for synchro voter for transition signaling convention systems which do not require
nization purposes must occur only on the rising edge (low-to-high) global initialization. Its operation is closely related to that of the
of the signals. If the falling edge were delayed, the voted "reply" following circuits in Figs. 15 and 16.
IEEE T R A N S A C T I O N S O N C O M P U T E R S , V O L . C-30, N O . 2, F E B R U A R Y 1981 163
D Q
7474CLR
T
ONE y ONE
D Q S H O T l ISHOTI
7474CLR
Q
7474
Fig. 11. Synchronizing voter for pulse signaling convention.
DATA A
D Qh
REPLY A
7475
Fig. 14. Modified synchronizing voter for transition signaling convention
with relaxed constraints. .
DATA V O T E D
D Q D A T A
REPLY
7475
A-
DQ
DATA C B-
ONE
7474
CLR
ISHOTl
D Q c-
R E P L Y C
7475 Fig. 15. Modified synchronizing voter for level signaling convention.
V O T E D ONE TJ" I ONE THESE LATCHES PASS D TO
D Q
Fig. 12. Data voter for pulse signaling convention.
7474
D Q
-A 744
/
D Q ONE b- >CLR
ISHOTI
7474
t><*R
Q
Fig. 13. Modified synchronizing voter for transition signaling
7474 SHOT|
convention. X
Fig. 16. Modified synchronizing voter for pulse signaling convention.
The circuit shown in Fig. 15 is in actual use in C.vmp [3]. The
change made to the circuit of Fig. 8 is "presetting" the D flip-flop and the delay is cut short using the "clear" input of the one-shot. Thus,
"clearing" the one-shot (e.g., type 74221 [4]) whenever all three voter the full delay is used only when necessary: a lagging signal is given
input signals have arrived. This bypasses the delay when it is unnec every chance to catch up with the other two. Note that this technique
essary, while still utilizing it when one of three inputs is slow or has of "clearing" the delay of the one-shot is very similar to that used in
failed. This circuit is used in C.vmp for the set of basic handshaking the previous circuit for level-based signals.
bus synchronization signals. It has proven capable of providing ade
quate synchronization of a three processor system. A similar circuit 1
has been implemented in a custom LSI voter chip designed to allow REMAINING PROBLEMS
easy implementation of triplicated microcomputer systems [5].
The circuit in Fig. 16 for pulse-based signals is based on the same One problem of the last set of voters is that a failure in one of the
reasoning as the earlier ones: when all three input signals have arrived, inputs can cause degradation of performance back to that of the
previous designs. This delay in the presence of an input fault is un
1
C.vmp uses a common clock to synchronize the three processors at the mi avoidable, as full allowance must be made for the variance in timing
crocode level in order to reduce bus disagreements as much as possible. This between the two surviving modules.
is important in light of the goal of measuring transient errors. Normally, the A more serious problem is that posed by runt pulses or critical races
"bus reply" signal is latched by the voter one clock phase-100 ns-prior to its in inputs to bistable circuits [6], [7]. Fig. 17 shows a possible syn
sampling by the processors. This ensures totally synchronous reception of the
chronizer to reduce this problem, based on a proposed circuit in [7].
signal, minimizing the bus disagreements during normal operation. To test
the robustness of the synchronization provided by the special synchronizing Whenever the D flip-flops are in the meta-stable state, the Q and Q
voter circuits used for the basic bus control lines, the system was rewired to outputs are equal, which is detected by the comparators, causing the
pass the voted "bus reply" directly to the processors without latching. During sampling clock to stop until a stable state is entered and the outputs
this test it was observed that the three processors very frequently fell out of are again complementary. The signals A', B\ and C can be used as
step with each other at the microcode level, but were kept synchronized at the the inputs to the circuits given previously, with greater assurance of
bus transaction level, maintaining proper execution of programs. reliable synchronization.
164 IEEE T R A N S A C T I O N S ON C O M P U T E R S , V O L . C-30, N O . 2, FEBRUARY 1981