Chapter 9

Bit Serial Arithmetic

Winter 2006 ECEn 621 Computer Arithmetic

Slide #1 Dr. Doran Wilde

Digit Serial Arithmetic

Consumes one digit of each operand per cycle
Produces one digit of the result each cycle

... , x3, x2, x1

... , z3, z2, z1
... , y3, y2, y1

clk

Two Modes of Operation

LSD-First (Least Significant Digit First)
MSD-First (Most Significant Digit First)
Also called Online Arithmetic

Winter 2006 ECEn 621 Computer Arithmetic

Slide #2 Dr. Doran Wilde

1
 Timing Parameters
r, the radix
n, the number of digits input/output
, the initial delay (online delay)
number of addition cycles before first digit is produced
T, total execution time
time from first input digit to last result digit
T=+n+1

Winter 2006 ECEn 621 Computer Arithmetic

Slide #3 Dr. Doran Wilde

Serial Addition/Subtraction

Radix 2
LSD-First

Radix 16
LSD-First

Winter 2006 ECEn 621 Computer Arithmetic

Slide #4 Dr. Doran Wilde

2
 Bit-Serial Multipliers

Winter 2006 ECEn 621 Computer Arithmetic

Slide #5 Dr. Doran Wilde

Dependence Graphs and Regular Array Design

Show all operations and use arrows to show flow of data
between operations.
Shows dependences between operations.
Determine a schedule.
What operations can happen at the same time.
Determine an allocation.
What operations can happen in the same place
(meaning the same processor).
Determine communication between processors.
Interpret data flow on dependence graph as
communication between processors.

Winter 2006 ECEn 621 Computer Arithmetic

Slide #6 Dr. Doran Wilde

3
 Semi-Systolic #1:
A parallel, X serial (LSB first)
a3 a2 a1 a0
Dependence x0
Isotemporal line.
Connects operations Graph
performed at the same time. x1

x2

x3
Allocation box.
Encloses operations 0 AND, full add,
performed on the same latch operation
processor.
0 Same operation,
(4 processors) these nodes are
used to propagate
0 carries and shift out
results.
0

Winter 2006 ECEn 621 Computer Arithmetic

Slide #7 Dr. Doran Wilde

Semi-systolic Design #1

Requires 4 zeros to be shifted in after the xs

Winter 2006 ECEn 621 Computer Arithmetic

Slide #8 Dr. Doran Wilde

4
 Modified Design #1
Allows a new problem to be started 4 cycles earlier.

a3 a2 a1 a0

PL
AND, Add
X

Delay Elements

PH

Serial Adder

Winter 2006 ECEn 621 Computer Arithmetic

Slide #9 Dr. Doran Wilde

Semi-Systolic #2:
A parallel, X serial (LSB first) a3 a2 a1 a0
x0
x1

x2

x3

0
Winter 2006 ECEn 621 Computer Arithmetic
Slide #10 Dr. Doran Wilde

5
 Semi-systolic Design #2

Winter 2006 ECEn 621 Computer Arithmetic

Slide #11 Dr. Doran Wilde

Systolic Design
A parallel, X serial (LSB first)
a3 a2 a1 a0
x0
x1

x2

x3

Winter 2006 ECEn 621 Computer Arithmetic

Slide #12 Dr. Doran Wilde

6
 Systolic Design

Winter 2006 ECEn 621 Computer Arithmetic

Slide #13 Dr. Doran Wilde

Systolic Design
A serial and X serial (LSB first)
a3 a2 a1 a0
x0
x1

x2

x3

Winter 2006 ECEn 621 Computer Arithmetic

Slide #14 Dr. Doran Wilde

7
Bit-Serial Multiplier
in Dot Notation

Output

(5:3] Counter
Column Reduction

Output
Winter 2006 ECEn 621 Computer Arithmetic
Slide #15 Dr. Doran Wilde

Bit-Serial Multiplier

Winter 2006 ECEn 621 Computer Arithmetic

Slide #16 Dr. Doran Wilde

8
 Both Inputs Serial, LSB First (Algebraic Derivation)
Let a ( i ) = 2i ai + a (i 1) , a ( 0) = a0
x ( i ) = 2i xi + x (i 1) , x ( 0 ) = x0
m (i ) = a (i ) x (i )
= (2i ai + a ( i 1) )(2i xi + x ( i 1) )
= 2 2i ai xi + 2i (ai x ( i 1) + xi a ( i 1) ) + a (i 1) x (i 1)
= 2 2i ai xi + 2i (ai x ( i 1) + xi a ( i 1) ) + m (i 1)
2 214
( i +1)
2m 3 = 2 ai xi + ai x
4
(i ) i ( i 1)
+ xi a (i 1) + 21i
42
( i 1)
m4 3
p(i ) p ( i 1)

2 p ( i ) = 2i ai xi + ai x (i 1) + xi a (i 1) + p (i 1)
Winter 2006 ECEn 621 Computer Arithmetic
Slide #17 Dr. Doran Wilde