School of Computer Science and Electronic Engineering

CE162 - Digital Electronic Systems

Dr. Nikolaos Thomos*

Section 3 – Higher Level Digital Logic Operations

*From original source material by Tim Dennis

1
 Data Storage: basic binary (two-state) cell

Often drawn in a symmetrical way (right), suggesting it has two internal feedback loops,
in fact there is only one:

S
X1 & Z1 =X1.Z2 =X1+ Z1.X2 & Q

X2 & Z 2 =Z1.X2 =Z1+ X2

& Q
R

X1 X2 Z1old Z1new Z2new Comment

1 0 0 0 1 1 Problem! Applying the logic equations for each of the gates, it's easy to
derive the static Truth Table for the circuit.
2 0 0 1 1 1 Problem!
3 0 1 0 1 0 Set The 'interesting' situations arise only when there are transitions
4 0 1 1 1 0 Remain Set between states (rows on the table), in particular out of states 1 and
5 1 0 0 0 1 Remain Reset 2 into states 7 or 8: in these cases it's impossible to predict the
6 1 0 1 0 1 Reset final state of the circuit.
7 1 1 0 0 1 Store
8 1 1 1 1 0 Store Transitions from anywhere else into states 1 to 6 are all well-
defined, because the output conditions are dominated by X1 and
X2: the feedback has no effect
NB: Z1old represents the state of the circuit before the
specified X1, X2 input conditions are applied. Rows 7 and 8, however, are where the feedback does matter and
the circuit can be in either of its two possible stable states,
which is how it stores information. Transitions into 7 and 8 from 3,
4, 5 and 6 are how the circuit is placed into a chosen state.

2
The root of the problem…

If you have time, try the circuit on Page 2 in MultiSim. Connect X1 and X2 together and drive them with a
1 0 1 0 ... sequence from the Word Generator.

Z2 Z1
1 1

Equivalent circuit when X1 = X2 = 1

There are two stable states which are Z2 Z1 = 01 and Z2 Z1 = 10.

If for any reason Z2 Z1 = 11, then an unstable positive feedback loop can be set up, causing
oscillation.

3
Useful application of RS flip-flop – (1) D-type Latch

S
&
D & Q

& Q
R
&
Clock

NB: RS flip-flop drawn in conventional way

It is impossible for S and R in this circuit both to be LOW at the same time,
so the instability problem cannot occur.

Work out how the circuit outputs depend on the D (data) input when the Clock input is
High or Low.

4
Useful application of RS flip-flop – (2) Switch Debounce Circuit

The problem
Mechanical switch,
1 second

+5 V

& Q

Mechanical switch,
250 microsecond & Q
0V R

'Pull-up resistor', ≈1k

+5 V

These are typicaactual waveforms that would be

seen on the S and R inputs to the flip flop.
5
Useful application (3) – Master-Slave configuration Edge-triggered J-K Flip Flop

Master Slave

Clock

• Subject to any constraints from the two overall

feedback paths, the Master's outputs will respond
directly to the J and K inputs while Clock is HIGH.
Master Master
Disabled • When the High to Low clock transition occurs, the
Clock Enabled Master's output is fixed.

• After the inverter propagation delay, the Slave

device is enabled and 'copies' the most recent
Clock output of the Master. Because the Master's state is
Slave Slave fixed, it cannot change again until the next High to
Disabled Inverter Low clock transition.
Enabled (U3A)
propagation • The overall feedback paths ensure that the Slave
delay
flip-flop changes state if both J and K are HIGH,
hence making constructive use of the 'problem'
input condition of the simple RS flip-flop.

6
JK Flip Flop terminal behaviour

Characteristic Table Excitation Table

J K Q- Q+ Qn Qn+1 J K
0 0 0 0 0 0 0 x
J Q
0 0 1 1 0 1 1 x
0 1 0 0
Clk 1 0 x 1
0 1 1 0
1 0 0 1 1 1 x 0
K Q
1 0 1 1
1 1 0 1
The way the clock input is This table shows what needs to be
drawn indicates that it is 1 1 1 0 done to J and K to get the Qn
edge triggered (>) and Qn+1 outcomes listed.
that the active edge is the Q- is the state just before the clock pulse
high to low (negative Q+ is the state just after the clock pulse
going) transition of the The presence of the 'don't care' (x)
clock. The 'toggle' (change of state) when J=K=1 conditions potentially simplifies
is probably the most useful feature of the the design equations for
device. sequential circuits based on JK
flip-flops.

7
Application of JK Flip-Flops: Asynchronous Up Counter (also known as Ripple Counter)
This exploits the 'change of state' behaviour of the JK flip flop when J=K=1. The next stage is clocked by the high to low transition from the
previous stage.

J Q1 J Q2 J Q3

Clock In Clk Clk Clk And so on...

K Q1 K Q2 K Q3

+5 V

Clock

Q1

Q2

0 1 2 3 4 5 6 7 0 1 2 3 . . .

Q3
8
In practice, with the Ripple Counter design, the waveforms will be more like this:

(see also Multisim Digital Circuits introductory document, exercise 3)

Clock

What is the likely effect in any application, and what happens for very long counters (i.e. many bits)?

9
 Synchronous 3-bit counter
This is a true 'sequential circuit', the definition of which is that its current outputs ('state') depend on the states of both its current
inputs (if any) and its previous outputs, i.e. the circuit must contain memory of some kind. The circuit uses external logic to
calculate the control inputs for each flip flop based on the current state and the input(s). These will generate the required next
state after a clock pulse.

&
+5 V

J 1 Q1 J J
2 Q2 3
Q3 Flip flops are clocked in
Clk Clk Clk parallel, so in theory all
outputs will change
state simultaneously.
K Q1 K Q2 K Q3

The design for a counter using JK flip flops is

Clock In very straightforward if we again exploit the
'change of state' property when J=K=1.

Clock Flip flop 1 always changes after each clock

pulse, so J1=K1=1.

Q1 Flip flop 2 changes state only when output

Q1 is at logic '1' before the clock pulse.
Hence J2 = K2 = Q1
Q2
Flip flop 3 changes state only when both Q1
and Q2 are at logic '1' before the clock
Q3 pulse. Hence J3 = K3 = Q1.Q2.

Repeat the process for a 'down counter', i.e.

More complex systems that include input control signals need a formal design process 7, 6, 5, 4....
that involves constructing a State Transition Diagram, State Table, State Assignment
and Boolean expressions for J and K for each flip flop. This process is covered in detail
in Year 2 modules. 10
D-type flip flop, e.g. TTL 74LS74
Positive edge-triggered device with asynchronous preset and clear

Characteristic Table Excitation Table

Preset Q
D Q- Q+ Qn Qn+1 D
0 0 0
D 0 0 0
0 1 0
Clk 0 1 1
1 0 1
Clea Q
r 1 1 1 1 0 0
1 1 1
Q- is the state just before the clock pulse
Q+ is the state just after the clock pulse
T
h
i
The Preset and Clear inputs are active-LOW, s
and 'asynchronous', meaning that they force The actual behaviour is very simple: the
the device to be in one or other state tstate of the D input immediately before the
a
irrespective of the D and Clock inputs. low
b to high clock transition appears at the
loutput after the transition, subject to a small
epropagation delay.
s
h
o
Sequential circuits built with D-type flip flops only have one next-state 'calculator' per w
s
device rather than the two required by JK, but the Boolean expression, and hence the
circuitry, are likely to be more complicated. w
h
a
t
n 11
e
e
3-bit Asynchronous/ripple Counter using D-type Flip Flops
Note that the D input for each flip flop is tied to Q to obtain the 'toggle' behaviour. Also, because this is a +ve edge triggered
device, the clock to the next flip flop also comes fromQ .

Since Preset and Clear are active LOW, these inputs must be tied to +5 V to inactivate them.

Preset Q1 Preset Q2 Preset Q3

D1 D2 D3
And so on...
Clk Clk Clk
Clea Q1 Clea Q2 Clea Q3
+5 V r +5 V r +5 V r

Clock

Q1
Ideal waveforms
Q2

Q3

Exercise: Work out the next state excitation equations for D1, D2 and D3 to make a synchronous counter using D-
type flip flops. Hint: D1 is obvious. D2 and D3 need truth tables that show desired next state as a function of current
outputs. 12
3-bit Synchronous Counter using D-type Flip Flops – example of FSM design
procedure
State Assignmen Next state Next state of Next state of Next state of
t Q3 Q2 Q3 = D3+ Q2 = D2+ Q1 = D1+
Q1
0 0 0 0 0 0 1 0 0 1 K-map for D2+:
1 0 0 1 0 1 0 0 1 0
2 0 1 0 0 1 1 0 1 1
3 0 1 1 1 0 0 1 0 0 Q2Q1 00 01 11 10
4 1 0 0 1 0 1 1 0 1
5 1 0 1 1 1 0 1 1 0 Q3
6 1 1 0 1 1 1 1 1 1 0 0 1 0 1
7 1 1 1 0 0 0 0 0 0

The table identifies the next state (and hence D input) of each flip flop that will 1 0 1 0 1
make the circuit generate a standard binary count sequence when clocked.

The next stage is to design 'next state' logic circuits for D3, D2, D1.

D1 is obvious from the table: D1+ = Q1

K-map for D3+:

From the Karnaugh-maps (K-maps), work out Boolean expressions for D2+ and D3+.
Q2Q1 00 01 11 10
The results confirm why JK flip-flops are the preferred storage element for
synchronous counters! Q3
0 0 0 1 0
This circuit has no external inputs, but one possibility might be a control that allows
it to be used as an UP or DOWN counter.
1 1 1 0 1
A further degree of complexity would be to allow the circuit to respond to the
UP/DOWN input only when it is in (say) State 0. This requires a full state transition
diagram, which is beyond the scope of the current module.

In practice, because counters are very common digital circuit elements, it isn't
necessary to design them from scratch: many varieties are available, both
asynchronous and synchronous, which can be cascaded to make a counter of any
reasonable length. 13
Modulo-N counter/frequency divider
Q0

It's not always the case that the count sequence needed is an exact
power of two, especially in an application like a frequency divider.
Q3
Integrated circuit counter devices are usually provided with a clear input
(set outputs to zero), which can be exploited to make the counter clear
itself when a particular output value appears. For example, this circuit clear
implements a modulo eleven (=1011 2) counter. Selected waveforms
from a practical implementation to right. clock

&

Q3 Q2 Q1 Q0 Closeup of
(MSB) 1010 to
0000
4 bit counter transiti
Clock clear on

Why is it not necessary to detect explicitly the value '1011',

which would require a 4 input AND gate, and one inverter on
output Q2?

How could this circuit be modified to count from zero and stop
at the final value (rather than reset to zero)? A pulse on the
clear input would reset the count to zero and repeat the Same, with 6
sequence. Note that this is a central element in a additional gate
possible implementation of the RS232 transmitter delays (inverters)
assignment. in feedback
path. Arrows
show causal
links.

14
Serial-in Parallel-out Shift Register
Z0 Z1 Z2 Z3

Serial data Preset Q0 Preset Q1 Preset Q2 Preset Q3

input

D0 D1 D2 D3
And so on...
Clock Clk Clk Clk Clk
Clea Q0 Clea Q1 Clea Q2 Clea Q3
r +5 V r +5 V r +5 V r
+5 V

All flip-flops are clocked simultaneously. Sequential data fed to the serial data input, with transitions synchronised to the clock
waveform, will be transferred from one device to the next, and after 4 clock pulses be available in parallel at outputs Z0-Z3.

Various 'flavours' of shift register can be built: this is serial-in, parallel-out (SIPO). Also commonly used are PISO, PIPO.

Typical waveforms

Time

Clock

Data input

Z0

Z1

Z2
15
Multiplexer/data selector
Four input Multiplexer

Data inputs
Output, Y Truth Table of four input multiplexer
I0 (based on 74LS153)
x = don't care
I1 A B G Y
MUX x x H L
I2
0 0 L I0
I3 0 1 L I1
1 0 L I2
1 1 L I3

Select inputs A B Strobe/enable See also 74LS151, 8 to1 multiplexer, datasheet

G included with Asynchronous Serial Data
transmission assignment documentation.
This device is basically a switch, in which one of inputs I0 – I3 is routed
through to the output, Y, depending on the state of inputs A and B

Input G enables or disables the whole device, and can be used when
multiplexers are cascaded to handle more inputs.

How could two of these devices be used this way to make an 8 to 1

multiplexer?

The name 'multiplexer' comes from its original application as a way of

transmitting digital data from a number of sources down a single
channel, by enabling each source in turn onto the channel. The reverse
operation is performed by a demultiplexer – see later.

16
Multiplexer/data selector – what's inside
Four input Multiplexer Logic diagram for a four input multiplexer

Data inputs Select inputs Strobe/enable

A G
Output, Y
I0 B

I1 1
MUX
I2 1 1
I3
A B

&
I0
Select inputs A B Strobe/enable
G
&
I1
Y
Actual circuits may have two or more
&
strobe/enable inputs, to facilitate cascading
devices and separate the strobe and enable
functions. The output may also be available in &
I2
true and complement forms.

Total expression for the data output

&
Y =I 0 ABG + I1 ABG + I 2 ABG + I 3 ABG I3

Decoding Matrix

= crosspoint connected

17
Other applications of Multiplexers - This concept can be extended by realising that as well as fixed
combinational logic logic levels, it's possible to connect a signal to each data input.

Consider for example how P is related to input variable C (if at

A multiplexer can implement combinational logic directly from all – it may be constant) on each pair of rows of the Truth Table:
the Truth Table in a way that avoids wiring individual gates,
otherwise known as a 'random logic' implementation. It means AB C Parity
that the same basic circuit element (the multiplexer) can be Bit, Y
C I0
'programmed' to realise any required function of a certain P
number of inputs. 00 0 1
00 1 0 C I1
Suppose we have an 8 to 1 multiplexer and want to generate 01 0 0
01 1 1 C I2 MUX
an 'odd' parity bit from three inputs ABC (see Section 1):
10 0 0
10 1 1 C I3
11 0 1
11 1 0
ABC Parity Y
Bit, 1 I0
P
Hardwired inputs

0 Select A B
000 1
0 I1
001 0
010 0 1
0 I2 MUX Now the function can be implemented more compactly using a
011 1 four to one multiplexer if the Select inputs are connected to A
100 0 1 I3
1 and B, and I0 to I3 are connected to C or C as shown. The
101 1 C
only additional logic required is one inverter to generate .
110 1 0 I4
111 0 This is the Variable Entered K-Map technique for logic design.
I5

Select I6
A B C B 0 1
A
I7 0 C C
1 C C

18
Variable Entered Maps (example from a Year 2 Digital Design module)

Consider this example: Plot a VEM using A as the map-entered variable.

DCB A F B 0 1
0 000 0 0 DC
1 000 1 0
2 001 0 1 00
3 001 1 0
4 010 0 0
5 010 1 1 01
6 011 0 1
7 011 1 1
8 100 0 0 11
9 100 1 0
10 101 0 0
11 101 1 1 10
12 110 0 1
13 110 1 0
14 111 0 1
15 111 1 1

19
Demultiplexer/decoder
(e.g. 74LS138)

Voltage Truth Table (from manufacturer's datasheet)

Outputs
Select inputs
C Y0

B Y1

A Y2
Enable inputs
G1 Y3
DEMUX Y4
G2A Y5
G2B Y6

Y7

This device has active LOW outputs, three Select inputs and three Enable (G) inputs.
To activate the outputs, G1 must be HIGH and BOTH G2A and G2B must be LOW,
in which case one of outputs Y0-Y7 will be low.

How would you connect two such devices to make a 16 output decoder?

20
Demultiplexer application: part of RS232 receiver

Count sequence, C Y0
0 to 7
B Y1
Y2
A
Strobe Y3
G1 DEMUX Y4
Y5
G2A
0V Y6
G2B
Y7
Y0
Ck Out 7 Ck Out 6 Ck Out 0
Q Q Q
Y1 D D D

Y2
Serial data input
Y3

Y4

Example
Y5 serial input sequence

Y6
The demultiplexer acts as a router to distribute a strobe (clock) pulse to a series of D-type flip
flops in a sequence controlled by the Select inputs CBA. All Data (D) inputs are connected
Y7in
parallel to the input data sequence. After Y7, the eight D-types would contain the bit pattern
01011001 for the input shown. 21
Decoder as logic function generator

Since the device decodes all possible combinations of its inputs, any three input Truth Table can be
implemented directly. Since the 74LS138 has active LOW outputs, a 5-input NAND gate would be
suitable in this case.

Is there a more efficient implementation that could use an output logic gate with fewer inputs?

F(CBA) = (0, 1, 3, 5, 6)
C Y0
CBA Logic
Function B Y1
000 1
001 1 A DEMUX Y2
010 0
011 1 G1 Y3
100 0
G2A Y4
101 1
110 1 G2B Y5
111 0
Y6

Y7

22
Decoders in memory matrix

Computer memory systems are typically organised in two-dimensional arrays, 'stacked' to sufficient depth to provide
the word length needed. Access to a single memory location is done by orthogonal sets of X and Y address lines,
each of which are decoders of half the address bits. The addressed location is the crosspoint where both X and Y
lines are enabled (active).

In this 64 location example, assuming the Y part is the upper three bits, the six bit address 101 011 accesses the
2
crosspoint highlighted.

C Y0

B Y1

A Y2
G1 Y3
DEMUX Y4
G2A Y5
G2B Y6 X-address lines
Y-address

Y7
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
lines

DEMUX

G2A
G1

G2
B
C
B
A

23
Summary
This section has covered digital logic design and applications based on higher-level circuit
elements, including:

• R-S, J-K and D-type Flip-Flops

• Counters, asynchronous and asynchronous: Modulo-N counter. Introduction to Sequential

Circuits.

• Shift-registers

• Multiplexers/data selectors and applications in Variable Entered maps for combinational

circuits

• Demultiplexers/decoders. Use in combinational circuits and memory matrix

implementation

24