CLEVO E412x - 6-7P-E4124-002 PDF

Preface
Notebook Computer
E4120 / E4121-C / E4125-C / E4121D-C
Service Manual
Preface
I
Preface
Notice
The company reserves the right to revise this publication or to change its contents without notice. Information contained
herein is for reference only and does not constitute a commitment on the part of the manufacturer or any subsequent ven-
dor. They assume no responsibility or liability for any errors or inaccuracies that may appear in this publication nor are
they in anyway responsible for any loss or damage resulting from the use (or misuse) of this publication.
This publication and any accompanying software may not, in whole or in part, be reproduced, translated, transmitted or
reduced to any machine readable form without prior consent from the vendor, manufacturer or creators of this publica-
tion, except for copies kept by the user for backup purposes.
Brand and product names mentioned in this publication may or may not be copyrights and/or registered trademarks of
their respective companies. They are mentioned for identification purposes only and are not intended as an endorsement
of that product or its manufacturer.
Preface
Version 1.0
March 2010
Trademarks
Intel, Celeron and Intel Core are trademarks of Intel Corporation.
Windows is a registered trademark of Microsoft Corporation.
Other brand and product names are trademarks and/or registered trademarks of their respective companies.
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Preface
About this Manual

This manual is intended for service personnel who have completed sufficient training to undertake the maintenance and
inspection of personal computers.
It is organized to allow you to look up basic information for servicing and/or upgrading components of the E4120 /
E4121-C / E4125-C / E4121D-C series notebook PC.
The following information is included:
Chapter 1, Introduction, provides general information about the location of system elements and their specifications.
Chapter 2, Disassembly, provides step-by-step instructions for disassembling parts and subsystems and how to upgrade
elements of the system.
Appendix A, Part Lists
Preface
Appendix B, Schematic Diagrams
III
Preface
IMPORTANT SAFETY INSTRUCTIONS

Follow basic safety precautions, including those listed below, to reduce the risk of fire, electric shock and injury to per-
sons when using any electrical equipment:
1. Do not use this product near water, for example near a bath tub, wash bowl, kitchen sink or laundry tub, in a wet
basement or near a swimming pool.
2. Avoid using a telephone (other than a cordless type) during an electrical storm. There may be a remote risk of elec-
trical shock from lightning.
3. Do not use the telephone to report a gas leak in the vicinity of the leak.
4. Use only the power cord and batteries indicated in this manual. Do not dispose of batteries in a fire. They may
explode. Check with local codes for possible special disposal instructions.
5. This product is intended to be supplied by a Listed Power Unit with an AC Input of 100 - 240V, 50 - 60Hz, DC Output
of 19V, 3.42A OR 18.5V, 3.5A (65 Watts) minimum AC/DC Adapter.
Preface
CAUTION
Always disconnect all telephone lines from the wall outlet before servicing or disassembling this equipment.
TO REDUCE THE RISK OF FIRE, USE ONLY NO. 26 AWG OR LARGER,

TELECOMMUNICATION LINE CORD
This Computers Optical Device is a Laser Class 1 Product
IV
Preface
Instructions for Care and Operation

The notebook computer is quite rugged, but it can be damaged. To prevent this, follow these suggestions:
1. Dont drop it, or expose it to shock. If the computer falls, the case and the components could be damaged.
Do not expose the computer Do not place it on an unstable Do not place anything heavy
to any shock or vibration. surface. on the computer.
2. Keep it dry, and dont overheat it. Keep the computer and power supply away from any kind of heating element. This
is an electrical appliance. If water or any other liquid gets into it, the computer could be badly damaged.
Do not expose it to excessive Do not leave it in a place Dont use or store the com- Do not place the computer on
Preface
heat or direct sunlight. where foreign matter or mois- puter in a humid environment. any surface which will block
ture may affect the system. the vents.
3. Follow the proper working procedures for the computer. Shut the computer down properly and dont forget to save
your work. Remember to periodically save your data as data may be lost if the battery is depleted.
Do not turn off the power Do not turn off any peripheral Do not disassemble the com- Perform routine maintenance
until you properly shut down devices when the computer is puter by yourself. on your computer.
all programs. on.
V
Preface
4. Avoid interference. Keep the computer away from high capacity transformers, electric motors, and other strong mag-
netic fields. These can hinder proper performance and damage your data.
5. Take care when using peripheral devices.
Use only approved brands of Unplug the power cord before

peripherals. attaching peripheral devices.
Power Safety
Preface
The computer has specific power requirements:

Only use a power adapter approved for use with this computer.
Your AC adapter may be designed for international travel but it still requires a steady, uninterrupted power supply. If you are
unsure of your local power specifications, consult your service representative or local power company.
Power Safety The power adapter may have either a 2-prong or a 3-prong grounded plug. The third prong is an important safety feature; do
Warning not defeat its purpose. If you do not have access to a compatible outlet, have a qualified electrician install one.
Before you undertake When you want to unplug the power cord, be sure to disconnect it by the plug head, not by its wire.
any upgrade proce- Make sure the socket and any extension cord(s) you use can support the total current load of all the connected devices.
dures, make sure that Before cleaning the computer, make sure it is disconnected from any external power supplies.
you have turned off the
power, and discon-
nected all peripherals Do not plug in the power Do not use the power cord if Do not place heavy objects
and cables (including cord if you are wet. it is broken. on the power cord.
telephone lines). It is
advisable to also re-
move your battery in
order to prevent acci-
dentally turning the
machine on.
VI
Preface
Battery Precautions
Only use batteries designed for this computer. The wrong battery type may explode, leak or damage the computer.
Do not continue to use a battery that has been dropped, or that appears damaged (e.g. bent or twisted) in any way. Even if the
computer continues to work with a damaged battery in place, it may cause circuit damage, which may possibly result in fire.
Recharge the batteries using the notebooks system. Incorrect recharging may make the battery explode.
Do not try to repair a battery pack. Refer any battery pack repair or replacement to your service representative or qualified service
personnel.
Keep children away from, and promptly dispose of a damaged battery. Always dispose of batteries carefully. Batteries may explode
or leak if exposed to fire, or improperly handled or discarded.
Keep the battery away from metal appliances.
Affix tape to the battery contacts before disposing of the battery.
Do not touch the battery contacts with your hands or metal objects.
Battery Guidelines
The following can also apply to any backup batteries you may have.
Preface
If you do not use the battery for an extended period, then remove the battery from the computer for storage.
Before removing the battery for storage charge it to 60% - 70%.
Check stored batteries at least every 3 months and charge them to 60% - 70%.

Battery Disposal
The product that you have purchased contains a rechargeable battery. The battery is recyclable. At the end of its useful life, under var-
ious state and local laws, it may be illegal to dispose of this battery into the municipal waste stream. Check with your local solid waste
officials for details in your area for recycling options or proper disposal.
Caution
Danger of explosion if battery is incorrectly replaced. Replace only with the same or equivalent type recommended by the manufacturer.
Discard used battery according to the manufacturers instructions.
Battery Level
Click the battery icon in the taskbar to see the current battery level and charge status. A battery that drops below a level of 10%
will not allow the computer to boot up. Make sure that any battery that drops below 10% is recharged within one week.
VII
Preface
Related Documents
You may also need to consult the following manual for additional information:
Users Manual on CD
This describes the notebook PCs features and the procedures for operating the computer and its ROM-based setup pro-
gram. It also describes the installation and operation of the utility programs provided with the notebook PC.
Preface
VIII
Preface
Contents
Introduction ..............................................1-1 Part Lists ..................................................A-1
Overview .........................................................................................1-1 Part List Illustration Location ........................................................ A-2
System Specifications .....................................................................1-2 Top (E4120 / E4121-C / E4121D-C) ............................................. A-3
External Locator - Top View with LCD Panel Open ......................1-4 Top (E4125) ................................................................................... A-4
External Locator - Front & Right side Views .................................1-5 Bottom ........................................................................................... A-5
External Locator - Left Side & Rear View .....................................1-6 LCD (E4120 / E4121-C) ................................................................ A-6
External Locator - Bottom View .....................................................1-7 LCD (E4125) ................................................................................. A-7
Mainboard Overview - Top (Key Parts) .........................................1-8 LCD (E4121D-C) .......................................................................... A-8
Mainboard Overview - Bottom (Key Parts) ....................................1-9 HDD ............................................................................................... A-9
Mainboard Overview - Top (Connectors) .....................................1-10 Blu-Ray Combo ........................................................................... A-10
Mainboard Overview - Bottom (Connectors) ...............................1-11 DVD-Super Multi Drive .............................................................. A-11
Disassembly ...............................................2-1 Schematic Diagrams................................. B-1
Preface
Overview .........................................................................................2-1 System Block Diagram ...................................................................B-2
Maintenance Tools ..........................................................................2-2 Clock Generator ..............................................................................B-3
Connections .....................................................................................2-2 Processor 1/7 ...................................................................................B-4
Maintenance Precautions .................................................................2-3 Processor 2/7 ...................................................................................B-5
Disassembly Steps ...........................................................................2-4 Processor 3/7 ...................................................................................B-6
Removing the Battery ......................................................................2-5 Processor 4/7 ...................................................................................B-7
Removing the Hard Disk Drive .......................................................2-6 Processor 5/7 ...................................................................................B-8
Removing the Optical (CD/DVD) Device ......................................2-8 Processor 6/7 ...................................................................................B-9
Removing the System Memory (RAM) ..........................................2-9 Processor 7/7 .................................................................................B-10
Removing and Installing the Processor .........................................2-11 DDRIII SO-DIMM_0 ...................................................................B-11
Removing the Wireless LAN Module ...........................................2-14 DDRIII SO-DIMM_1 ...................................................................B-12
Removing the 3.75G Module ........................................................2-15 LVDS, Inverter .............................................................................B-13
Removing the Modem ...................................................................2-16 HDMI, CRT ..................................................................................B-14
Removing the Bluetooth Module ..................................................2-17 IBEXPEAK - M 1/9 ......................................................................B-15
Removing the LCD Back Cover (for E4121D-C only) .................2-18 IBEXPEAK - M 2/9 ......................................................................B-16
Removing the LCD Front Cover ...................................................2-20 IBEXPEAK - M 3/9 ......................................................................B-17
Removing the Keyboard ................................................................2-21 IBEXPEAK - M 4/9 ......................................................................B-18
IX
Preface
IBEXPEAK - M 5/9 ..................................................................... B-19

IBEXPEAK - M 6/9 ..................................................................... B-20
IBEXPEAK - M 7/9 ..................................................................... B-21
IBEXPEAK - M 8/9 ..................................................................... B-22
IBEXPEAK - M 9/9 ..................................................................... B-23
New Card, Mini PCIE .................................................................. B-24
CCD, 3G, TPM ............................................................................. B-25
Card Reader, LAN (JMB251) ...................................................... B-26
LAN (JMC251), SATA HDD, ODD ........................................... B-27
Audio Codec VIA 1812 ................................................................ B-28
KBC-ITE IT8502E ....................................................................... B-29
LED, MDC, BT ............................................................................ B-30
USB, Fan, TP, Multi Con1 ........................................................... B-31
5VS, 3VS, 1.05VS ........................................................................ B-32
Preface
Power 3.3V/5V ............................................................................. B-33

Power 1.5V/0.75V/1.8VS ............................................................. B-34
Power 1.1VS_VTT ....................................................................... B-35
Power VGFX_CORE ................................................................... B-36
V-Core .......................................................................................... B-37
DC-In, Charger ............................................................................. B-38
Click Board .................................................................................. B-39
Audio / USB / RJ11 Board ........................................................... B-40
Power Switch & LID Board ......................................................... B-41
X
Introduction
Chapter 1: Introduction
Overview
This manual covers the information you need to service or upgrade the E4120 / E4121-C / E4125-C / E4121D-C series
notebook computer. Information about operating the computer (e.g. getting started, and the Setup utility) is in the Users
Manual. Information about drivers (e.g. VGA & audio) is also found in Users Manual. That manual is shipped with the
computer.
Operating systems (e.g. Windows 7, Windows Vista, etc.) have their own manuals as do application software (e.g. word
processing and database programs). If you have questions about those programs, you should consult those manuals.
1.Introduction
The E4120 / E4121-C / E4125-C / E4121D-C series notebook is designed to be upgradeable. See Disassembly on page 2
- 1 for a detailed description of the upgrade procedures for each specific component. Please note the warning and safety
information indicated by the symbol.
The balance of this chapter reviews the computers technical specifications and features.
Overview 1 - 1
Introduction
System Specifications
Processor Core Logic Keyboard & Pointing Device
Intel Core i7-620M Processor: Intel HM55 Chipset Isolated WinKey Keyboard
(2.66GHz) Built-in TouchPad with Multi-Gesture
Display Functionality
32nm (32 Nanometer) Process Technology,
4MB L2 Cache & 1066MHz FSB - TDP 35W 14.0 / 35.56cm 16:9 HD (1366 * 768) Interface
rPGA988A Socket P Package
Memory Three USB 2.0 Ports
Intel Core i5-540M Processor:
(2.53GHz) Dual Channel DDRIII (DDR3) One External Monitor Port
32nm (32 Nanometer) Process Technology, Two 204 Pin SO-DIMM sockets supporting One HDMI Out Port
3MB L2 Cache & 1066MHz FSB - TDP 35W DDR3 1066 MHz One Headphone-Out Jack
rPGA988A Socket P Package Memory Expandable up to 4GB (using 2GB One Microphone-In Jack
One RJ-45 LAN Jack
1.Introduction
SO-DIMM Modules)
One RJ-11 Modem Jack
(2.4GHz) Video One DC-In Jack
3MB L2 Cache & 1066MHz FSB - TDP 35W Intel HM55 Integrated Video: Card Reader
rPGA988A Socket P Package High Preference 3D/2D Graphic Accelerator
Shared Memory Architecture of up to 1748MB Embedded 7-in-1 Card Reader (MS/ MS Pro/
Intel Core i5-430M Processor: SD/ Mini SD/ MMC/ RS MMC/ MS Duo) Note:
Supports Microsoft DirectX10 Compatible
(2.26GHz) MS Duo/ Mini SD/ RS MMC Cards require a
32nm (32 Nanometer) Process Technology, BIOS PC adapter
3MB L2 Cache & 1066MHz FSB, - TDP 35W
rPGA988A Socket P Package One 32Mbit SPI Flash ROM Slots
Phoenix BIOS
Intel Core i3-350M Processor: One ExpressCard 34 Slot Supporting USB &
(2.26GHz) Storage PCIe Interfaces
32nm (32 Nanometer) Process Technology, Two Mini-Card Slots with PCIe (Slot 1) & USB
3MB L2 Cache & 1066MHz FSB - TDP 35W One Changeable 12.7mm(h) Super Multi/Blu- (Slot 2) interface:
rPGA988A Socket P Package ray Combo Optical Device Drive with SATA Slot 1 for WLAN Module (Factory Option)
Interface Slot 2 for 3.75G Module (Factory Option)
One Changeable 2.5" / 9.5 mm (h) HDD with
(2.13GHz) SATA (Serial) Interface
3MB L2 Cache & 1066MHz FSB - TDP 35W Audio
rPGA988A Socket P Package
High Definition Audio Interface
3D Enhanced Stereo System
Built-In Microphone
2 * Built-In Speakers
1 - 2 System Specifications
Introduction
Communication Security
56K Fax/Modem Security (Kensington Type) Lock Slot

Built-In 10/100/1000Mb Base-TX Ethernet LAN BIOS Password
Intel WiFi Link 1000 (802.11 b/g/n) Half Mini- Operating System
Card PCIe WLAN Module (Factory Option)
Windows Vista (with Service Pack 2)
3rd Party WLAN 802.11b/g/n Half Mini-Card
Windows 7
Module with PCIe Interface(Option)
Bluetooth 2.1 + EDR (Enhanced Data Rate) Design Feature
Module (Factory Option)
IMR Changeable LCD Back Covers (Factory
1.3M Pixel PC Camera Module with USB Option)
interface (Factory Option)
Environmental Spec
UMTS/HSPDA-based 3.75G Module with USB
1.Introduction
Half Mini-Card Interface (Factory Option) Temperature
Quad-band GSM/GPRS (850 MHz, 900 MHz, Operating: 5C - 35C
1800 MHz, 1900 MHz) Non-Operating: -20C - 60C
UMTS WCDMA FDD (2100 MHz) Relative Humidity
Note that UMTS modes CAN NOT be used Operating: 20% - 80%
in North America Non-Operating: 10% - 90%
Dimensions & Weight

Power Management
340mm (w) * 238mm (d) * 15.6 - 35.2mm (h)
Supports Wake on LAN 2.2 kg with 6 Cell Battery & ODD
Supports Wake on USB
Power
Full Range AC/DC Adapter

AC input 100 - 240V, 50 - 60Hz,
DC Output 19V, 3.42A or 18.5V, 3.5A (65
Watts)
Removable 6 Cell Smart Lithium Ion Battery
Pack 48.84WH
(Factory Option) Removable 6 Cell Smart
Lithium Ion Battery Pack 62.16WH
System Specifications 1 - 3
Introduction
Figure 1
External Locator - Top View with LCD Panel Open
Top View
1. Optional Built-In 1
PC Camera
2. LCD
3. Power Button
4. Hot Key Buttons
5. LED Status
Indicators
6. Keyboard
7. Built-In 2
1.Introduction
Microphone
8. Touchpad &
Buttons
5 4 3
1 - 4 External Locator - Top View with LCD Panel Open

Introduction
External Locator - Front & Right side Views Figure 2

Front Views
1. LED Power
Indicators
1.Introduction
Figure 3
Right Side Views
1. Microphone-In
Jack
2. Headphone-Out
4 5 Jack
1 2 3 6 3. USB 2.0 Port
4. RJ-11 Phone
Jack
5. Optical Device
Drive Bay
6. Security Lock
Slot
External Locator - Front & Right side Views 1 - 5

Introduction
External Locator - Left Side & Rear View

Figure 4
Left Side View
1. DC-In Jack
2. External Monitor
Port
3. RJ-45 LAN Jack
4. HDMI-Out Port
5. Vent/Fan Intake/ 7
3 4 6 6
Outlet 2 5 8
6. 2 * USB 2.0 Ports 1
7. ExpressCard Slot
1.Introduction
8. 7-in-1 Card
Reader
Figure 5
Rear View
1. Battery 1
1 - 6 External Locator - Left Side & Rear View

Introduction
External Locator - Bottom View

Figure 6
Bottom View
1. Battery
2. Component Bay
Cover
1 1 3. Vent/Fan Intake/
Outlet
3 4. Hard Disk Bay
Cover
5. 3.75G/HSPA
1.Introduction
3 2 3 2 USIM Card
3 Cover (optional)
3
4 3 4 5
WITHOUT 3G WITH 3G

Overheating
To prevent your com-

puter from overheating
make sure nothing
blocks the vent/fan in-
takes while the com-
puter is in use.
External Locator - Bottom View 1 - 7

Introduction
Figure 7 Mainboard Overview - Top (Key Parts)

Mainboard Top
Key Parts
1. ExpressCard
Connector
2. JMC251
3. KBC ITE IT8512E
1
1.Introduction
3 4
3
1 - 8 Mainboard Overview - Top (Key Parts)

Introduction
Mainboard Overview - Bottom (Key Parts) Figure 8

Mainboard Bottom
Key Parts
1. CPU Socket (no

7 CPU installed)
2. Memory Slots
DDR3 SO-DIMM
3. Intel HM55
4. Mini-Card
Connector (3G
Module)
6
5. Audio Codec
1.Introduction
6. Mini-Card
Connector (WLAN
Module)
1 7. Card Reader
Socket
2
4
Mainboard Overview - Bottom (Key Parts) 1 - 9

Introduction
Figure 9 Mainboard Overview - Top (Connectors)

Mainboard Top
Connectors
1. USB Port 1 1
2. Microphone
Cable Connector
3. Audio Cable
Connector
4. TouchPad Cable
Connector
5. Keyboard Cable
Connector
1.Introduction
9
2 10
6
8
5 11
4
7
3
1 - 10 Mainboard Overview - Top (Connectors)

Introduction
Mainboard Overview - Bottom (Connectors) Figure 10

Mainboard Bottom
Connectors
1. CCD Connector
2. LCD Cable
Connector
3. CMOS Cable
Connector
1 4. BT Cable
Connector
5. ODD Connector
2 6. HDD Connector
1.Introduction
7. MDC Cable
8 Connector
8. Fan Cable
Connector
7
5 6
Mainboard Overview - Bottom (Connectors) 1 - 11

Introduction
1.Introduction
1 - 12
Disassembly
Chapter 2: Disassembly
Overview
This chapter provides step-by-step instructions for disassembling the E4120 / E4121-C / E4125-C / E4121D-C series
notebooks parts and subsystems. When it comes to reassembly, reverse the procedures (unless otherwise indicated).
We suggest you completely review any procedure before you take the computer apart.
Procedures such as upgrading/replacing the RAM, optical device and hard disk are included in the Users Manual but are
repeated here for your convenience.
2.Disassembly
To make the disassembly process easier each section may have a box in the page margin. Information contained under
the figure # will give a synopsis of the sequence of procedures involved in the disassembly procedure. A box with a
lists the relevant parts you will have after the disassembly process is complete. Note: The parts listed will be for the dis-
Information
assembly procedure listed ONLY, and not any previous disassembly step(s) required. Refer to the part list for the previ-
ous disassembly procedure. The amount of screws you should be left with will be listed here also.
A box with a will also provide any possible helpful information. A box with a contains warnings.
An example of these types of boxes are shown in the sidebar.

Warning
Overview 2 - 1
Disassembly
NOTE: All disassembly procedures assume that the system is turned OFF, and disconnected from any power supply (the
battery is removed too).
Maintenance Tools
The following tools are recommended when working on the notebook PC:
M3 Philips-head screwdriver
M2.5 Philips-head screwdriver (magnetized)
M2 Philips-head screwdriver
Small flat-head screwdriver
Pair of needle-nose pliers
Anti-static wrist-strap
2.Disassembly
Connections
Connections within the computer are one of four types:
Locking collar sockets for ribbon connectors To release these connectors, use a small flat-head screwdriver to
gently pry the locking collar away from its base. When replac-
ing the connection, make sure the connector is oriented in the
same way. The pin1 side is usually not indicated.
Pressure sockets for multi-wire connectors To release this connector type, grasp it at its head and gently
rock it from side to side as you pull it out. Do not pull on the
wires themselves. When replacing the connection, do not try to
force it. The socket only fits one way.
Pressure sockets for ribbon connectors To release these connectors, use a small pair of needle-nose pli-
ers to gently lift the connector away from its socket. When re-
placing the connection, make sure the connector is oriented in
the same way. The pin1 side is usually not indicated.
Board-to-board or multi-pin sockets To separate the boards, gently rock them from side to side as
you pull them apart. If the connection is very tight, use a small
flat-head screwdriver - use just enough force to start.
2 - 2 Overview
Disassembly
Maintenance Precautions
The following precautions are a reminder. To avoid personal injury or damage to the computer while performing a re-
moval and/or replacement job, take the following precautions: Power Safety
Warning
1. Don't drop it. Perform your repairs and/or upgrades on a stable surface. If the computer falls, the case and other
Before you undertake
components could be damaged. any upgrade proce-
2. Don't overheat it. Note the proximity of any heating elements. Keep the computer out of direct sunlight. dures, make sure that
3. Avoid interference. Note the proximity of any high capacity transformers, electric motors, and other strong mag- you have turned off the
netic fields. These can hinder proper performance and damage components and/or data. You should also monitor power, and discon-
the position of magnetized tools (i.e. screwdrivers). nected all peripherals
and cables (including
4. Keep it dry. This is an electrical appliance. If water or any other liquid gets into it, the computer could be badly telephone lines). It is
damaged. advisable to also re-
5. Be careful with power. Avoid accidental shocks, discharges or explosions. move your battery in
2.Disassembly
Before removing or servicing any part from the computer, turn the computer off and detach any power supplies. order to prevent acci-
When you want to unplug the power cord or any cable/wire, be sure to disconnect it by the plug head. Do not pull on the wire. dentally turning the
machine on.
6. Peripherals Turn off and detach any peripherals.
7. Beware of static discharge. ICs, such as the CPU and main support chips, are vulnerable to static electricity.
Before handling any part in the computer, discharge any static electricity inside the computer. When handling a
printed circuit board, do not use gloves or other materials which allow static electricity buildup. We suggest that
you use an anti-static wrist strap instead.
8. Beware of corrosion. As you perform your job, avoid touching any connector leads. Even the cleanest hands pro-
duce oils which can attract corrosive elements.
9. Keep your work environment clean. Tobacco smoke, dust or other air-born particulate matter is often attracted
to charged surfaces, reducing performance.
10. Keep track of the components. When removing or replacing any part, be careful not to leave small parts, such as
screws, loose inside the computer.
Cleaning
Do not apply cleaner directly to the computer, use a soft clean cloth.
Do not use volatile (petroleum distillates) or abrasive cleaners on any part of the computer.
Overview 2 - 3
Disassembly
Disassembly Steps
The following table lists the disassembly steps, and on which page to find the related information. PLEASE PERFORM
THE DISASSEMBLY STEPS IN THE ORDER INDICATED.
To remove the Battery: To remove the Modem:

1. Remove the battery page 2 - 5 1. Remove the battery page 2 - 5
2. Remove the modem page 2 - 16
To remove the HDD:
1. Remove the battery page 2 - 5 To remove the Bluetooth Module:
2. Remove the HDD page 2 - 6 1. Remove the battery page 2 - 5
2. Remove the Bluetooth page 2 - 17
To remove the Optical Device:
2.Disassembly
1. Remove the battery page 2 - 5 To remove the LCD Back Cover (E4121D-C):
2. Remove the Optical device page 2 - 8 1. Remove the battery page 2 - 5
2. Remove the LCD Back Cover page 2 - 18
To remove the System Memory:
1. Remove the battery page 2 - 5 To remove the LCD Front Cover:
2. Remove the system memory page 2 - 9 1. Remove the battery page 2 - 5
2. Remove the LCD Front Cover page 2 - 20
To remove and install a Processor:
1. Remove the battery page 2 - 5 To remove the Keyboard:
2. Remove the processor page 2 - 11 1. Remove the battery page 2 - 5
3. Install the processor page 2 - 13 2. Remove the keyboard page 2 - 21
To remove the WLAN Module:

1. Remove the battery page 2 - 5
2. Remove the wireless LAN page 2 - 14
To remove the 3.75G Module:
1. Remove the battery page 2 - 5
2. Remove the 3.75G page 2 - 15
2 - 4 Disassembly Steps
Disassembly
Removing the Battery

1. Turn the computer off, and turn it over.
Figure 1
2. Slide the latch 1 in the direction of the arrow.
Battery Removal
3. Slide the latch 2 in the direction of the arrow, and hold it in place.
4. Slide the battery 63 in the direction of the arrow 4 . a. Slide the latch and hold
in place.
b. Slide the battery in the di-
a. rection of the arrow.
2 1
2.Disassembly
b.

3. Battery
Removing the Battery 2 - 5

Disassembly
Removing the Hard Disk Drive

Figure 2 The hard disk drive can be taken out to accommodate other 2.5" serial (SATA) hard disk drives with a height of 9.5mm
HDD Assembly (h). Follow your operating systems installation instructions, and install all necessary drivers and utilities (as outlined in
Removal Chapter 4 of the Users Manual) when setting up a new hard disk.
a. Locate the HDD bay Hard Disk Upgrade Process

cover and remove the
screw(s).
1. Turn off the computer, and remove the battery (page 2 - 5).
2. Locate the hard disk bay cover and remove screws 1 & 2 .
a.
2.Disassembly
1 2

HDD System Warning
New HDDs are blank. Before you begin make sure:
You have backed up any data you want to keep from your old HDD.
2 Screws You have all the CD-ROMs and FDDs required to install your operating system and programs.
If you have access to the internet, download the latest application and hardware driver updates for the operating system you plan
to install. Copy these to a removable medium.
2 - 6 Removing the Hard Disk Drive

Disassembly
3. Remove the hard disk bay cover 63 .

4. Grip the tab and slide the hard disk in the direction of arrow 4 . Figure 3
5. Lift the hard disk out of the bay 5 . HDD Assembly
Removal (contd.)
6. Remove the screw 6 - 9 and the adhesive cover 10 from the hard disk 11 .
7. Reverse the process to install a new hard disk (do not forget to replace all the screws and covers).
b. Remove the HDD bay
cover.
d. c. Grip the tab and slide the
b.
HDD in the direction of
the arrow.
d. Lift the HDD assembly
out of the bay.
e. Remove the screw and
adhesive cover.
2.Disassembly
5
3
e.
c. 9
8 6
4 10
7

3. HDD Bay Cover
10. Adhesive Cover
11. HDD
11
4 Screws
Removing the Hard Disk Drive 2 - 7

Disassembly
Figure 4 Removing the Optical (CD/DVD) Device

Optical Device
Removal
2. Locate the RAM & CPU bay cover 1 , and remove screws 2 - 5 .
3. Carefully (a fan and cable are attached to the under side of the cover) lift up the bay cover.
a. Remove the screws.
b. Remove the cover. 4. Carefully disconnect the fan cable 6 , and remove the cover 1 .
c. Remove the screw and 5. Remove the screw at point 7 , and use a screwdriver to carefully push out the optical device 9 at point 8 .
push the optical device 6. Insert the new device and carefully slide it into the computer (the device only fits one way. DO NOT FORCE IT; The
out off the computer at screw holes should line up).
point 8. 7. Restart the computer to allow it to automatically detect the new device.
a. c.
2
2.Disassembly
1
4 7
8
5
b.

1. Component Bay Cover 1
9. Optical Device
9
6
5 Screws
2 - 8 Removing the Optical (CD/DVD) Device

Disassembly
Removing the System Memory (RAM) Figure 5

The computer has two memory sockets for 200 pin Small Outline Dual In-line Memory Modules (SO-DIMM) supporting RAM Module
DDR3 1066MHz. The main memory can be expanded up to 8GB. The SO-DIMM modules supported are 1GB, 2GB and Removal
4GB and DDRIII Modules. The total memory size is automatically detected by the POST routine once you turn on your
computer. a. Locare the memory
socket.
b. Pull the release
Memory Upgrade Process latch(es).
1. Turn off the computer, remove the battery (page 2 - 5) and the component bay cover (page 2 - 8). c. Remove the mod-
ule(s).
2. The RAM module (s) will be visible at point 1 on the main board.
3. Gently pull the two release latches ( 2 & 3 ) on the sides of the memory socket in the direction indicated by the
arrows (Figure 6c).

2.Disassembly
a. b. c. Contact Warning
Be careful not to touch

2 the metal pins on the
modules connecting
4 edge. Even the clean-
1
est hands have oils
which can attract parti-
cles, and degrade the
modules perfor-
3 mance.
4. The RAM module(s) 4 will pop-up (Figure 6d), and you can then remove it.
5. Pull the latches to release the second module if necessary. 4. RAM Module
6. Insert a new module holding it at about a 30 angle and fit the connectors firmly into the memory slot.
7. The modules pin alignment will allow it to only fit one way. Make sure the module is seated as far into the slot as it
will go. DO NOT FORCE the module; it should fit without much pressure.
8. Press the module in and down towards the mainboard until the slot levers click into place to secure the module.
Removing the System Memory (RAM) 2 - 9

Disassembly
Figure 6 9. Replace the bay cover and screws (make sure you reconnect the fan cable before screwing down the bay
RAM Module cover).
Removal (contd.) Note that there are four 5 - 8 cover pins which need to be aligned with slots in the case, to insure a proper cover
fit, before screwing down the bay cover.
d. Properly re-insert the
bay cover pins. d. 5
7
2.Disassembly
10. Restart the computer to allow the BIOS to register the new memory configuration as it starts up.
2 - 10 Removing the System Memory (RAM)

Disassembly
Removing and Installing the Processor

Figure 7
Processor Removal Procedure Processor
1. Turn off the computer, remove the battery (page 2 - 5), and the component bay cover (page 2 - 9). Removal
2. Loosen the CPU heat sink screws in the order 3 , 2 & 1 (the reverse order as indicated on the label).
3. Carefully lift up the heat sink 4 (Figure 7c) off the computer. a. Remove the cover
and Iocate the heat
sink.
a.
b. Loosen the screws
in the order indicat-
ed.
c. Remove the heat
sink.
2.Disassembly

CPU Warning
In order to prevent
damaging the contact
b. c.
pins when removing
1 the CPU, it is neces-
4 sary to first remove the
WLAN module from
2 the computer.

4. Heat Sink
Note: Loosen the screws in the reverse order
3, 2, 1 as indicated on the label.
3 Screws
Removing and Installing the Processor 2 - 11

Disassembly
4. Turn the release latch 6 towards the unlock symbol , to release the CPU (Figure 8a).
Figure 8 5. Carefully (it may be hot) lift the CPU 7 up out of the socket (Figure 8b).
Processor Removal 6. See page 2 - 13 for information on inserting a new CPU.
(contd) 7. When re-inserting the CPU, pay careful attention to the pin alignment, it will fit only one way (DO NOT FORCE IT!).
d. Turn the release latch to
unlock the CPU. d.
e. Lift the CPU out of the
socket.
6
6
2.Disassembly
Unlock Lock
e.

7 Caution
The heat sink, and CPU area in

general, contains parts which are
subject to high temperatures. Al-
low the area time to cool before re-
moving these parts.

7. CPU
2 - 12 Removing and Installing the Processor

Disassembly
Processor Installation Procedure Figure 9

1. Insert the CPU A , pay careful attention to the pin alignment, it will fit only one way (DO NOT FORCE IT!), and turn Processor
the release latch B towards the lock symbol (Figure 9b). Installation
2. Remove the sticker C (Figure 9c) from the heat sink.
3. Insert the heat sink D as indicated in Figure 9c. a. Insert the CPU.
4. Tighten the CPU heat sink screws in the order 1 , 2 & 3 (the order as indicated on the label and Figure 9d). b. Turn the release latch to-
wards the lock symbol.
5. Replace the component bay cover and tighten the screws (page 2 - 11).
c. Remove the sticker from
the heat sink and insert
a. c. the heat sink.
d. Tighten the screws.
2.Disassembly
D C
b. d.
1
Note:
2 Tighten the screws
in the order 1, 2, 3 as
B 3 indicated on the la-
bel.
A. CPU
D. Heat Sink
3 Screws
Removing and Installing the Processor 2 - 13

Disassembly
Figure 10 Removing the Wireless LAN Module

Wireless LAN 1. Turn off the computer, remove the battery (page 2 - 5) and the component bay cover (page 2 - 9).
Module Removal 2. The Wireless LAN module will be visible at point 1 on the mainboard.
3. Carefully disconnect cables 2 - 3 , then remove screw 4 from the module socket.
a. Remove the cover. 4. Lift the Wireless LAN module 5 (Figure 11d) up and off the computer.
b. Disconnect the cables
and remove the screw.
c. Lift the WLAN module
out. a. c.
2.Disassembly
b.
4

5. WLAN Module.
2
1 Screw
2 - 14 Removing the Wireless LAN Module

Disassembly
Removing the 3.75G Module Figure 11

1. Turn off the computer, remove the battery (page 2 - 5) and the component bay cover (page 2 - 9). 3.75G Module
2. The 3.75G module will be visible at point 1 on the mainboard. Removal
3. Carefully disconnect the cable 2 , then remove the screw 3 from the module socket.
4. The 3.75G module 4 will pop-up. a. Remove the cover.
b. Disconnect the cable
5. Lift the 3.75G module (Figure 11d) up and off the computer.
and remove the screw.
c. The 3.75G module will
a. pop up.
d. Lift the 3.75G module
out.
2.Disassembly
d.
1
b. c.

4 4. 3.75G Module.
2
1 Screw
3 4
Removing the 3.75G Module 2 - 15

Disassembly
Figure 12 Removing the Modem

Modem Removal 1. Turn off the computer, turn it over, and remove the battery (page 2 - 5) and the component bay cover (page 2 - 9).
2. The modem will be visible at point 1 on the mainboard.
a. Locate the modem. 3. Remove the screws 2 - 3 and disconnect the cable 4 .
b. Remove the screws and
4. Carefully lift the modem 6 up and off the socket 5 .
disconnect the cable.
c. Lift the modem up and
off the sockets. a. c.
5
2.Disassembly
b.
6
4
6. Modem
3
2 Screws
2 - 16 Removing the Modem

Disassembly
Removing the Bluetooth Module Figure 13

Bluetooth Module
1. Turn off the computer, remove the battery (page 2 - 5), and component bay cover (page 2 - 9).
Removal
2. The Bluetooth module will be visible at point 1 on the mainboard.
3. Remove the screw 2 and turn the module over.
a. Locate the Bluetooth mod-
4. Carefully disconnect the cable 3 and separate the connector 4 (Figure 13b) from the Bluetooth Module. ule.
5. Lift the Bluetooth module 5 (Figure 13c) up and off the computer. b. Remove the screw.
c. Disconnect the cable and
a. the connector from the
Bluetooth module.
d. Lift the Bluetooth module
d. out.
2.Disassembly
1
b. c.
5

3 5. Bluetooth Module
2
1 Screw
Removing the Bluetooth Module 2 - 17

Disassembly
Removing the LCD Back Cover (for E4121D-C only)

1. Turn off the computer, and turn the computer over to remove the battery (page 2 - 5).
Figure 14 2. Open the LCD and carefully remove the rubber screw covers 1 & 2 (2 corner rubber screw covers only) and set
LCD Back Cover them aside.
Removal 3. Remove screws 3 & 4 from the front cover.
4. Carefully slide the cover forward in the direction of the arrows 5 & 6 as illustrated below.
a. Remove the rubber cov- 5. Remove the LCD back cover 7 .
ers and screws.
b. Slide the cover forward.
c. Remove the LCD back
cover. a. b.
1 2
5 6
2.Disassembly
3 4
c.

Rubber Screw Covers
7. LCD Back Cover
After removing the rubber screw covers, place them on a
7
clean dry surface (or attach them to the front cover itself) in
2 Screws order to prevent loss of adhesive.
2 - 18 Removing the LCD Back Cover (for E4121D-C only)

Disassembly
6. Align the replacement cover with the dotted line 8 as illustrated below (and as marked on the cover). Figure 15
LCD Back Cover
Removal (contd)
d.
8 d. Align the replacement
cover and slide forward to
click firmly into place.
10 10
2.Disassembly
9
10
7. Slide the back cover forward until it clicks firmly into place 9 .
8. Run your hands around the sides and front of the cover 10 to make sure it is firmly aligned in place (carefully press
down to make sure the fit is secure).
9. Replace the screws and rubber covers.
Removing the LCD Back Cover (for E4121D-C only) 2 - 19

Disassembly
Figure 16 Removing the LCD Front Cover

LCD Front Cover
1. Turn off the computer, and remove the battery (page 2 - 5), and remove the LCD back cover (page 2 - 18).
Removal
2. Remove the rubber covers and screws 1 - 4 (Figure 16a), then run your finger around the middle of the frame to
carefully unsnap the LCD front cover 5 from the LCD panel.
a. Remove the screws and
unsnap the LCD front 3. After unsnapping all four sides of the LCD front cover, carefully slide the LCD front cover downwards in the direc-
cover from the LCD pan- tion of the arrow 6 (be careful of the LCD hinges at point 7 ).
el. 4. You can now remove the LCD front cover.
b. Slide the LCD panel cov-
er in the direction of the
arrow. a. b.
2 3
5
2.Disassembly
1 5 4
7 7

5. LCD Front Cover Rubber Screw Covers
After removing the rubber screw covers, place them on a

clean dry surface (or attach them to the front cover itself) in
4 Screws order to prevent loss of adhesive.
2 - 20 Removing the LCD Front Cover

Disassembly
Removing the Keyboard

2. Press the four keyboard latches at the top of the keyboard to elevate the keyboard from its normal position (you Figure 17
may need to use a small screwdriver to do this). Keyboard Removal
3. Carefully lift the keyboard up, being careful not to bend the keyboard ribbon cable (Figure 17b).
4. Disconnect the keyboard ribbon cable 5 from the locking collar socket 6 . a. Press the four latches to
5. Carefully lift up the keyboard 7 (Figure 17c) off the computer. release the keyboard.
b. Lift the keyboard up and
disconnect the cable
a. c. from the locking collar.
1 2 3 4 c. Remove the keyboard.
2.Disassembly

Re-Inserting the Key-
board
b. When re-inserting the

keyboard firstly align
the four keyboard tabs
5 at the bottom of the
7 keyboard with the slots
in the case.
6

7. Keyboard
Keyboard Tabs
Removing the Keyboard 2 - 21

Disassembly
2.Disassembly
2 - 22
Part Lists
Appendix A: Part Lists

This appendix breaks down the E4120 / E4121-C / E4125-C / E4121D-C series notebooks construction into a series of
illustrations. The component part numbers are indicated in the tables opposite the drawings.
Note: This section indicates the manufacturers part numbers. Your organization may use a different system, so be sure
to cross-check any relevant documentation.
Note: Some assemblies may have parts in common (especially screws). However, the part lists DO NOT indicate the
total number of duplicated parts used.
Note: Be sure to check any update notices. The parts shown in these illustrations are appropriate for the system at the
A.Part Lists
time of publication. Over the product life, some parts may be improved or re-configured, resulting in new part numbers.
A - 1
Part Lists
Part List Illustration Location

The following table indicates where to find the appropriate part list illustration.
Table A- 1
Part List Illustration
Location
Parts E4120 E4121-C E4125-C E4121D-C
Top page A - 3 page A - 4 page A - 3
Bottom page A - 5
LCD page A - 7 page A - 7 page A - 8

A.Part Lists
HDD page A - 9
Blu-Ray Combo page A - 10
DVD-Super Multi Drive page A - 11
A - 2 Part List Illustration Location

Part Lists
Top (E4120 / E4121-C / E4121D-C)
Figure A - 1
Top
A.Part Lists
(E4120 / E4121-C)
()
Top (E4120 / E4121-C / E4121D-C) A - 3

Part Lists
Top (E4125)
Figure A - 2
A.Part Lists
Top
(E4125)
()
A - 4 Top (E4125)
Part Lists
Bottom
Figure A - 3
Bottom
A.Part Lists
Bottom A - 5
Part Lists
LCD (E4120 / E4121-C)
Figure A - 4

A.Part Lists
LCD
(E4120 / E4121-C)
()
()
()
A - 6 LCD (E4120 / E4121-C)

Part Lists
LCD (E4125)
Figure A - 5

LCD
A.Part Lists

(E4125)

()
()
()
FOR C4801M
FOR C4801M-C
FOR E4121D-C
FOR MOFA
FOR C4801M-C
FOR E4121D-C
FOR E4121D-C
FOR E4121M/D-C
FOR C4801M/-C

LCD (E4125) A - 7
Part Lists
LCD (E4121D-C)
Figure A - 6
A.Part Lists
LCD

(E4121D-C)
()
()
()
FOR C4801M
FOR C4801M-C
FOR E4121D-C
FOR MOFA
FOR C4801M-C
FOR E4121D-C
FOR E4121D-C
FOR E4121M/D-C
FOR C4801M/-C

A - 8 LCD (E4121D-C)
Part Lists
HDD
Figure A - 7
HDD
A.Part Lists

()
HDD A - 9
Part Lists
Blu-Ray Combo
Figure A - 8
A.Part Lists
Blu-Ray Combo
*()
A - 10 Blu-Ray Combo
Part Lists
DVD-Super Multi Drive
Figure A - 9
DVD-Super Multi
A.Part Lists
Drive
*()
DVD-Super Multi Drive A - 11

Part Lists
A.Part Lists
A - 12
Schematic Diagrams
Appendix B: Schematic Diagrams

This appendix has circuit diagrams of the E412P-C notebooks PCBs. The following table indicates where to find the
appropriate schematic diagram.
Diagram - Page Diagram - Page Diagram - Page Table B - 1

System Block Diagram - Page B - 2 IBEXPEAK - M 2/9 - Page B - 16 LED, MDC, BT - Page B - 30 Schematic
Diagrams
Clock Generator - Page B - 3 IBEXPEAK - M 3/9 - Page B - 17 USB, Fan, TP, Multi Con1 - Page B - 31
B.Schematic Diagrams
Processor 1/7 - Page B - 4 IBEXPEAK - M 4/9 - Page B - 18 5VS, 3VS, 1.05VS - Page B - 32
Processor 2/7 - Page B - 5 IBEXPEAK - M 5/9 - Page B - 19 Power 3.3V/5V - Page B - 33
Processor 3/7 - Page B - 6 IBEXPEAK - M 6/9 - Page B - 20 Power 1.5V/0.75V/1.8VS - Page B - 34
Processor 4/7 - Page B - 7 IBEXPEAK - M 7/9 - Page B - 21 Power 1.1VS_VTT - Page B - 35
Processor 5/7 - Page B - 8 IBEXPEAK - M 8/9 - Page B - 22 Power VGFX_CORE - Page B - 36
Processor 6/7 - Page B - 9 IBEXPEAK - M 9/9 - Page B - 23 V-Core - Page B - 37
Processor 7/7 - Page B - 10 New Card, Mini PCIE - Page B - 24 DC-In, Charger - Page B - 38
DDRIII SO-DIMM_0 - Page B - 11 CCD, 3G, TPM - Page B - 25 Click Board - Page B - 39
DDRIII SO-DIMM_1 - Page B - 12 Card Reader, LAN (JMB251) - Page B - 26 Audio / USB / RJ11 Board - Page B - 40 Version Note
LVDS, Inverter - Page B - 13 LAN (JMC251), SATA HDD, ODD - Page B - 27 Power Switch & LID Board - Page B - 41
The schematic dia-
HDMI, CRT - Page B - 14 Audio Codec VIA 1812 - Page B - 28 grams in this chapter
are based upon ver-
IBEXPEAK - M 1/9 - Page B - 15 KBC-ITE IT8502E - Page B - 29
sion 6-7P-E4124-002.
If your mainboard (or
other boards) are a lat-
er version, please
check with the Service
Center for updated di-
agrams (if required).
B - 1
Schematic Diagrams
System Block Diagram
CLICK BOARD
6-71-C4502-D02 Calpella System Block Diagram VDD3,VDD5
14.318 MHz
POWER SWITCH BOARD POWER GPU 1.8VS

POWER SWITCH+HOTKEY X 3 Clock Generator
SLG8SP585V
Memory Termination
6-71-C450S-D02 Arrandale 800/1067 MHz 5V,3V,5VS,3VS,1.5VS,
DDR3 / 1.5V
AUDIO BOARD
PROCESSOR DDRIII
PJ11+USB+EARPHONE+EXT.MIC
SO-DIMM0
rPGA989/988 1.5V,0.75VS(VTT_MEM)
6-71-C410A-D01 SYSTEM SMBUS
0.1"~13 DDRIII
SO-DIMM1 VCORE 1.1VS_VTT
FDI DMI*4
HDMI 0.5"~6.5" <=8"
Sheet 1 of 40 CLICK BOARD CRT CONNECTOR

<15"
INTERNAL
AUDIO BOARD
TOUCH PAD
System Block Synaptic
CR T SW IT CH
GRAPHICS Ibex Peak-M MIC HP
Diagram 810602-1703
LCD CONNECTOR, <8"
Platform RJ-11 IN OUT
INTERNAL
L VD S SW IT CH
GRAPHICS Controller
Hub (PCH) AZALIA INT SPK R
32.768 KHz AMP
MDC
EC Azalia Codec N7101
SPI TPM MODULE INT SPK L
ITE 8502E VIA VT1812
128pins LQFP
1 4*1 4*1. 6mm
MDC CON
33 MHz
INT MIC
LPC 27x27mm
0.5"~11" BIOS 1071 Ball FCBGA AZALIA LINK 24 MHz
SPI
INT. K/B EC SMBUS
PCIE 100 MHz <12"
THERMAL SMART SMART
SENSOR FAN BATTERY
32.768KHz
W83L771AWG
New Card 3G CARD Mini PCIE JMICRO
SOCKET (USB9) SOCKET
<12"
USB2.0 (USB3) (USB2)
JMC251
SATA I/II 3.0Gb/s 480 Mbps
(Optional) LAN CARD READER 25
1"~16" MHz
RJ-45 7IN1
USB0 USB1 USB4 Bluetooth CCD SOCKET
SATA HDD SATA ODD
(USB11) (USB5)
AUDIO
BOARD
B - 2 System Block Diagram

Schematic Diagrams
Clock Generator
CLKGEN POWER
CLOCK GENERATOR
C LK _V C C 1 CL K _ V CC2 3 .3 V S
CL K _ V CC 1
U7
1 15 L 15 *1 5 m li _ sh o rt _ 06
5 V DD _ D OT V D D _ S R C _I / O 18
V DD _ 27 V D D _ C P U _I / O
17
24
29
V DD
V DD
V DD
_ S RC
_ CP U
_ RE F D OT _9 6
3
4
C L K _B U F _ D OT 9 6 _P 1 5
C L K _B U F _ D OT 9 6 _N 15
C 21 3
0 . 1 u_ 1 0 V _X 7 R _ 0 4
C2 0 5
0. 1 u _ 10 V _ X 7R _0 4
C2 1 5
1 u _6 . 3 V _ X5 R _ 0 4 Sheet 2 of 40
D OT _ 96 #
2 7M
6
7
Clock Generator
X OU T 27 2 7 M_ S S
XIN X TA L _ OU T
28 0 .1 u F n e a r t h e e v er y p ow e r p i n
X TA L _ I N 10
S RC_ 1 /S A T A C L K _S A T A 1 5
11
S R C _ 1# / S A T A # C L K _S A T A # 1 5
13 C L K _P C I E _ I C H 1 5
R1 3 0 3 3 _0 4 R E F _0 / C P U _ S E L 30 S RC_ 2 14
15 C LK _ B U F _R E F 1 4 RE F _ 0 /CP U _ S E L S R C _2 # C L K _P C I E _ I C H # 1 5
CL K _ S DA T A 31
CL K _ S CL K 32 S DA 16 C P U _ S T OP # R 1 44 2. 2 1 K _1 % _ 04
S CL C P U _ S T OP # 3 .3 V S 1 . 1V S _V T T
2 20 CL K _ V CC 2
V S S _ DO T CP U_ 1
8 19
9 VSS_ 2 7 C P U _1 # 23 L14 *1 5m i l _s h ort _0 6
VSS_ SATA CP U_ 0 C L K _B U F _ B C L K _ P 15
12 22 C L K _B U F _ B C L K _ N 1 5
21 V S S _ S RC C P U _0 # C2 1 4 C 2 04
V S S _ CP U C L K _P W R GD
26 25 V D D_ I / O c a n b e
33 V S S _ RE F C K P W R GD / P D # 0 . 1 u_ 1 0V _ X 7 R _ 04 1 u _ 6. 3 V _ X 5R _0 4
GN D r a ng i n g f r om
S L G8 S P 5 85 3 .3 VS
1 . 05 V to 3 .3 V
I C S 9 L RS 3 1 97
R 14 5
R e al t e k R T M8 7 5 N6 3 2 -V B 0 . 1 uF n ea r th e ev e r y p o we r pi n
1 0 K _0 4
D
Q 12 R 14 2
G
SMBus 36 CL K E N#
M T N 7 00 2 Z H S 3 1 M_ 0 4
S
Q1 1 A
MT D N 7 00 2 Z H S 6 R EMI
2
D
C L K _S C L K
15 S MB _ C L K C L K _S C L K 10 , 1 1
6
3 .3 V S
G
X1 F S X8 L _ 14 . 3 1 81 8 MH z
5 VS
1 4 R N1 5 X IN 2 1 X OU T
2 3 2 . 2 K _ 4P 2 R _0 4 R E F _ 0 / C P U _S E L C2 0 2 * 1 0p _ 50 V _ N P O _0 6
G
C 2 07 C 20 8
3
C L K _S D A T A
15 S MB _ D A T A C L K _S D A T A 1 0, 1 1
3 3 p _5 0 V _ N P O_ 0 4 3 3 p_ 5 0 V _N P O_ 0 4 E M I C a p ac t i or
D
S
5
Q1 1 B
MT D N 7 00 2 Z H S 6 R
CPU_SEL_During CK_PEWGD Latch Pinl
3 .3 VS
PI N _ 30 C PU _ 0 C P U_ 1
R1 3 2 * 4. 7 K _ 0 4 R E F _ 0/ C P U _ S E L
0 ( de f a ul t ) 1 33 M H z 1 3 3M H z
R1 3 3 1 0 K _0 4
1 ( 0. 7 V -1 . 5 V) 1 00 M H z 1 0 0M H z 5 VS 13 , 1 7 , 20 , 2 1 , 26 , 2 7, 3 0 , 3 1, 3 5 , 3 6
3 .3 V 3, 4 , 1 2 , 14 , 1 5 , 16 , 1 8, 19 , 2 0, 2 1 , 2 3, 2 4 , 2 5, 2 9 , 3 0, 3 1 , 33 , 3 4 , 35
3 .3 VS 10 , 1 1 , 12 , 1 3 , 14 , 1 5, 1 6 , 1 7, 1 8 , 1 9, 2 0 , 2 1, 2 3 , 2 4, 2 5 , 26 , 2 7 , 28 , 2 9 , 30 , 3 1 , 35 , 3 6
1 . 1 V S _V TT 4 , 6, 7, 1 4 , 15 , 1 6 , 19 , 2 0 , 21 , 3 4 , 35 , 3 6
Clock Generator B - 3
Schematic Diagrams
Processor 1/7
PROCESSOR 1/7 ( DMI,PEG,FDI )
U 16 A
B2 6
20 mil P E G _I R C OM P _R R 2 06 4 9 . 9 _ 1% _ 0 4
P E G_ I C OM P I A2 6
P E G_ I C O MP O
A2 4 B2 7
16 D MI _ T X N 0 C 23 DM I_ RX # [0 ] P E G _R C O MP O A2 5 EX P _ RBIA S R 2 05 7 5 0 _1 % _ 0 4
16 D MI _ T X N 1 DM I_ RX # [1 ] P E G_ R B I A S
B2 2
16 D MI _ T X N 2 A2 1 DM I_ RX # [2 ] K3 5
16 D MI _ T X N 3 DM I_ RX # [3 ] P E G_ R X# [ 0 ] J34
P E G_ R X# [ 1 ]
B2 4 J33
16 D MI _ T X P 0 D 23 DM I_ RX [0 ] P E G_ R X# [ 2 ] G 35
16 D MI _ T X P 1 DM I_ RX [1 ] P E G_ R X# [ 3 ]
DMI
B2 3 G 32
16 D MI _ T X P 2 A2 2 DM I_ RX [2 ] P E G_ R X# [ 4 ] F3 4
16 D MI _ T X P 3 DM I_ RX [3 ] P E G_ R X# [ 5 ]
F3 1
D 24 P E G_ R X# [ 6 ] D 35
16 D MI _ R X N 0 DM I _ TX # [ 0 ] P E G_ R X# [ 7 ]
G 24 E3 3
16 D MI _ R X N 1 DM I _ TX # [ 1 ] P E G_ R X# [ 8 ]
16 D MI _ R X N 2 F23 C 33
H 23 DM I _ TX # [ 2 ] P E G_ R X# [ 9 ] D 32
16 D MI _ R X N 3 DM I _ TX # [ 3 ] P E G_ R X #[ 1 0 ]
B3 2
D 25 P E G_ R X #[ 1 1 ] C 31
16 D MI _ R X P 0 DM I _ TX [ 0 ] P E G_ R X #[ 1 2 ]
F24 B2 8
16 D MI _ R X P 2 E2 3 B3 0
G 23 DM I _ TX [ 2 ] P E G_ R X #[ 1 4 ] A3 1
J35
P E G_ R X [ 0 ]
H 34
P E G_ R X [ 1 ] H 33
Sheet 3 of 40 16
16
FD
FD
I _ TX N
I _ TX N
0
1
E2 2
D 21
D 19
F DI
F DI
_T X # [ 0 ]
_T X # [ 1 ]
P E G_ R X [ 2 ]
P E G_ R X [ 3 ]
P E G_ R X [ 4 ]
F3 5
G 33
E3 4
16 FD I _ TX N 2 F DI _T X # [ 2 ] P E G_ R X [ 5 ]
Processor 1/7 16
16
16
FD
FD
FD
I _ TX N
I _ TX N
I _ TX N
3
4
5
D 18
G 21
E1 9
F21
F DI
F DI
F DI
_T X # [ 3 ]
_T X # [ 4 ]
_T X # [ 5 ]
P E G_ R X [ 6 ]
P E G_ R X [ 7 ]
P E G_ R X [ 8 ]
F3 2
D 34
F3 3
B3 3
PCI EXPRESS -- GRAPHICS

16 FD I _ TX N 6 F DI _T X # [ 6 ] P E G_ R X [ 9 ]
Intel(R) FDI
G 18 D 31
16 FD I _ TX N 7 F DI _T X # [ 7 ] P E G_ R X[ 1 0 ]
A3 2
P E G_ R X[ 1 1 ] C 30
P E G_ R X[ 1 2 ]
D 22 A2 8
16 FD I _ TX P 0 C 21 F DI _T X [ 0 ] P E G_ R X[ 1 3 ] B2 9
16 FD I _ TX P 1 F DI _T X [ 1 ] P E G_ R X[ 1 4 ]
D 20 A3 0
16 FD I _ TX P 2 C 18 F DI _T X [ 2 ] P E G_ R X[ 1 5 ]
16 FD I _ TX P 3 F DI _T X [ 3 ]
G 22 L33
16 FD I _ TX P 4 F DI _T X [ 4 ] P E G _ T X# [ 0 ]
16 FD I _ TX P 5 E2 0 M 35
F20 F DI _T X [ 5 ] P E G _ T X# [ 1 ] M 33
16 FD I _ TX P 6 F DI _T X [ 6 ] P E G _ T X# [ 2 ]
G 19 M 30
16 FD I _ TX P 7 F DI _T X [ 7 ] P E G _ T X# [ 3 ] L31
It applies to Auburndale and Clarksfield discrete graphic designs. F17 P E G _ T X# [ 4 ] K3 2
16 F D I_ F S Y NC 0 F D I _F S Y N C [ 0 ] P E G _ T X# [ 5 ]
If discrete graphic chip is used for Auburndale, VAXG (GFX core) rail can be connected E1 7 M 29
16 F D I_ F S Y NC 1 F D I _F S Y N C [ 1 ] P E G _ T X# [ 6 ] J31
to GND if motherboard only supports discrete graphics and also in a common P E G _ T X# [ 7 ]
C 17 K2 9
motherboard design if GFX VR is not stuffed. On the other hand, if the VR is stuffed, 16 F D I_ INT F D I _I N T P E G _ T X# [ 8 ] H 30
VAXG can be left floating in a common motherboard design (Gfx VR keeps VAXG from P E G _ T X# [ 9 ]
F18 H 29
floating). 16 F D I_ L S Y N C0 D 17 F D I _L S Y N C [ 0 ] P E G_ T X #[ 1 0 ] F2 9
16 F D I_ L S Y N C1 F D I _L S Y N C [ 1 ] P E G_ T X #[ 1 1 ] E2 8
In addition, FDI_RXN_[7:0] and FDI_RXP_[7:0] can be left floating on the PCH. P E G_ T X #[ 1 2 ]
FDI_TX[7:0] and FDI_TX#[7:0] can be left floating on the Auburndale. D 29
P E G_ T X #[ 1 3 ] D 27
The GFX_IMON, FDI_FSYNC[0], FDI_FSYNC[1], FDI_LSYNC[0], FDI_LSYNC[1], and P E G_ T X #[ 1 4 ]
C 26
FDI_INT signals should be tied to GND (through 1K ? % resistors) in the common P E G_ T X #[ 1 5 ]
motherboard design case. Please not that if these signals are left floating, there are no L34
P E G _ TX [ 0 ] M 34
functional impacts but a small amount of power (~15 mW) maybe wasted. VAXG_SENSE
P E G _ TX [ 1 ] M 32
and VSSAXG_SENSE on Auburndale can be left as no connect. P E G _ TX [ 2 ]
L30
DPLL_REF_SSCLK and DPLL_REF_SSCLK# can be connected to GND on Auburndale P E G _ TX [ 3 ] M 31
directly if motherboard only supports discrete graphics. In a common motherboard P E G _ TX [ 4 ]
K3 1
design, these pins are driven via PCH (even if Graphics is disabled by BIOS) thus no P E G _ TX [ 5 ] M 28
P E G _ TX [ 6 ] H 31
external termination is required. P E G _ TX [ 7 ]
K2 8
P E G _ TX [ 8 ] G 30
P E G _ TX [ 9 ]
G 29
P E G _ T X[ 1 0 ] F2 8
P E G _ T X[ 1 1 ]
E2 7
On Board DDR3 Thermal Sensor P E G _ T X[ 1 2 ] D 28
P E G _ T X[ 1 3 ] C 27
P E G _ T X[ 1 4 ]
C 25
P E G _ T X[ 1 5 ]
P Z 9 8 9 27 -3 6 4 1- 01 F
3 .3 V
Analog Thermal Sensor

C 36 4 R2 2 5 *1 0 m i _l s h ort 3 . 3V
C R I T _T E M P _ R E P # 1 9
Q 16
* 0. 1 u _ 1 0V _X 5 R _ 0 4 2 1 1:2 (4mils:8mils)
VC C OU T T H E R M _V OL T 2 8
U 18 D1 5 * RB7 5 1 V T H E R M_ A L E R T# 2 8 4, 1 2 , 1 4 , 15 , 1 6 , 1 8 , 19 , 2 0 , 2 1, 23 , 2 4 , 2 5, 29 , 3 0 , 3 1, 3 3 , 3 4 , 3 5 3 . 3 V
1 4 C A P M_ E X T T S #_ E C 4 C 3 66 3 C3 6 7
VDD T H ERM GN D
2 6
C
D+ A LE R T 0 . 1 u _ 10 V _ X 7 R _ 0 4 0 . 1u _ 1 0 V _ X7 R _0 4
G7 1 1 S T 9U
B 1
Q 10 3
*2 N 3 9 0 4 3 7
D- SD ATA S MD _ C P U _T H E R M 1 5 , 28
E
5 8
GN D SC L K S MC _ C P U _T H E R M 1 5 , 28
2
*W 83 L 7 7 1A W G PLACE NEAR U3
B - 4 Processor 1/7
Schematic Diagrams
Processor 2/7
PROCESSOR 2/7 ( CLK,MISC,JTAG ) 1 .5 V
Processor Compensation
R 20 0
Signals * 1K _0 4
R2 3 6 4 9 . 9 _ 1% _ 0 4 H _C OM P 0 R 2 01 0_04
R2 1 2 4 9 . 9 _ 1% _ 0 4 H _C OM P 1 DDR3 Compensation Signals BSS138 ( VGS 1.5V )
S M _R C O MP _ 0 R2 2 6 1 0 0 _ 1% _ 0 4 Q 15
* R J U 00 3 N 0 3 T 1 06
S M _R C O MP _ 1 R2 2 7 2 4 . 9 _ 1% _ 0 4 S M _D R A M R S T# S D
D D R 3 _ D R A MR S T # 1 0, 1 1
R2 3 4 2 0 _ 1 %_ 0 4 H _C OM P 2
S M _R C O MP _ 2 R2 2 8 1 3 0 _ 1% _ 0 4
R2 3 3 2 0 _ 1 %_ 0 4 H _C OM P 3 R 2 02
G
* 10 0 K _ 0 4
D R A MR S T _C T R L 9 , 1 9
TRACE WIDTH 10MIL, LENGTH <500MILS
C3 1 8 ? ? IBEX CONTROL
*4 7 n_ 5 0 V _ 04
U 16 B
H _ C O MP 3 AT2 3
C O MP 3 A1 6
H _ C O MP 2 B CL K B C L K _C P U _P 19
MISC
AT2 4 B1 6
Processor Pullups C O MP 2 B CL K # B C L K _C P U _N 19
H _ C O MP 1 G1 6 AR 3 0
C O MP 1 B CL K _ IT P AT3 0
Sheet 4 of 40
CLOCKS
1 .1 V S _ V T T H _ C O MP 0 AT2 6 B C LK _I T P #
C O MP 0
E1 6 C LK _E X P _ P 1 5
P E G _ CL K D 16
P E G_ C L K # C LK _E X P _ N 1 5
R2 1 6 4 9 . 9 _ 1% _ 0 4 H _C A T E R R # A H2 4
R2 3 7 68_04 H _P R OC H O T #_ D
H _ C A TE R R # AK1 4
S K T OC C #
D P LL _ R E F _S S C L K
D P L L_ R E F _ S S C L K #
A1 8
A1 7
C LK _D P _ P 1 5
C LK _D P _ N 1 5
Processor 2/7
H _C P U R S T # C A TE R R #
THERMAL
R2 4 5 * 6 8_ 0 4
F6 S M_ D R A M R S T #
AT1 5 S M_ D R A M R S T # 1 .1 V S _ V T T
1 9 ,2 8 H _ P E CI PEC I AL 1 S M_ R C O MP _ 0
S M_ R C O MP [ 0 ] S M_ R C O MP _ 1
AM 1 R 2 30 1 0 K _ 04
S M_ R C O MP [ 1 ] AN 1 S M_ R C O MP _ 2 R 54 1 0 K _ 04
H _ P R OC H O T# _ D S M_ R C O MP [ 2 ]
R2 4 6 0 _0 4 A N2 6
DDR3
MISC
3 6 H _ P R OC H O T # P R OC H OT # AN 1 5 P M_ E X T T S #[ 0] R 53 * 0_ 0 4
P M_ E X T _T S # [ 0 ] P M_ E X T T S #[ 1] P M_ E X T T S # _E C 3
If PROCHOT# is not used, then it must be terminated A P 15 R 2 29 * 0_ 0 4
P M_ E X T _T S # [ 1 ] T S #_ D I MM 0 _1 1 0 , 1 1
with a 50-O pull-up resistor to VTT_1.1 rail.
1 9 H _ TH R M T R I P # AK1 5 R 2 31 * 12 . 4 K _ 1 % _0 4
T H E R MT R I P #
AT2 8
P RD Y # A P 27 XD P _ P R E Q#
P R E Q#
AN 2 8 XD P _ T C L K
H _ C P U R S T# TC K XD P _ T MS
AP2 6 A P 28
R E S E T _O B S # TM S
PWR MANAGEMENT
AT2 7 XD P _ T R S T #
T RS T #
AL 1 5 AT2 9 XD P _ T DI_ R
1 6 H _ P M_ S Y N C
JTAG & BPM

P M _S Y N C TD I AR 2 7 XD P _ T D O _R
TD O XD P _ T DI_ M 1 .1 V S _ V T T
AR 2 9
R 24 7 *0 _ 0 4 S Y S _ A G E N T _ P W R OK A N 1 4 T D I_ M A P 29 XD P _ T D O _M
1 6 , 3 6 D E L A Y _ P W R GD V C C P W R GO OD _ 1 T DO _ M X DP _T M S R 2 50 * 51 _ 0 4
R 24 8 * 1 0m i l _s h o rt AN 2 5 X DP _T D O_ M R 2 42 5 1 _ 04
D B R# X DP _T D I _R
1 9 H _ C P U P W R GD A N2 7 R 2 49 * 51 _ 0 4
V C C P W R GO OD _ 0 X DP _P R E Q # R 2 40 * 51 _ 0 4
AJ 2 2 X DP _T D O_ R R 2 39 * 51 _ 0 4
R 52 * 1 0m i l _s h o rt V D D P W R GO OD _R AK1 3 B P M# [ 0 ] A K 22
1 6 P M _ D R A M_ P W R GD S M _D R A M P W R OK B P M# [ 1 ] A K 24
B P M# [ 2 ]
AJ 2 4
A M1 5 B P M# [ 3 ] AJ 2 5
1 6 H _ V T TP W R G D V T T P W R G OO D B P M# [ 4 ]
AH 2 2
Connect to the Processor (VTTPWRGOOD) VTT_1.1 VR power B P M# [ 5 ] A K 23 X D P _T C LK R 2 43 * 51 _ 0 4
good signal to processor. Signal voltage level is 1.1 V. H _ P W R GD _ XD P B P M# [ 6 ] X D P _T R S T #
A M2 6 AH 2 3 R 2 38 5 1 _ 04
T A P P W R GO OD B P M# [ 7 ]
R 60 1 . 5 K _ 1% _ 0 4 P L T_ R S T #_ R AL 1 4
1 8 , 2 3, 2 5 , 2 8 B U F _P L T _ R S T # R S TI N #
Signal from PCH to Processor
Connect to PCH (PLT_RST#)
R6 1
(needs to be level translated
from 3.3 V to 1.1 V). 7 50 _ 1 % _0 4 P Z 9 8 9 2 7-3 6 4 1- 01 F
X D P _T D O_ M R 2 41 *1 0 mi l _ sh o rt XD P _ T D I _ M
1 .5 V S _ CP U
3 .3 V
R 50
1 . 1 K _ 1% _ 0 4 R2 3 2 * 8 . 2K _ 0 4
3 .3 V 3, 12 , 1 4 , 1 5, 1 6 , 1 8 , 19 , 2 0 , 2 1, 2 3 , 2 4 , 25 , 2 9 , 3 0, 31 , 3 3 , 3 4, 3 5
V D D P W R G OO D _ R
1 .5 V 9, 10 , 1 1 , 2 1, 2 3 , 2 7 , 29 , 3 1 , 3 3, 3 6
5
U1 7 1 .5 V S _ C P U 7 ,3 1
1 IN3 .3 V
1 . 1 V S _ V T T 2 , 6 , 7, 1 4 , 1 5 , 16 , 1 9 , 2 0, 21 , 3 4 , 3 5, 3 6
R 62 R2 4 4 * 1 . 5K _ 1 % _ 04 D R A MP W R G D _ C P U 4
2 1 . 1 V S _ V T T _P W R G D 1 6 , 3 3, 3 4
3 K _ 1% _ 0 4
*M C 7 4 V H C 1 G0 8 D F T 1 G
3
Intel change
4.75K -->1.1K
12K -->3K
Processor 2/7 B - 5
Schematic Diagrams
Processor 3/7
PROCESSOR 3/7 ( DDR3 )
U16C
U16D
AA6
SA_CK[0] M_CLK_DDR0 10
AA7 W8
10 M_A_DQ[63:0] SA_CK#[0] M_CLK_DDR#0 10 11 M_B_DQ[ 63:0] SB_CK[0] M_CLK_DDR2 11
P7 W9
M_A_DQ0 SA_CKE[0] M_CKE0 10 M_B_DQ0 SB_CK#[0] M_CLK_DDR#2 11
A10 B5 M3 M_CKE2 11
M_A_DQ1 SA_DQ[0] M_B_DQ1 SB_DQ[0] SB_CKE[0]
C10 A5
M_A_DQ2 SA_DQ[1] M_B_DQ2 SB_DQ[1]
C7 C3
M_A_DQ3 A7 SA_DQ[2] Y6 M_B_DQ3 B3 SB_DQ[2] V7
SA_DQ[3] SA_CK[1] M_CLK_DDR1 10 SB_DQ[3] SB_CK[1] M_CLK_DDR3 11
M_A_DQ4 B10 Y5 M_B_DQ4 E4 V6
SA_DQ[4] SA_CK#[1] M_CLK_DDR#1 10 SB_DQ[4] SB_CK#[1] M_CLK_DDR#3 11
M_A_DQ5 D10 P6 M_B_DQ5 A6 M2
SA_DQ[5] SA_CKE[1] M_CKE1 10 SB_DQ[5] SB_CKE[1] M_CKE3 11
M_A_DQ6 E10 M_B_DQ6 A4
SA_DQ[6] SB_DQ[6]
M_A_DQ7 A8 M_B_DQ7 C4
D8 D1
F10 AE2 M_CS#0 10 D2
M_A_DQ10 SA_DQ[9] SA_CS#[0] M_B_DQ10 SB_DQ[9]
E6 AE8 M_CS#1 10 F2 AB8 M_CS#2 11
M_A_DQ11 F7 SA_DQ[10] SA_CS#[1] M_B_DQ11 F1 SB_DQ[10] SB_CS#[0] AD6
M_CS#3 11
M_A_DQ12 E9 SA_DQ[11] M_B_DQ12 C2 SB_DQ[11] SB_CS#[1]

M_A_DQ13 B7 SA_DQ[12] M_B_DQ13 F5 SB_DQ[12]
SA_DQ[13] SB_DQ[13]
M_A_DQ14 E7 AD8 M_B_DQ14 F3
SA_DQ[14] SA_ODT[0] M_ODT0 1
0 SB_DQ[14]
M_A_DQ15 C6 AF9 M_ODT1 1
0 M_B_DQ15 G 4 AC7 M_ODT2 11
M_A_DQ16 SA_DQ[15] SA_ODT[1] M_B_DQ16 SB_DQ[15] SB_ODT[0]
H10 H6 AD1 M_ODT3 11
M_A_DQ17 SA_DQ[16] M_B_DQ17 SB_DQ[16] SB_ODT[1]
G8 G 2
K7 J6
M_A_DQ19 J8 SA_DQ[18] M_B_DQ19 J3 SB_DQ[18]
Sheet 5 of 40 M_A_DQ20
M_A_DQ21
M_A_DQ22
G7
G10
J7
SA_DQ
SA_DQ
SA_DQ
SA_DQ
[19]
[20]
[21]
[22] SA_DM[0]
B9 M_A_
DM0
M_A_DM[7: 0
] 10
M_B_DQ
M_B_DQ
M_B_DQ
20
21
22
G
G
1
5
J2
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DM[0]
SB_DM[1]
D4
E1
M_B_DM0
M_B_DM1
M_B_DM[7:0] 11
M_A_DQ23 M_A_
DM1 M_B_DQ23 M_B_DM2
Processor 3/7
J10 D7 J1 H3
M_A_DQ24 SA_DQ[23] SA_DM[1] M_A_
DM2 M_B_DQ24 SB_DQ[23] SB_DM[2] M_B_DM3
L7 H7 J5 K1
M6 M7 K2 AH1
M8 AG6 L3 AL2
M_A_DQ27 L9 SA_DQ[26] SA_DM[4] AM7 M_A_
DM5 M_B_DQ27 M 1 SB_DQ[26] SB_DM[5] AR4 M_B_DM6
M_A_DQ28 L6 SA_DQ[27] SA_DM[5] AN10 M_A_
DM6 M_B_DQ28 K5 SB_DQ[27] SB_DM[6] AT8 M_B_DM7
M_A_DQ29 K8 SA_DQ[28] SA_DM[6] AN13 M_A_
DM7 M_B_DQ29 K4 SB_DQ[28] SB_DM[7]
SA_DQ[29] SA_DM[7] SB_DQ[29]
M_A_DQ30 N8 M_B_DQ30 M 4
P9 N5
AH5 AF3
AF5 AG 1
M_A_DQ34 AK6 SA_DQ[33] C9 M_A_
DQS#0 M_A_DQS#
[ 7:0] 10 M_B_DQ34 AJ3 SB_DQ[33] D5 M_B_DQS#0 M_B_
DQS#[7:0] 11
M_A_DQ35 AK7 SA_DQ[34] SA_DQS#[0] F8 M_A_
DQS#1 M_B_DQ35 AK1 SB_DQ[34] SB_DQS#[0] F4 M_B_DQS#1
DDR SY STEM MEM ORY A

M_A_DQ36 AF6 SA_DQ[35] SA_DQS#[1] J9 M_A_
DQS#2 M_B_DQ36 AG 4 SB_DQ[35] SB_DQS#[1] J4 M_B_DQS#2
M_A_DQ37 AG5 SA_DQ[36] SA_DQS#[2] N9 M_A_
DQS#3 M_B_DQ37 AG 3 SB_DQ[36] SB_DQS#[2] L4 M_B_DQS#3
SA_DQ[37] SA_DQS#[3] SB_DQ[37] SB_DQS#[3]
M_A_DQ38 AJ7 AH7 M_A_
DQS#4 M_B_DQ38 AJ4 AH2 M_B_DQS#4
M_A_DQ39 SA_DQ[38] SA_DQS#[4] M_A_
DQS#5 M_B_DQ39 SB_DQ[38] SB_DQS#[4] M_B_DQS#5
AJ6 AK9 AH4 AL4
SA_DQ[39] SA_DQS#[5] SB_DQ[39] SB_DQS#[5]
DDR SYS TEM MEMO RY - B

M_A_DQ40 AJ10 AP11 M_A_
DQS#6 M_B_DQ40 AK3 AR5 M_B_DQS#6
M_A_DQ41 SA_DQ[40] SA_DQS#[6] M_A_
DQS#7 M_B_DQ41 SB_DQ[40] SB_DQS#[6] M_B_DQS#7
AJ9 AT13 AK4 AR8
M_A_DQ42 AL10 SA_DQ[41] SA_DQS#[7] M_B_DQ42 AM 6 SB_DQ[41] SB_DQS#[7]
M_A_DQ43 AK12 SA_DQ[42] M_B_DQ43 AN2 SB_DQ[42]
M_A_DQ44 AK8 SA_DQ[43] M_B_DQ44 AK5 SB_DQ[43]
M_A_DQ45 AL7 SA_DQ[44] M_B_DQ45 AK2 SB_DQ[44]
SA_DQ[45] M_A_DQS[7:0] 10 SB_DQ[45]
M_A_DQ46 AK11 C8 M_A_
DQS0 M_B_DQ46 AM 4
M_A_DQ47 SA_DQ[46] SA_
DQS[0] M_A_
DQS1 M_B_DQ47 SB_DQ[46]
AL8 F9 AM 3
DQS[1] M_A_
DQS2 M_B_DQ48 SB_DQ[47] M_B_DQS0 M_B_
DQS[7:0] 11
AN8 H9 AP3 C5
DQS[2] M_A_
DQS3 M_B_DQ49 SB_DQ[48] SB_DQS[0] M_B_DQS1
AM10 M9 AN5 E3
M_A_DQ50 AR11 SA_DQ[49] SA_
DQS[3] AH8 M_A_
DQS4 M_B_DQ50 AT 4 SB_DQ[49] SB_DQS[1] H4 M_B_DQS2
M_A_DQ51 AL11 SA_DQ[50] SA_
DQS[4] AK10 M_A_
DQS5 M_B_DQ51 AN6 SB_DQ[50] SB_DQS[2] M5 M_B_DQS3
M_A_DQ52 AM9 SA_DQ[51] SA_
DQS[5] AN11 M_A_
DQS6 M_B_DQ52 AN4 SB_DQ[51] SB_DQS[3] AG2 M_B_DQS4
M_A_DQ53 AN9 SA_DQ[52] SA_
DQS[6] AR13 M_A_
DQS7 M_B_DQ53 AN3 SB_DQ[52] SB_DQS[4] AL5 M_B_DQS5
SA_DQ[53] SA_
DQS[7] SB_DQ[53] SB_DQS[5]
M_A_DQ54 AT11 M_B_DQ54 AT 5 AP5 M_B_DQS6
M_A_DQ55 SA_DQ[54] M_B_DQ55 SB_DQ[54] SB_DQS[6] M_B_DQS7
AP12 AT 6 AR7
M_A_DQ56 SA_DQ[55] M_B_DQ56 SB_DQ[55] SB_DQS[7]
AM12 AN7
AN12 M_A_A[15:0] 10 AP6
M_A_DQ58 AM13 SA_DQ[57] Y3 M_A_
A0 M_B_DQ58 AP8 SB_DQ[57]
M_A_DQ59 AT14 SA_DQ[58] SA_MA[0] W1 M_A_
A1 M_B_DQ59 AT 9 SB_DQ[58]
M_A_DQ60 AT12 SA_DQ[59] SA_MA[1] AA8 M_A_
A2 M_B_DQ60 AT 7 SB_DQ[59]
SA_DQ[60] SA_MA[2] SB_DQ[60]
M_A_DQ61 AL13 AA3 M_A_
A3 M_B_DQ61 AP9
SA_DQ[61] SA_MA[3] SB_DQ[61]
M_A_DQ62 AR14 V1 M_A_
A4 M_B_DQ62 AR1 0 M_B_A[15:0] 1
1
M_A_DQ63 SA_DQ[62] SA_MA[4] M_A_
A5 M_B_DQ63 SB_DQ[62] M_B_A0
AP14 AA9 AT1 0 U5
SA_DQ[63] SA_MA[5] M_A_
A6 SB_DQ[63] SB_MA[0] M_B_A1
V8 V2
SA_MA[6] M_A_
A7 SB_MA[1] M_B_A2
T1 T5
SA_MA[7] Y9 M_A_
A8 SB_MA[2] V3 M_B_A3
AC3 SA_MA[8] U6 M_A_
A9 SB_MA[3] R1 M_B_A4
10 M_A_BS0 SA_BS[0] SA_MA[9] SB_MA[4]
AB2 AD4 M_A_
A10 AB1 T8 M_B_A5
10 M_A_BS1 SA_BS[1] SA_MA[10] 11 M_B_BS0 SB_BS[0] SB_MA[5]
U7 T2 M_A_
A11 W5 R2 M_B_A6
10 M_A_BS2 SA_BS[2] SA_MA[11] M_A_
A12 11 M_B_BS1 SB_BS[1] SB_MA[6] M_B_A7
U3 11 M_B_BS2 R7 R6
SA_MA[12] M_A_
A13 SB_BS[2] SB_MA[7] M_B_A8
AG8 R4
SA_MA[13] M_A_
A14 SB_MA[8] M_B_A9
T3 R5
AE1 SA_MA[14] V9 M_A_
A15 AC5 SB_MA[9] AB5 M_B_A10
10 M_A_CAS# SA_CAS# SA_MA[15] 11 M_B_CAS# SB_CAS# SB_MA[10]
AB3 Y7 P3 M_B_A11
10 M_A_RAS# SA_RAS# 11 M_B_RAS# SB_RAS# SB_MA[11]
AE9 AC6 R3 M_B_A12
10 M_A_WE# SA_WE# 11 M_B_WE# SB_WE# SB_MA[12] AF7 M_B_A13
SB_MA[13]
P5 M_B_A14
SB_MA[14] M_B_A15
N1
SB_MA[15]
PZ98927-3641-01F
PZ9892
7- 36
41-01F
B - 6 Processor 3/7
Schematic Diagrams
Processor 4/7
PROCESSOR 4/7 ( POWER )

U1 6 F
P ROCESSOR CORE POWE R PROCE SSOR UNCO RE POWER

VCO R E 1 .1 V S _ V T T
48A VTT T OTAL 21A
A G3 5 AH 1 4
V CC 1 VTT0 _ 1
I C CM AX Ma xi m um Pr oc e ss or S V 48 A G3 4 AH 1 2
V CC 2 VTT0 _ 2
A G3 3 AH 1 1 C 28 C2 9 C 331 C 34 C 32 C3 0 8 C 341
A G3 2 V CC 3 VTT0 _ 3 AH 1 0
A G3 1 V CC 4 VTT0 _ 4 J14 1 0 u _ 6. 3V _ X5 R _ 0 6 *1 0 u _ 6 . 3 V _ X 5R _ 0 6 1 0 u _ 6 .3 V_ X 5 R_ 0 6 * 10 u _ 6 . 3 V _ X 5 R _ 0 6 * 1 0 u _6 . 3 V _X 5 R _ 06 2 2 u_ 6 . 3 V _ X 5 R _ 08 2 2 u _ 6 . 3 V _ X 5R _ 0 8
V CO R E V CC 5 VTT0 _ 5
A G3 0 J13
V CC 6 VTT0 _ 6
A G2 9 H 14
C3 3 0 C3 3 8 C3 4 2 C3 4 4 A G2 8 V CC 7 VTT0 _ 7 H 12
A G2 7 V CC 8 VTT0 _ 8 G 14
V CC 9 VTT0 _ 9
2 2u _ 6 . 3 V _ X 5 R _ 0 8
2 2u _ 6 . 3 V _ X 5 R _ 0 8
A G2 6 G 13
*2 2 u _ 6. 3V _ X 5 R _ 0 8
22 u _ 6 . 3 V _ X 5 R _ 08
V CC 10 VT T 0 _ 1 0
AF3 5 G 12
AF3 4 V CC 11 VT T 0 _ 1 1 G 11
AF3 3 V CC 12 VT T 0 _ 1 2 F14 C 36 C3 1 0 C 33 C 335
V CC 13 VT T 0 _ 1 3
ICCMAX_VTT Max Current
AF3 2 F13
V CC 14 VT T 0 _ 1 4 for VTT Rail
AF3 1 F12 1 0 u _ 6. 3V _ X5 R _ 0 6 10 u _ 6 . 3 V _ X 5 R _ 0 6 1 0 u _6 . 3 V _ X 5 R _ 06 * 1 0 u_ 6 . 3 V _ X 5 R _0 6
AF3 0 V CC 15 VT T 0 _ 1 5 F11
V CC 16 VT T 0 _ 1 6
SV 18
AF2 9 E1 4
V CC 17 VT T 0 _ 1 7
AF2 8 E1 2
V CC 18 VT T 0 _ 1 8
AF2 7 D 14
AF2 6 V CC 19 VT T 0 _ 1 9 D 13
V CC 20 VT T 0 _ 2 0
A D3 5 D 12
V CC 21 VT T 0 _ 2 1
1.1V RAIL POWER

C3 4 9 C3 5 9 C3 3 6 C3 2 5 A D3 4 D 11
A D3 3
A D3 2
V
V
CC
CC
22
23
VT T 0 _ 2 2
VT T 0 _ 2 3
C 14
C 13 Sheet 6 of 40
*2 2 u _ 6 . 3 V _ X 5 R _ 0 8
2 2u _ 6 . 3 V _ X 5 R _ 0 8
*2 2 u _ 6. 3V _ X 5 R _ 0 8
22 u _ 6 . 3 V _ X 5 R _ 08
V CC 24 VT T 0 _ 2 4
A D3 1 C 12
V CC 25 VT T 0 _ 2 5
A D3 0 C 11 The decoupling capacitors, filter
Processor 4/7
A D2 9 V CC 26 VT T 0 _ 2 6 B1 4
A D2 8 V CC 27 VT T 0 _ 2 7 B1 2 recommendations and sense resistors on the
V CC 28 VT T 0 _ 2 8
A D2 7 A1 4
A D2 6
V CC 29 VT T 0 _ 2 9
A1 3
CPU/PCH Rails are specific to the CRB
A C3 5 V CC 30 VT T 0 _ 3 0 A1 2
V CC 31 VT T 0 _ 3 1
Implementation. Customers need to follow the
A C3 4 A1 1
V CC 32 VT T 0 _ 3 2 recommendations in the Calpella Platform
A C3 3
V CC 33 1 .1 VS _ V T T
A C3 2 Design Guide
A C3 1 V CC 34
C3 3 9 C3 6 3 C3 6 2 C3 6 1 A C3 0 V CC 35 A F 10
V CC 36 VT T 0 _ 3 3
A C2 9 A E 10
V CC 37 VT T 0 _ 3 4
2 2u _ 6 . 3 V _ X 5 R _ 0 8
2 2u _ 6 . 3 V _ X 5 R _ 0 8
*2 2 u _ 6. 3V _ X 5 R _ 0 8
*2 2 u _ 6. 3V _ X 5 R _ 0 8
A C2 8 AC 1 0 C 311 C3 1 2 C 319
V CC 38 VT T 0 _ 3 5
CPU CORE SUPPLY

A C2 7 A B 10
A C2 6 V CC 39 VT T 0 _ 3 6 Y 10 2 2 u _ 6 .3 V _ X 5 R_ 0 8 2 2u _ 6 . 3 V _ X 5 R _0 8 2 2 u _ 6 . 3 V _ X 5R _ 0 8
V CC 40 VT T 0 _ 3 7
AA3 5 W 10
AA3 4 V CC 41 VT T 0 _ 3 8 U 10
AA3 3 V
V
CC
CC
42
43
VT T 0 _ 3 9
VT T 0 _ 4 0
T10 1.1VS_VTT
AA3 2 J12
V CC 44 VT T 0 _ 4 1
AA3 1 J11 Please note that the
AA3 0 V CC 45 VT T 0 _ 4 2 J16 + V T T _4 3 R 209 *1 0 m i _l s h o rt _ 0 4
AA2 9 V CC 46 VT T 0 _ 4 3 J15 + V T T _4 4 R 211 *1 0 m i _l s h o rt _ 0 4 VTT Rail Values are
V CC 47 VT T 0 _ 4 4
AA2 8
V CC 48
AA2 7
AA2 6 V CC 49
V CC 50
Auburndale VTT=1.05V
Y3 5
V CC 51
Y3 4
V CC 52 1 . 1 V S _ V TT
Y3 3
V CO R E Y3 2 V CC 53
Y3 1 V CC 54 1K PU t o V TT an d 1 K P D t o GN D
V CC 55
Y3 0
V CC 56 fo r P OC
C3 5 5 C3 5 3 C3 5 2 C3 5 1 Y2 9 R 222
Y2 8 V CC 57
V CC 58
10 u _ 6 . 3 V _ X 5 R _ 0 6
Y2 7 VCORE * 1 K_ 0 4
*1 0 u _ 6 . 3 V _ X 5 R _ 0 6
*1 0 u _ 6. 3V _ X 5 R _ 0 6
10 u _ 6 . 3 V _ X 5 R _ 06
V CC 59
Y2 6
V3 5 V CC 60 AN 3 3 PSI #
V CC 61 P S I# P S I# 36
V3 4
V CC 62 1 .1 V S_ V T T
V3 3
V CC 63
V3 2 A K 35 R 223
POWER
V3 1 V CC 64 V ID [0 ] A K 33 H _V ID0 36
V CC 65 V ID [1 ] H _V ID1 36
V3 0 A K 34 1 K _0 4
V CC 66 V ID [2 ] H _V ID2 36
V2 9 AL 3 5 R 220
V CC 67 V ID [3 ] H _V ID3 36
V2 8 AL 3 3
CPU VIDS
V2 7 V CC 68 V ID [4 ] AM 3 3 H _V ID4 36 1 K_ 0 4
V CC 69 V ID [5 ] H _V ID5 36
V2 6 AM 3 5
V CC 70 V ID [6 ] H _V ID6 36
C3 3 3 C3 3 2 C3 3 4 C3 5 4 U3 5 AM 3 4 P M _D P R S L P V R 36
V CC 71 P R OC _ D P R S L P V R
U3 4
U3 3 V CC 72
1 0u _ 6 . 3 V _ X 5 R _ 0 6
*1 0 u _ 6. 3V _ X 5 R _ 0 6
*1 0 u _ 6. 3V _ X 5 R _ 0 6
10 u _ 6 . 3 V _ X 5 R _ 06
U3 2 V CC 73 R 219
V CC 74 H _V T TV I D 1
U3 1 G 15
V CC 75 VT T _ SEL EC T
U3 0 * 1 K_ 0 4
U2 9 V CC 76
U2 8 V CC 77
V CC 78
U2 7
V CC 79
U2 6
R3 5 V CC 80
V CC 81
R3 4 TO VCORE POWER CONTROL
V CC 82
R3 3
R3 2 V CC 83 AN 3 5
V CC 84 IS E NS E IM O N 36
C3 4 7 C3 4 6 C3 4 5 C3 4 0 R3 1
V CC 85
R3 0
0. 01 u _ 5 0 V _ X 7 R _ 04
V CC 86
0 . 1 u_ 1 0 V _ X 7 R _ 0 4
1 0u _ 6 . 3 V _ X 5 R _ 0 6
R2 9
10 u _ 6 . 3 V _ X 5 R _ 06
R2 8 V CC 87 AJ 3 4
V CC 88 V C C_ S E NS E VC C _ SEN SE 3 6
SENSE LINES
R2 7 AJ 3 5
V CC 89 V S S _ S E NS E V S S _ S E N S E 36
R2 6
V CC 90
P3 5
P3 4 V CC 91 B1 5
V CC 92 V T T _ S E NS E V T T _ S E NSE 34
P3 3 A1 5
V CC 93 V S S _ S E NS E _ V T T
P3 2
V CC 94
P3 1
P3 0 V CC 95
P2 9 V CC 96
V CC 97 V CO RE 36
P2 8 1 . 1 V S _ V T T 2 , 4 , 7 , 1 4, 15 , 1 6 , 1 9 , 2 0 , 2 1 , 3 4 , 3 5, 36
V CC 98
P2 7
P2 6 V CC 99
V CC 100
P Z 9 8 9 2 7- 36 4 1 -0 1 F
Processor 4/7 B - 7
Schematic Diagrams
Processor 5/7
PROCESSOR 5/7 ( GRAPHICS POWER )
V G F X _ CO R E U1 6 G
A T 21
A T 19 VAXG 1 A R 22
VAXG 2 VAXG _ SEN SE G P U V C C S E N S E 35
C3 7 3 C 356 A T 18 AT 2 2 G P UV S S S E NS E 3 5
VAXG 3 VSSAXG _ SEN SE
LINES
SENSE
A T 16
10 u _ 6 . 3 V _ X 5 R _ 0 6 1 0 u _ 6 . 3 V _ X 5R _ 0 6 A R 21 VAXG 4
A R 19 VAXG 5
VAXG 6
A R 18
A R 16 VAXG 7 A M 22
VAXG 8 GF X_ V I D[0 ] D F GT _ V I D _0 35
A P 21 AP2 2
A P 19 A N 22
GRAPHICS VIDs
A P 18 AP2 3 D F GT _ V I D _3 35
C3 5 7 C 369 A P 16 VAXG 11 GF X_ V I D[3 ] A M 23
C 37 1 A N 21 AP2 4
+ VAXG 13 GF X_ V I D[5 ] D F GT _ V I D _5 35
GRAPHICS
22 u _ 6 . 3 V _ X 5 R _ 0 8 2 2 u _ 6 . 3 V _ X 5R _ 0 8 A N 19 A N 24 D F GT _ V I D _6 35
2 2 0 u_ 4 V _ V _ A A N 18 VAXG 14 GF X_ V I D[6 ]
A N 16 VAXG 15
VAXG 16
Sheet 7 of 40 A M 21
A M 19
A M 18
VAXG
VAXG
VAXG
17
18
19
G F X _ V R _E N
G F X _ DP RS L P V R
GF X_ I M O N
A R 25
AT 2 5
A M 24
GF XV R _ D P R S L P V R
T P _ GF X_ I M O N
R2 3 5
R4 5
* 1K _ 04
1 0 0 _ 1% _ 0 4
D F G T _ VR_ EN
G F X _ I M ON 35
35
1 .1 VS _ VT T
A M 16
Processor 5/7 A L 21
A L 19
A L 18
VAXG
VAXG
VAXG
VAXG
20
21
22
23
1 . 5 V S _C P U
A L 16 VDDQ 6A
VAXG 24
A K 21 AJ 1
A K 19 VAXG 25 V D D Q1 AF 1
A K 18 VAXG 26 V D D Q2 AE7 C4 5 C 343 C3 3 7 C 58 C5 1
VAXG 27 V D D Q3
- 1.5V RAILS
A K 16 AE4
A J 21 VAXG 28 V D D Q4 AC 1 1 u _6 . 3 V _ X 5 R _ 04 2 2 u _ 6 . 3 V _ X5 R _ 0 8 2 2u _ 6 . 3 V _ X 5 R _ 0 8 1 0 u _ 6. 3V _X 5 R _ 0 6 10 u _ 6 . 3 V _ X 5 R _ 0 6
Please note that the VAXG 29 V D D Q5
A J 19 AB7
VTT Rail Values are VAXG 30 V D D Q6
A J 18 AB4
VAXG 31 V D D Q7
A J 16 Y1
A H 21 VAXG 32 V D D Q8 W7
Auburndale VTT=1.05V A H 19 VAXG 33 V D D Q9 W4
VAXG 34 V D D Q 10
A H 18 U1 C3 4 8 C 350 C3 9 C 57 +C 4 3
Clarksfield VTT=1.1V VAXG 35 V D D Q 11
POWER
A H 16 T7
VAXG 36 V D D Q 12 T4 1 u _6 . 3 V _ X 5 R _ 04 1 u _ 6 . 3 V _ X 5R _ 0 4 1 u_ 6 . 3 V _ X 5 R _0 4 1 u _ 6 . 3 V _ X5 R _ 0 4 1 0 0 u _ 6. 3V _ B _ A
V D D Q 13
P1
V D D Q 14
N7
V D D Q 15 N4
V D D Q 16 L1
V D D Q 17
DDR3
1 .1 VS _ VT T J 24 H1
V T T 1_ 4 5 V D D Q 18 1 .1 VS _ VT T
FDI
J 23
C 32 1 C 3 15 H 25 V T T 1_ 4 6
V T T 1_ 4 7
2 2 u _6 . 3 V _ X 5 R _0 8 2 2 u _ 6. 3V _X 5 R _ 08
P1 0 C3 2 8 C 65
V T T 0 _ 59 N1 0
V T T 0 _ 60
L 10 1 0 u_ 6 . 3 V _ X 5 R _0 6 1 0 u _ 6 . 3 V _ X5 R _ 0 6
V T T 0 _ 61
K1 0
V T T 0 _ 62
1 .1 V S_ V T T
J 22
V T T 1 _ 63
1.1V
1 .1 VS _ VT T K 26 J 20
V T T 1_ 4 8 V T T 1 _ 64
J 27 J 18 C3 2 2 C 320
V T T 1_ 4 9 V T T 1 _ 65
PEG & DMI

C 31 3 C 3 14 J 26 H2 1
V T T 1_ 5 0 V T T 1 _ 66
J 25 H2 0 2 2 u_ 6 . 3 V _ X 5 R _0 8 2 2 u _ 6 . 3 V _ X5 R _ 0 8
V T T 1_ 5 1 V T T 1 _ 67
2 2 u _6 . 3 V _ X 5 R _0 8 2 2 u _ 6. 3V _X 5 R _ 08 H 27 H1 9
1 .1 V S _ V T T G 28 V T T 1_ 5 2 V T T 1 _ 68
G 27 V T T 1_ 5 3
V T T 1_ 5 4 1 .8 V S
G 26
V T T 1_ 5 5
F 26 VCCPLL 0.6A
E 26 V T T 1_ 5 6 L 26
V T T 1_ 5 7 V C C P L L1
C 31 6 C 3 09 E 25 L 27
V T T 1_ 5 8 V C C P L L2
1.8V
C4 0 3 C3 5 8 M2 6 C4 1 C 37 C3 8 C4 2 C 46 C 44
2 2 u _6 . 3 V _ X 5 R _0 8 2 2 u _ 6. 3V _X 5 R _ 08 V C C P L L3
0 . 0 1 u_ 5 0 V _ X 7 R _ 0 4 0 . 0 1u _ 5 0 V _ X 7 R _ 0 4
1 u _6 . 3 V _ X 5 R _ 04 1 u _ 6 . 3 V _ X 5R _ 0 4 2 . 2 u_ 1 6 V _ X 5 R _ 0 6 4 . 7 u _6 . 3 V _ X 5 R _0 6 1 0 u _6 . 3 V _X 5 R _ 06 1 0 u _ 6 .3 V _ X 5 R_ 0 6
P Z 9 8 9 2 7 -3 64 1 -0 1 F
1 .5 V S _ C P U 4 ,3 1
1 .8 V S 20 , 3 3
VG F X_ CO R E 3 5
1 . 1 V S _ V T T 2 , 4 , 6 , 1 4 , 1 5 , 1 6 , 1 9, 20 , 2 1 , 3 4 , 3 5 , 3 6
1 .5 V 4, 9, 10 , 1 1 , 2 1 , 2 3 , 2 7 , 2 9, 31 , 3 3 , 3 6
B - 8 Processor 5/7
Schematic Diagrams
Processor 6/7
PROCESSOR 6/7 ( GND )

U 16H U1 6I
AT2 0 AE34
AT1 7 VSS1 VSS81 AE33
AR3 1 VSS2 VSS82 AE32 K27
AR2 8 VSS3 VSS83 AE31 K9 VSS16 1
VSS4 VSS84 VSS16 2
AR2 6 AE30 K6
VSS5 VSS85 VSS16 3
AR2 4 AE29 K3
VSS6 VSS86 VSS16 4
AR2 3 AE28 J 32
AR2 0 VSS7 VSS87 AE27 J 30 VSS16 5
AR1 2 VSS1 0 VSS90 AD1 0 H 35 VSS16 8
VSS1 1 VSS91 VSS16 9
AR 9 AC8 H 32
AR 6 AC4 H 28
AR 3 VSS1 4 VSS94 AC2 H 26 VSS17 2
AP2 0 AB35 H 24
AP1 7 VSS1 5 VSS95 AB34 H 22 VSS17 3
AP1 3
AP1 0
AP7
VSS1 6
VSS1 7
VSS1 8
VSS96
VSS97
VSS98
AB33
AB32
AB31
H 18
H 15
H 13
VSS17 4
VSS17 5
VSS17 6
Sheet 8 of 40
Processor 6/7
AP4 AB30 H 11
AP2 VSS2 0 VSS1 00 AB29 H8 VSS17 8
AN3 4 VSS2 1 VSS1 01 AB28 H5 VSS17 9
AN3 1 VSS2 2 VSS1 02 AB27 H2 VSS18 0
AN2 3 VSS2 3 VSS1 03 AB26 G 34 VSS18 1
AN2 0 VSS2 4 VSS1 04 AB6 G 31 VSS18 2
VSS2 5 VSS1 05 VSS18 3
AN1 7 AA10 G 20
AM2 9 VSS2 6 VSS1 06 Y8 G9 VSS18 4
AM2 7 VSS2 7 VSS1 07 Y4 G6 VSS18 5
AM2 5 VSS2 8 VSS1 08 Y2 G3 VSS18 6
AM2 0 VSS2 9 VSS1 09 W3 5 F30 VSS18 7
AM1 7 W3 4 F27
AM1 4 W3 3 F25
AM1 1 W3 2 F22
AM8 VSS3 3 VSS1 13 W3 1 F19 VSS19 1
AM5 VSS3 4 VSS1 14 W3 0 F16 VSS19 2
AM2 VSS3 5 VSS1 15 W2 9 E35 VSS19 3
AL3 4 VSS3 6 VSS1 16 W2 8 E32 VSS19 4
AL3 1
AL2 3
VSS3 7
VSS3 8
VSS3 9
VSS VSS1 17
VSS1 18
VSS1 19
W2 7
W2 6
E29
E24
VSS19 5
VSS19 6
VSS19 7
VSS
AL2 0 W6 E21
AL1 7 VSS4 0 VSS1 20 V10 E18 VSS19 8
AL1 2 VSS4 1 VSS1 21 U8 E13 VSS19 9
AL 9 VSS4 2 VSS1 22 U4 E11 VSS20 0
AL 6 VSS4 3 VSS1 23 U2 E8 VSS20 1
AL 3 VSS4 4 VSS1 24 T35 E5 VSS20 2
AK2 9 VSS4 5 VSS1 25 T34 E2 VSS20 3 AT35
AK2 7 VSS4 6 VSS1 26 T33 D 33 VSS20 4 VSS_N CTF1 AT1
AK2 5 VSS4 7 VSS1 27 T32 D 30 VSS20 5 VSS_N CTF2 AR34
AK2 0 VSS4 8 VSS1 28 T31 D 26 VSS20 6 VSS_N CTF3 B34
AK1 7 VSS4 9 VSS1 29 T30 D9 VSS20 7 VSS_N CTF4 B2
AJ3 1 VSS5 0 VSS1 30 T29 D6 VSS20 8 VSS_N CTF5 B1
NCTF
VSS5 1 VSS1 31 VSS20 9 VSS_N CTF6
AJ2 3 T28 D3 A35
VSS5 2 VSS1 32 VSS21 0 VSS_N CTF7
AJ2 0 T27 C 34
AJ1 7 VSS5 3 VSS1 33 T26 C 32 VSS21 1
AJ1 4 VSS5 4 VSS1 34 T6 C 29 VSS21 2
AJ1 1 VSS5 5 VSS1 35 R 10 C 28 VSS21 3
AJ 8 VSS5 6 VSS1 36 P8 C 24 VSS21 4
AJ 5 P4 C 22
AJ 2 P2 C 20
AH3 5 N 35 C 19
AH3 4 VSS6 0 VSS1 40 N 34 C 16 VSS21 8
AH3 3 VSS6 1 VSS1 41 N 33 B31 VSS21 9
AH3 2 VSS6 2 VSS1 42 N 32 B25 VSS22 0
AH3 1 VSS6 3 VSS1 43 N 31 B21 VSS22 1
AH3 0 N 30 B18
AH2 9 N 29 B17
AH2 8 VSS6 7 VSS1 47 N 28 B13 VSS22 5
AH2 7 N 27 B11
AH2 6 VSS6 8 VSS1 48 N 26 B8 VSS22 6
AH2 0 VSS6 9 VSS1 49 N6 B6 VSS22 7
AH1 7 VSS7 0 VSS1 50 M10 B4 VSS22 8
AH1 3 VSS7 2 VSS1 52 L 35 A29 VSS23 0
AH 9 L 32 A27
AH 6 VSS7 3 VSS1 53 L 29 A23 VSS23 1
AH 3 VSS7 4 VSS1 54 L8 A9 VSS23 2
AG1 0 VSS7 5 VSS1 55 L5 VSS23 3
AF8 VSS7 6 VSS1 56 L2
VSS7 7 VSS1 57
AF4 K34
VSS7 8 VSS1 58
AF2 K33
VSS7 9 VSS1 59
AE3 5 K30
VSS8 0 VSS1 60
PZ98 92 7- 364 1- 01F PZ989 27 -36 41 -01 F
Processor 6/7 B - 9
Schematic Diagrams
Processor 7/7
PROCESSOR 7/7 ( RESERVED )
1 .5 V
U 16E
AP2302GN
A J 13 R 36
R S V D 32
A J 12
R S V D 33 Q8 * 1 K _ 1% _ 0 4
PCI-Express Configuration Select
AP2 5 * A O 34 0 2 L
R SVD 1 V R E F _ C H _ A _ D I MM M V R E F _ D Q _D I M 0
AL 2 5 A H2 5 S D
AL 2 4 R SVD 2 R S V D 34 AK2 6
CFG0 1 : Single PEG R SVD 3 R S V D 35
AL 2 2
0 : Bifurcation enable R SVD 4
AJ 3 3 A L 26 R2 1 0 R 37
R SVD 5 R S V D 36
G
A G9 A R2 *1 0 0 K _ 0 4
R SVD 6 R S V D _ N C T F _ 37
M2 7 * 1 K _ 1% _ 0 4
L28 R SVD 7 A J 26
R SVD 8 R S V D 38 D R A MR S T _ C T R L 4 , 1 9
CF G 0 R 2 24 * 3 . 0 1K _0 4 R3 5 * 0 _0 4 V R E F _ CH _ A _ DIM M J17 A J 27
1 0 M V R E F _ D Q _D I M 0 V R E F _ CH _ B _ DIM M R SVD 9 R S V D 39
R3 9 * 0 _0 4 H1 7
1 1 M V R E F _ D Q _D I M 1 G2 5 R SVD 10 ? ? IBEX CONTROL
G1 7 R SVD 11
R SVD 12
CFG3 - PCI-Express Static Lane Reversal E3 1 AP1
E3 0 R SVD 13 R S V D _ N C T F _ 40 AT2
R SVD 14 R S V D _ N C T F _ 41 1 .5 V
1 : Normal Operation
Sheet 9 of 40 CFG3 0 : Lane Numbers Reversed
15 -> 0, 14 -> 1, ...
R S V D _ N C T F _ 42
R S V D _ N C T F _ 43
AT3
A R1
AP2302GN R 38
Processor 7/7 CF G 3 R 2 18 * 3 . 0 1K _0 4 C F G0 A M3 0
A M2 8 C F G [ 0]
R S V D 45
R S V D 46
A L 28
A L 29
AP3 0 V R E F _ C H _ B _ D I MM S
Q9
* A O 34 0 2 L
D M V R E F _ D Q _D I M 1
* 1 K _ 1% _ 0 4
C F G [ 1] R S V D 47
AP3 1 AP3 2
C F G3 AL 3 2 C F G [ 2] R S V D 48 A L 27
C F G4 AL 3 0 C F G [ 3] R S V D 49 A T 31 R2 1 3 R 40
CFG4 - Display Port Presence C F G [ 4] R S V D 50
G
A M3 1 A T 32 *1 0 0 K _ 0 4
A N2 9 C F G [ 5] R S V D 51 AP3 3 * 1 K _ 1% _ 0 4
C F G [ 6] R S V D 52
1 : Di sa b ll ed ; No p h ys ic al D is p la y Po rt C F G7 A M3 2 A R3 3 D R A MR S T _ C T R L 4 , 1 9
C F G [ 7] R S V D 53
a tt ac he d t o Em be dd e d Di sp la y P or t AK3 2 A T 33
AK3 1 C F G [ 8] R SVD _ N C T F _ 54 A T 34
C F G [ 9] R SVD _ N C T F _ 55
AK2 8 AP3 5 ? ? IBEX CONTROL
CFG4
RESERVED
AJ 2 8 C F G [ 10 ] R SVD _ N C T F _ 56 A R3 5
0 : En ab l ed ; An e xt e rn al D is pl a y Po rt C F G [ 11 ] R SVD _ N C T F _ 57
A N3 0 A R3 2
de vi ce i s c on ne ct ed to t he E mb e dd ed C F G [ 12 ] R S V D 58
A N3 2
is pl ay P o rt AJ 3 2 C F G [ 13 ]
AJ 2 9 C F G [ 14 ] E1 5
C F G [ 15 ] R S V D _ T P _ 59
? ?? ? ,? ?? ? AJ 3 0 F15
AK3 0 C F G [ 16 ] R S V D _ T P _ 60 A2
C F G [ 17 ] K EY
CF G 4 R 2 17 * 3 . 0 1K _0 4 R 20 8 * 0 _ 04 RS V D8 6 H1 6 D1 5
R S V D _ TP _8 6 R S V D 62
C1 5
RSVD86 R S V D 63 A J 15 RS V D6 4 _ R R2 1 4 * 1 0 mi l _ s ho rt _ 0 4
Connect to GND R S V D 64 RS V D6 5 _ R
A H1 5 R2 1 5 * 1 0 mi l _ s ho rt _ 0 4
R S V D 65
B1 9
R SVD 1 5
A1 9
CF G 7 R 2 21 * 3 . 0 1K _0 4 R SVD 1 6
R2 0 4 * 1 0 mi l _ s ho rt _ 0 4 H _ R S V D 17 _ R A2 0
H _ R S V D 18 _ R R SVD 1 7
CFG7 R2 0 3 * 1 0 mi l _ s ho rt _ 0 4 B2 0
R SVD 1 8 AA5
RS V D _ T P _ 66
Clar ksf ield (on ly f or earl y sa mpl es U9
R SVD 1 9 RS V D _ T P _ 67
AA4
T9 R8
pre- ES1 ) - Conn ect to GND with 3. 01K Ohm/ 5% R SVD 2 0 RS V D _ T P _ 68 A D3
RS V D _ T P _ 69
resi sto r A C9 A D2
R SVD 2 1 RS V D _ T P _ 70
AB9 AA2
R SVD 2 2 RS V D _ T P _ 71 AA1
RS V D _ T P _ 72
R9
RS V D _ T P _ 73 A G7
C1 RS V D _ T P _ 74 AE3
R S V D _ N C TF _2 3 RS V D _ T P _ 75
A3
R S V D _ N C TF _2 4
V4
RS V D _ T P _ 76
V5
RS V D _ T P _ 77 N2
RS V D _ T P _ 78
J29 A D5
R SVD 2 6 RS V D _ T P _ 79
J28 A D7
R SVD 2 7 RS V D _ T P _ 80 W3
RS V D _ T P _ 81
A3 4 W2
A3 3 R S V D _ N C TF _2 8 RS V D _ T P _ 82 N3
R S V D _ N C TF _2 9 RS V D _ T P _ 83 AE5
RS V D _ T P _ 84
C3 5 A D9
B3 5 R S V D _ N C TF _3 0 RS V D _ T P _ 85
R S V D _ N C TF _3 1
AP3 4 T P _ RS V D8 6
VSS VSS (AP34) can be left NC is
CRB implementation ; EDS/DG
recommendation to GND
P Z 9 89 2 7 -3 6 41 -0 1 F
1. 5V 4 , 1 0 , 1 1, 2 1 , 2 3 , 2 7 , 29 , 3 1 , 3 3 , 3 6
B - 10 Processor 7/7
Schematic Diagrams
DDRIII SO-DIMM_0
SO-DIMM A CHANGE TO STANDARD
JD I M M2 A
5 M_ A _ A [ 1 5 : 0 ] M_ A _ A 0 M_ A _ D Q0 M_ A _ D Q [ 6 3 : 0] 5
98 5 J D I MM 2 B
M_ A _ A 1 97 A 0 DQ 0 7 M_ A _ D Q1
A 1 DQ 1
M_ A _ A 2 96 15 M_ A _ D Q2
M_ A _ A 3 95 A 2 DQ 2 17 M_ A _ D Q3 1 .5 V
M_ A _ A 4 92 A 3 DQ 3 4 M_ A _ D Q4
M_ A _ A 5 A 4 DQ 4 M_ A _ D Q5
91 6 75 44
M_ A _ A 6 90 A 5 DQ 5 16 M_ A _ D Q6 76 VD D1 VSS 16 48
A 6 DQ 6 VD D2 VSS 17
M_ A _ A 7 86 18 M_ A _ D Q7 81 49
M_ A _ A 8 89 A 7 DQ 7 21 M_ A _ D Q8 82 VD D3 VSS 18 54
La yout Note : M_ A _ A 9 85 A 8 DQ 8 23 M_ A _ D Q9 87 VD D4 VSS 19 55
M_ A _ A 1 0 A 9 DQ 9 M_ A _ D Q1 0 VD D5 VSS 20
1 07 33 88 60
si gna l /spa c e/ signa l : M_ A _ A 1 1 84 A 10 / A P DQ 1 0 35 M_ A _ D Q1 1 93 VD D6 VSS 21 61
M_ A _ A 1 2 A 11 DQ 1 1 M_ A _ D Q1 2 VD D7 VSS 22
83 22 94 65
8/4/8 M_ A _ A 1 3 1 19 A 12 / B C # DQ 1 2 24 M_ A _ D Q1 3 3 .3 V S 99 VD D8 VSS 23 66
M_ A _ A 1 4 80 A 13 DQ 1 3 34 M_ A _ D Q1 4 10 0 VD D9 VSS 24 71
M_ A _ A 1 5 78
A 14 DQ 1 4
36 M_ A _ D Q1 5 20mils 10 5
VD D1 0 VSS 25
72
A 15 DQ 1 5 39 M_ A _ D Q1 6 10 6 VD D1 1 VSS 26 127
DQ 1 6 M_ A _ D Q1 7 VD D1 2 VSS 27
1 09 41 C1 0 1 C 10 2 11 1 128
5 M _ A _B S 0 1 08 B A0 DQ 1 7 51 M_ A _ D Q1 8 11 2 VD D1 3 VSS 28 133
5 M _ A _B S 1 B A1 DQ 1 8 VD D1 4 VSS 29
79 53 M_ A _ D Q1 9 1u _ 6 . 3 V _ X5 R _ 04 0 . 1 u_ 1 0 V _ X 7R _ 04 11 7 134
5 M _ A _B S 2 B A2 DQ 1 9 M_ A _ D Q2 0 VD D1 5 VSS 30
5 M _ CS # 0 1 14 40 11 8 138
1 21 S 0# DQ 2 0 42 M_ A _ D Q2 1 12 3 VD D1 6 VSS 31 139
5
5
5
5
M _ CS # 1
M_ C L K _ D D R 0
M_ C L K _ D D R # 0
M_ C L K _ D D R 1
1 01
1 03
1 02
S 1#
C K0
C K0 #
C K1
DQ 2 1
DQ 2 2
DQ 2 3
DQ 2 4
50
52
57
M_ A _ D
M_ A _ D
M_ A _ D
Q2 2
Q2 3
Q2 4
12 4
19 9
VD
VD
D1 7
D1 8
V D DS P D
VSS
VSS
VSS
VSS
32
33
34
35
144
145
150
Sheet 10 of 40
1 04 59 M_ A _ D Q2 5 151
5
5
5
5
M_ C L K _ D D R # 1
M _ CK E 0
M _ CK E 1
M _ A_ CAS #
73
74
1 15
C K1 #
C KE0
C KE1
DQ 2 5
DQ 2 6
DQ 2 7
67
69
56
M_ A _ D
M_ A _ D
M_ A _ D
Q2 6
Q2 7
Q2 8
3 .3 VS
R 72 10 K _ 0 4
77
12 2
12 5
N C1
N C2
VSS
VSS
VSS
36
37
38
155
156
161
DDRIII SO-DIMM _0
1 10 C AS# DQ 2 8 58 M_ A _ D Q2 9 N CT E ST VSS 39 162
5 M _ A_ RAS # R AS# DQ 2 9 M_ A _ D Q3 0 VSS 40
5 M _ A_ W E# 1 13 68 4 , 11 T S # _ D I MM 0_ 1 19 8 167
S A 0 _D I M 0 1 97 W E# DQ 3 0 70 M_ A _ D Q3 1 30 EV ENT # VSS 41 168
S A 1 _D I M 0 S A0 DQ 3 1 M_ A _ D Q3 2 4 , 11 D D R 3 _ D R A MR S T # R ESET# VSS 42
2 01 1 29 172
2 02 S A1 DQ 3 2 1 31 M_ A _ D Q3 3 20mils C1 7 2 . 2u _ 6 . 3 V _ X5 R _ 04 VSS 43 173
2 , 1 1 C L K _ S C LK S CL DQ 3 3 VSS 44
2 , 1 1 C L K _ S D A TA 2 00 1 41 M_ A _ D Q3 4 C1 8 0 . 1u _ 1 0 V _ X7 R _0 4 1 178
S DA DQ 3 4 M_ A _ D Q3 5 VR EF _ D Q VSS 45
1 43 2010/01/08 12 6 179
3 .3 VS 1 16 DQ 3 5 1 30 M_ A _ D Q3 6 VR EF _ C A VSS 46 184
5 M _ OD T0 O D T0 DQ 3 6 M_ A _ D Q3 7
CU? ? VSS 47
1 20 1 32 R1 9 *0 _ 0 4 R1 8 0 _0 4 185
5 M _ OD T1 O D T1 DQ 3 7 1 40 M_ A _ D Q3 8 9 MV R E F _ D Q _ D I M 0 2 VSS 48 189
5 M _A _D M[ 7 : 0 ] DQ 3 8 VS S1 VSS 49
R N3 M_ A _ D M 0 11 1 42 M_ A _ D Q3 9 M VR EF _ DIM 0 3 190
M_ A _ D M 1 D M 0 DQ 3 9 M_ A _ D Q4 0 VS S2 VSS 50
1 0 K _ 8 P 4 R_ 0 4 28 1 47 ? ? CPU SUPPORT C 89 2 . 2 u _6 . 3 V _ X 5 R _ 0 4 8 195
1 8 S A 1 _ DIM 1 M_ A _ D M 2 46 D M 1 DQ 4 0 1 49 M_ A _ D Q4 1 C 88 0 . 1 u _1 0 V _ X 7 R _ 0 4 9 VS S3 VSS 51 196
S A 1 _ DIM 1 1 1 D M 2 DQ 4 1 VS S4 VSS 52
2 7 S A 0 _ DIM 1 M_ A _ D M 3 63 1 57 M_ A _ D Q4 2 13
3 6 S A 1 _ DIM 0 S A 0 _ DIM 1 1 1 M_ A _ D M 4 1 36 D M 3 DQ 4 2 1 59 M_ A _ D Q4 3 2010/01/08 14 VS S5
D M 4 DQ 4 3 VS S6
4 5 S A 0 _ DIM 0 M_ A _ D M 5 1 53 1 46 M_ A _ D Q4 4 19
M_ A _ D M 6 D M 5 DQ 4 4 M_ A _ D Q4 5 VS S7 V TT _ ME M
1 70 1 48 2.2U? ? :6-07-22511-2A0 20
M_ A _ D M 7 1 87 D M 6 DQ 4 5 1 58 M_ A _ D Q4 6 25 VS S8
D M 7 DQ 4 6 M_ A _ D Q4 7 VS S9
5 M _A _D QS [ 7: 0 ] 1 60 26 203
M_ A _ D Q S0 12 DQ 4 7 1 63 M_ A _ D Q4 8 31 VS S 10 V T T1 204
D Q S0 DQ 4 8 VS S 11 V T T2
M_ A _ D Q S1 29 1 65 M_ A _ D Q4 9 32
M_ A _ D Q S2 47 D Q S1 DQ 4 9 1 75 M_ A _ D Q5 0 37 VS S 12 G ND 1
M_ A _ D Q S3 64 D Q S2 DQ 5 0 1 77 M_ A _ D Q5 1 38 VS S 13 G1 G ND 2
M_ A _ D Q S4 D Q S3 DQ 5 1 M_ A _ D Q5 2 VS S 14 G2
1 37 1 64 43
M_ A _ D Q S5 1 54 D Q S4 DQ 5 2 1 66 M_ A _ D Q5 3 VS S 15
D Q S5 DQ 5 3
M_ A _ D Q S6 1 71 1 74 M_ A _ D Q5 4 A S 0 A 62 1 -U 2S N -7 F
M_ A _ D Q S7 1 88 D Q S6 DQ 5 4 1 76 M_ A _ D Q5 5
D Q S7 DQ 5 5 1 81 M_ A _ D Q5 6
5 M _ A _ D Q S # [ 7: 0 ] M_ A _ D Q S# 0 DQ 5 6 M_ A _ D Q5 7
10 1 83
M_ A _ D Q S# 1 27 D Q S 0# DQ 5 7 1 91 M_ A _ D Q5 8
M_ A _ D Q S# 2 D Q S 1# DQ 5 8 M_ A _ D Q5 9
45 1 93
M_ A _ D Q S# 3 62 D Q S 2# DQ 5 9 1 80 M_ A _ D Q6 0
M_ A _ D Q S# 4 1 35 D Q S 3# DQ 6 0 1 82 M_ A _ D Q6 1
M_ A _ D Q S# 5 D Q S 4# DQ 6 1 M_ A _ D Q6 2
1 52 1 92
M_ A _ D Q S# 6 1 69 D Q S 5# DQ 6 2 1 94 M_ A _ D Q6 3
M_ A _ D Q S# 7 D Q S 6# DQ 6 3
1 86
D Q S 7# C LOSE TO SO- DI MM _ 0
1 .5 V A S 0 A 6 2 1-U 2 S N -7 F
R 63 1 K _ 1 % _0 4 M V R E F _D I M 0
1 .5 V
C3 6 0 + C 32 9 C4 9 C 69 C 84 C6 2 C 82 C 76 C7 1 C 75 + C 32 3
+
5 6 0 u_ 2 . 5 V _ 6 . 6* 6 . 6 *5 . 9 *5 6 0 u _2 . 5 V _ 6 . 6 *6 . 6 *5 . 9 R6 5 C9 2
*2 2 0 u_ 2 . 5 V _ B _ A 1 0u _ 6 . 3 V _ X5 R _ 06 1 0 u _6 . 3 V _ X 5 R _ 0 6 * 1 0 u_ 6 . 3 V _ X 5R _ 06 1 u_ 6 . 3 V _ X 5R _ 0 4 * 1u _ 6 . 3 V _ X5 R _0 4 * 1 u_ 6 . 3 V _ X 5R _ 0 4 1 u_ 6 . 3 V _ X 5R _ 04 * 1u _ 6 . 3 V _ X5 R _0 4
1 K _ 1 %_ 0 4 0. 1u _ 1 0 V _ X7 R _0 4
1. 5V
C8 0 C 52 C 59 C5 5 C 60 C 64 C6 6 C 72 C 85 C4 8 4 , 9 , 11 , 2 1 , 2 3 , 27 , 2 9 , 3 1 , 33 , 3 6 1 . 5 V
11 , 3 3 V T T _ ME M
0 . 1 u_ 1 0 V _ X7 R _ 04 0 . 1 u _1 0 V _ X 7 R _ 0 4 * 0 . 1 u_ 1 0 V _ X 7R _ 04 0 . 1u _ 1 0 V _ X7 R _ 04 * 0. 1 u _ 1 0V _X 7 R _ 0 4 * 0 . 1 u_ 1 0 V _ X 7R _ 04 *0 . 1 u _ 10 V _ X 7 R _ 0 4 0 . 1 u _1 0 V _ X 7 R _ 0 4 0 . 1 u _ 1 0V _ X 7 R _ 0 4 *0 . 1 u _1 0 V _ X 7 R _ 0 4
2 , 1 1 , 1 2, 13 , 1 4 , 1 5, 16 , 1 7 , 1 8, 19 , 2 0 , 2 1, 23 , 2 4 , 2 5 , 26 , 2 7 , 2 8 , 29 , 3 0 , 3 1 , 35 , 3 6 3 . 3 V S
V T T _ ME M
C1 0 6 C 11 0 C 108 C1 1 1 C 11 2
1 0u _ 6 . 3 V _ X5 R _ 06 * 1u _ 6 . 3 V _ X5 R _ 04 1 u _ 6 . 3 V _ X5 R _0 4 1 u_ 6 . 3 V _ X 5R _ 0 4 * 1u _ 6 . 3 V _ X5 R _0 4
DDRIII SO-DIMM_0 B - 11
Schematic Diagrams
DDRIII SO-DIMM_1
SO-DIMM B CHANGE TO STANDARD
5 M_ B _ A [ 1 5 : 0 ] JD I M M1 A M_ B _ D Q[ 6 3 : 0 ] 5
M_ B _ A 0 98 5 M_ B _ D Q 0 J D I M M1 B
M_ B _ A 1 A 0 D Q0 M_ B _ D Q 1
97 7
M_ B _ A 2 96 A 1 D Q1 15 M_ B _ D Q 2 1 .5 V
M_ B _ A 3 95 A 2 D Q2 17 M_ B _ D Q 3
M_ B _ A 4 A 3 D Q3 M_ B _ D Q 4
92 4
M_ B _ A 5 91 A 4 D Q4 6 M_ B _ D Q 5 75 44
M_ B _ A 6 A 5 D Q5 M_ B _ D Q 6 VDD 1 VS S 16
90 16 76 48
M_ B _ A 7 86 A 6 D Q6 18 M_ B _ D Q 7 81 VDD 2 VS S 17 49
M_ B _ A 8 A 7 D Q7 M_ B _ D Q 8 VDD 3 VS S 18
89 21 82 54
La y out Not e: M_ B _ A 9 85 A 8 D Q8 23 M_ B _ D Q 9 87 VDD 4 VS S 19 55
M_ B _ A 1 0 1 07 A 9 D Q9 33 M_ B _ D Q 10 88 VDD 5 VS S 20 60
si gnal /spa c e /si gna l : M_ B _ A 1 1 84
A 10 / A P D Q 10
35 M_ B _ D Q 11 93
VDD 6 VS S 21
61
M_ B _ A 1 2 83 A 11 D Q 11 22 M_ B _ D Q 12 94 VDD 7 VS S 22 65
8/4/8 M_ B _ A 1 3 1 19
A 12 / B C # D Q 12
24 M_ B _ D Q 13 99
VDD 8 VS S 23
66
M_ B _ A 1 4 80 A 13 D Q 13 34 M_ B _ D Q 14 1 00 VDD 9 VS S 24 71
A 14 D Q 14 VDD 10 VS S 25
M_ B _ A 1 5 78 36 M_ B _ D Q 15 1 05 72
A 15 D Q 15 39 M_ B _ D Q 16 1 06 VDD 11 VS S 26 12 7
1 09 D Q 16 41 M_ B _ D Q 17 1 11 VDD 12 VS S 27 12 8
5 M_ B _ B S 0 B A0 D Q 17 M_ B _ D Q 18 VDD 13 VS S 28
5 M_ B _ B S 1 1 08 51 1 12 13 3
79 B A1 D Q 18 53 M_ B _ D Q 19 1 17 VDD 14 VS S 29 13 4
5 M_ B _ B S 2 B A2 D Q 19 M_ B _ D Q 20 VDD 15 VS S 30
1 14 40 1 18 13 8
5 M_ C S #2 1 21 S 0# D Q 20 42 M_ B _ D Q 21 1 23 VDD 16 VS S 31 13 9
5 M_ C S #3 S 1# D Q 21 VDD 17 VS S 32
1 01 50 M_ B _ D Q 22 3 . 3V S 1 24 14 4
5 M _C L K _ D D R 2 C K0 D Q 22 M_ B _ D Q 23 VDD 18 VS S 33
1 03 52 14 5
5 M _C L K _ D D R # 2
1 02 C K0 # D Q 23 57 M_ B _ D Q 24 20mils 1 99 VS S 34 15 0
5 M _C L K _ D D R 3 C K1 D Q 24 M_ B _ D Q 25 VDD SP D VS S 35
5 M _C L K _ D D R # 3 1 04 59 15 1
73 C K1 # D Q 25 67 M_ B _ D Q 26 C1 0 3 C1 0 4 77 VS S 36 15 5
5 M_ C K E 2 C KE0 D Q 26 M_ B _ D Q 27 NC 1 VS S 37
Sheet 11 of 40
74 69 1 22 15 6
5 M_ C K E 3 1 15 C KE1 D Q 27 56 M_ B _ D Q 28 1 u _6 . 3 V _ X 5R _ 0 4 0. 1u _ 1 0 V _X 7 R _0 4 1 25 NC 2 VS S 38 16 1
5 M_ B _ C A S # C AS# D Q 28 N C TE S T VS S 39
1 10 58 M_ B _ D Q 29 16 2
5 M_ B _ R A S # R AS# D Q 29 M_ B _ D Q 30 VS S 40
5 M_ B _ W E # 1 13 68 4 , 1 0 T S # _D I MM 0 _ 1 1 98 16 7
SA 0 _ DIM 1 1 97 W E# D Q 30 70 M_ B _ D Q 31 30 EV ENT # VS S 41 16 8
DDRIII SO-DIMM _1 10
10
2 , 10
2 ,1 0
S A 0 _ DIM 1
S A 1 _ DIM 1
C LK _S C L K
CL K_ SD A T A
SA 1 _ DIM 1 2 01
2 02
2 00
S A0
S A1
S CL
D Q 31
D Q 32
D Q 33
12 9
13 1
14 1
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
32
33
34
C 21
C 22
4 ,1 0 DD R3 _ DR A M RS T #
2 . 2 u _6 . 3 V _ X 5 R _ 0 4
0 . 1 u _1 0 V _ X 7R _ 0 4 1
RE S E T # VS
VS
VS
S 42
S 43
S 44
17 2
17 3
17 8
S DA D Q 34 14 3 M_ B _ D Q 35 1 26 VREF _ D Q VS S 45 17 9
1 16 D Q 35 13 0 M_ B _ D Q 36 VREF _ C A VS S 46 18 4
5 M_ OD T 2 O DT 0 D Q 36 M_ B _ D Q 37 VS S 47
5 M_ OD T 3 1 20 13 2 9 M V R E F _D Q_ D I M1 R 22 * 0 _0 4 R2 1 0 _0 4 18 5
O DT 1 D Q 37 14 0 M_ B _ D Q 38 2 VS S 48 18 9
5 M_ B _ D M [ 7 : 0] M_ B _ D M 0 D Q 38 M_ B _ D Q 39 M V R E F _D I M1 VSS1 VS S 49
11 14 2 3 19 0
M_ B _ D M 1 28 D M0 D Q 39 14 7 M_ B _ D Q 40 C 91 2 . 2 u _6 . 3 V _ X 5 R _ 0 4 8 VSS2 VS S 50 19 5
D M1 D Q 40 VSS3 VS S 51
M_ B _ D M 2 46 14 9 M_ B _ D Q 41 C 90 0 . 1 u _1 0 V _ X 7R _ 0 4 9 19 6
M_ B _ D M 3 63 D M2 D Q 41 15 7 M_ B _ D Q 42 13 VSS4 VS S 52
M_ B _ D M 4 1 36 D M3 D Q 42 15 9 M_ B _ D Q 43 14 VSS5
M_ B _ D M 5 D M4 D Q 43 M_ B _ D Q 44 VSS6
1 53 14 6 19
M_ B _ D M 6 1 70 D M5 D Q 44 14 8 M_ B _ D Q 45 20 VSS7 V TT _ ME M
M_ B _ D M 7 D M6 D Q 45 M_ B _ D Q 46
2.2U? ? :6-07-22511-2A0 VSS8
1 87 15 8 25
D M7 D Q 46 16 0 M_ B _ D Q 47 26 VSS9 20 3
5 M_ B _ D Q S [ 7 : 0 ] D Q 47 VSS1 0 V T T1
M_ B _ D Q S0 12 16 3 M_ B _ D Q 48 31 20 4
M_ B _ D Q S1 D QS 0 D Q 48 M_ B _ D Q 49 VSS1 1 V T T2
29 16 5 32
M_ B _ D Q S2 47 D QS 1 D Q 49 17 5 M_ B _ D Q 50 37 VSS1 2 GN D 1
M_ B _ D Q S3 D QS 2 D Q 50 M_ B _ D Q 51 VSS1 3 G1
64 17 7 38 GN D 2
M_ B _ D Q S4 1 37 D QS 3 D Q 51 16 4 M_ B _ D Q 52 43 VSS1 4 G2
M_ B _ D Q S5 D QS 4 D Q 52 M_ B _ D Q 53 VSS1 5
1 54 16 6
M_ B _ D Q S6 1 71 D QS 5 D Q 53 17 4 M_ B _ D Q 54 A S 0 A 6 2 1-U A S N -7 F
M_ B _ D Q S7 1 88 D QS 6 D Q 54 17 6 M_ B _ D Q 55
D QS 7 D Q 55 M_ B _ D Q 56
5 M_ B _ D Q S # [ 7 : 0 ] 18 1
M_ B _ D Q S# 0 10 D Q 56 18 3 M_ B _ D Q 57
M_ B _ D Q S# 1 D QS 0# D Q 57 M_ B _ D Q 58
27 19 1
M_ B _ D Q S# 2 45 D QS 1# D Q 58 19 3 M_ B _ D Q 59
D QS 2# D Q 59
M_ B _ D Q S# 3 62 18 0 M_ B _ D Q 60
M_ B _ D Q S# 4 1 35 D QS 3# D Q 60 18 2 M_ B _ D Q 61
M_ B _ D Q S# 5 1 52 D QS 4# D Q 61 19 2 M_ B _ D Q 62
M_ B _ D Q S# 6 D QS 5# D Q 62 M_ B _ D Q 63
1 69 19 4
M_ B _ D Q S# 7 1 86 D QS 6# D Q 63
D QS 7#
A S 0 A 6 2 1-U A S N -7 F
CLOS E TO SO -DI M M_ 1
La y out Not e:
R 64 1 K _ 1 % _ 04 M V R E F _D I M 1
1 .5 V S O- DIM M _ 1 i s pl a ce d f a rt he r from the G M CH t ha n SO -DI M M _0 1 .5 V
R 66 C9 3
C 86 C 50 C 68 C7 7 C5 4 C7 8 C 70 C 61 1 K _ 1 %_ 0 4 0. 1u _ 1 0V _X 7 R _ 0 4
*1 0 u _ 6. 3 V _ X 5 R _ 0 6 1 0 u _6 . 3 V _ X 5R _ 0 6 1 0 u _ 6. 3 V _ X 5 R _ 0 6 *1 u _6 . 3 V _ X 5R _ 0 4 1u _ 6 . 3 V _ X5 R _0 4 1 u_ 6 . 3 V _ X 5R _ 04 1 u _6 . 3 V _ X 5 R _ 0 4 * 1u _ 6 . 3 V _ X5 R _0 4
1 .5 V
C 11 6 C 24 C 56 C2 3 9 C6 3 C7 3 C 79 C 83 C 47 C7 4 4 , 9, 10 , 2 1 , 2 3, 27 , 2 9 , 3 1, 3 3 , 3 6 1 . 5V
1 0 , 3 3 V T T _M E M
0 . 1 u_ 1 0 V _ X 7R _ 04 0 . 1 u _1 0 V _ X 7R _ 0 4 0 . 1 u _ 10 V _ X 7 R _ 0 4 0. 1 u _ 1 0V _ X 7 R _ 0 4 0. 1u _ 1 0V _X 7 R _ 0 4 0 . 1 u_ 1 0 V _ X7 R _0 4 0 . 1 u_ 1 0 V _ X 7R _ 04 0 . 1 u _1 0 V _ X 7R _ 0 4 0 . 1 u _ 10 V _ X 7 R _ 0 4 0. 1 u _ 1 0V _ X 7 R _ 0 4 2, 10 , 1 2 , 1 3, 1 4 , 1 5 , 1 6, 1 7 , 1 8 , 19 , 2 0 , 2 1 , 23 , 2 4 , 2 5, 26 , 2 7 , 2 8, 29 , 3 0 , 3 1, 3 5 , 3 6 3 . 3V S
V T T _ ME M
C 10 7 C 11 4 C 1 15 C1 0 9 C1 1 3
1 0 u_ 6 . 3 V _ X 5R _ 06 1 u _ 6. 3 V _ X 5 R _ 0 4 * 1 u_ 6 . 3 V _ X 5R _ 04 1u _ 6 . 3 V _X 5 R _0 4 *1 u _6 . 3 V _ X 5 R _ 0 4
B - 12 DDRIII SO-DIMM_1
Schematic Diagrams
LVDS, Inverter
PANEL CONNECTOR 3 .3 V S EDID Mode

COSTDOWN 2 3 R N6
1 4 2 . 2 K _ 4P 2R _0 4
VIN V IN_ L CD ? ? ? ?
J _ LC D 1
L25 *1 5 m il _ s ho rt _ 0 6
8 0mi ls 1 2 P _ D D C _D A T A
3 1 2 4 P _ D D C _C LK P _ DDC _ DA T A 1 7
3 4 P _ DDC _ CL K 1 7
5 6
7 5 6 8 B R I GH TN E S S
7 8 B RIG HT N E S S 2 8
C 30 7 C 3 04 C 30 1 9 10
11 9 10 12 I N V _ B L ON
11 12
0 . 1 u_ 5 0 V _Y 5 V _ 06 0 . 1 u _5 0 V _ Y 5 V _ 06 0 . 1 u _5 0 V _ Y 5 V _ 06 13 14
L V D S -L C L K N 15 13 14 16 LV D S -L 2N
17 L V D S -LC L K N L V D S -L C L K P 15 16 LV D S -L 2P L V D S -L 2 N 1 7
17 LV D S -L C L K P 17 18 L V D S -L 2 P 1 7
19 17 18 20
L V D S -L 1N 19 20
17 L V D S -L 1 N 21 22
L V D S -L 1P 23 21 22 24
17 L V D S -L1 P 23 24 3 . 3V S
25 26
L V D S -L 0N 27 25 26 28
17 L V D S -L 0 N L V D S -L 0P 29 27 28 30
17 L V D S -L0 P 29 30
87 2 1 6-3 0 0 6 C2 9 8
CLOSE TO LVDS CONN. 2A 0. 1u _ 10 V _ X 7 R _ 04
PIN PL VD D
C4
4. 7 u _ 6. 3 V _ X 5R _ 06
C 6
0 . 1 u _1 0 V _ X7 R _0 4
Sheet 12 of 40
PANEL POWER LVDS, Inverter
3. 3 V S
2A 3 .3 V
C 15 PL VD D D1 4
U 1 C
0. 1 u _ 10 V _ X 7 R _ 04 4 1 2A B R I GH T N E S S AC C 2 97
VIN V O UT
5 A * 0 . 1u _ 1 0V _ X 5 R _ 0 4
VIN
*B A V 9 9 R E C T I F I E R
3 2
1 7 N B _ E NA V D D EN GN D
R 13 G5 2 4 3A
1 0 0 K _ 04
INVERTER CONNECTOR
R6 8 1 0K _ 0 4 B K L _ E N_ R
28 BKL _ EN
R6 7 C 96
10 0 K _ 0 4 0 . 4 7u _ 1 0V _ Y 5V _ 0 4
3 .3 V 3. 3V 3 .3 V
U3 A
14
7 4L V C 08 P W U 3B
14
1 7 4 LV C 0 8P W C 95
3 Z 1 2 01 4
B LO N 2 6 * 0. 1u _ 1 0V _ X 5 R _ 04
1 7 BL O N 5
7
R6 9
7
10 0 K _ 0 4 U 3C
14
7 4 L V C0 8 P W
19 S B _B L O N Z12 02 9
3. 3V 8 I N V _ B L ON
R 70 1 00 K _ 0 4 Z12 03 10
U 3D
14
7 4 LV C 0 8P W R7 1 C 99
7
28 , 3 0 L ID_ S W # 12
11 1 M_ 04 0 . 1 u _1 0 V _ X7 R _ 0 4
16 , 2 8 A L L_ S Y S _P W R G D 13
7
3 0 , 3 1, 3 2 , 3 3, 3 4 , 3 5, 3 6 , 3 7 V IN
3 , 4 , 1 4 , 15 , 1 6 , 18 , 1 9 , 20 , 2 1 , 23 , 2 4 , 2 5, 2 9 , 3 0, 3 1 , 3 3, 3 4 , 3 5 3. 3 V
2 , 1 0, 1 1 , 1 3, 1 4 , 1 5, 16 , 1 7 , 18 , 1 9 , 20 , 2 1 , 23 , 2 4 , 25 , 2 6 , 2 7, 2 8 , 2 9, 3 0 , 3 1, 3 5 , 3 6 3. 3 V S
3 1 ,3 2 SYS1 5 V
LVDS, Inverter B - 13
Schematic Diagrams
HDMI, CRT
L 27
For ESD 1 _0 4 5 VS
5V S
HDMI PORT RD2 RD3

B A V9 9 R E C TI F I E R B A V 99 R E C T FI I E R
R 20 7
FOR INTEL GRAPHIC
C
A
A
RD1 1_ 04
B A V9 9 R E C TI F I E R J _H D MI 1
U2
AC
AC
AC
C 32 7 C 32 4
17 H D MI B_ D 2B P 39 22 H D MI B_ D A TA 2P
38 I N _D 1 + OU T_ D 1+ 23 H D MI B_ D A TA 2N 10 u_6 . 3V _X 5R _ 06 22 u_ 6. 3V _ X5 R _0 8
17 H D MI B_ D 2B N I N _D 1 - OU T_D 1 - 5 VS 19 H D MI B_ E XT1 _H P D
42 19 H D MI B_ D A TA 1P RN2 200 9. 06 .1 8 18 H OT PL U G D ET E C T
17 H D MI B_ D 1B P I N _D 2 + OU T_ D 2+ + 5V
17 H D MI B_ D 1B N 41 20 H D MI B_ D A TA 1N 2. 2 K_ 4P 2 R _0 4 17
I N _D 2 - OU T_D 2 - H D MI B_ E XT1 _S D A 16 D D C / C E C GN D
45 16 H D MI B_ D A TA 0P 1 4 S DA 15 H D MI B_ E XT1 _S C L
17 H D MI B_ D 0B P I N _D 3 + OU T_ D 3+ H D MI B_ D A TA 0N S CL
17 H D MI B_ D 0B N 44 I N _D 3 - OU T_D 3 - 17 2 3 F OR E MI 14 R E S E R VE D FOR E MI
L5 13 H D MI_ C E C
48 13 H D MI B_ C LOC K P H D MI B_ C LOC K N 1 2 12 CE C
17 H D MI B_ C LK B P 47 I N _D 4 + OU T_ D 4+ 14 H D MI B_ C LOC K N T MD S C L OC K - 11
17 H D MI B_ C LK B N I N _D 4 - OU T_D 4 - H D MI B_ C LOC K P 4 3 10 C L K S H I E LD L6
H D MI _C T R LC L K 9 28 H D MI B_ E XT1 _S C L * H D MI 201 2F 2 SF -90 0T 04 -sho rt T MD S C L OC K + 9 4 3 H D MI B _D A TA 0 N
1 7 H D MI _C TR LC LK
*L VA R 0 40 2-24 0E 0 R 05P -L F
H D MI _C T R LD A T A 8 SCL SC L _S I N K 29 H D MI B_ E XT1 _S D A 8 TMD S D A TA 0-
*LV A R 04 02 -240 E 0R 0 5P -LF

1 7 H D MI _C T R LD A TA SDA S D A _S I N K S H I E LD 0 7 1 2 H D MI B _ D AT A 0P
T MD S D A TA 0 +
R4 2
M_P OR T B_ H P D #_ R 7 30 H D MI B_ E XT1 _H P D 6 *H D MI 20 12 F2 S F-9 00 T0 4-sh ort
R 41
HP D H P D _S I N K T MD S D A T A1 -
*L VA R 0 40 2-24 0E 0 R 05P -L F
R4 4
5
*LV A R 04 02 -2 40 E 0R 05 P -LF
R 43
R5 6 *4. 7 K_ 04 Z4 30 4 25 2 4 S H IE L D 1
3 . 3V S OE # V C C [1 ] 3 3. V S T MD S D A T A1 +
R4 7 *0_ 04 V C C [2 ] 11 R4 8 TMD S D A TA 2- 3
D C C _E N # 32 15 C1 C 40 C3 1 2
D C C _E N # V C C [3 ] S H I E LD 2
? ? ? 10 R T_ E N # V C C [4 ] 21 2 0K _1 %_0 4 T MD S D A TA 2 + 1
26 0. 1u _1 0V _X 7R _ 04 0. 1 u_ 10V _ X7 R _0 4 0 1. u_ 10 V_ X7 R _0 4
PC 0 3 V C C [5 ] 33
PC 1 4 PC0 V C C [6 ] 40
R2 8 49 9_ 1%_ 04 Z4 30 5 6 PC1 V C C [7 ] 46 H D MI B_ D A TA 1N 1 2
R E XT V C C [8 ]
1 H D MI B_ D A TA 1P 4 3 L8
3. 3 VS R4 9 *4. 7 K _04 Z4 30 6 34 G N D [1 ] 5 C2 6 C 67 C 1 28 17 -119 A 5-L 4 3 H D MI B _D A TA 2 N
OE _1 G N D [2 ]
*L VA R 0 40 2-24 0E 0 R 05P -L F
R5 8 *4. 7 K _04 Z4 30 7 35 12 L7
*LV A R 04 02 -240 E 0R 0 5P -LF

QE _2 G N D [3 ] 2 H D MI B _ D AT A 2P
Sheet 13 of 40 G N D [4 ]
18 0 . 1u _1 0V _X 7R _ 04 0. 1u _1 0V _X 7R _ 04 *H D MI2 01 2F 2S F -90 0T 04 -s ho rt 1
R5 1
? ? ? 24 *H D MI 20 12 F2 S F-9 00 T0 4-sh ort
R 46
G N D [5 ]
*L VA R 0 40 2-24 0E 0 R 05P -L F
27
*LV A R 04 02 2- 40 E 0R 05 P -LF
G N D [6 ]
R5 9
R 55
G N D [7 ] 31
36 3 . 3V S
HDMI, CRT 49
GN D
P T N 33 60B B S
G N D [8 ]
G N D [9 ]
GN D [ 10 ]
37
43
P OR T C _H P D
R 26
M_ P OR TB _H P D # _R
R3 4
P I N 4 9 =G N D *1 0mi l _sh ort
* 20 K_ 1% _04
P OR TC _ H P D 3 . 3V S
6-03-03360-030 17 P OR TC _ H P D
D
PS 810 1 ( 6-0 3-0 810 1-0 32) PI N T O P IN Q7
*MT N 70 02 Z H S3
G M_P OR TB _ H PD #_R C 31 7 C 53
R 57 4. 7 K_ 04 D C C _ EN # C 35 R3 3
S
3. 3V S 0. 1u _1 0V _X 7R _ 04 0. 1 u_ 10V _ X7 R _0 4
R 30 4. 7 K_ 04 P C0 *0 . 1u _10 V _X 7R _ 04 *7 . 5K _1 %_0 4 R3 2
R 29 *4 .7 K _0 4 P C1 *2 0K _1 %_ 04
? ? ?
J _C R T 1
6-19-31001-264 108 A H 15 FS T 04N 1C 3
CRT PORT 3. 3V S 5 VS
L4 . F C M10 05 K F-3 00 T03
R ED 1
2
9
2 4 m il
1 7 D A C _R E D L3 . F C M10 05 K F-3 00 T03 GR N 10
1 7 D A C _GR E E N
4
3
4
3
L2 . F C M10 05 K F-3 00 T03 BL U E 3
RN7 RN1 1 7 D A C _B L U E 11
6 p_ 50 V _N P O_0 4
6 p_ 50 V_ N P O_0 4
2. 2K _ 4P 2R _ 04 2. 2K _ 4P 2R _ 04 4
6 p_ 50 V_ N P O_04
6p _5 0V _N PO_ 04
6p _5 0V _N P O_0 4
6 p_ 50V _ N PO _04
12 DDCDA T A
U1 5 R1 2 R 11 R 10 5
1
2
1
2
10 9 D D C D A TA 13 HS Y NC
17 D A C _ D D C AD A T A D D C _I N 1 D D C _ OU T1
1 50 _1% _0 4 15 0_1 %_ 04 15 0_ 1% _0 4 6
11 12 D D C LK 14 V S Y NC
17 D A C _ D D C AC L K D D C _I N 2 D D C _ OU T2 7
13 14 C R T _H S Y N C R1 5 33 _04 HS Y NC 15 DDCL K
1 7 D A C _ H SY N C SY N C _ I N 1 S Y N C _ OU T1 8
C 10
C1 2
C1 4
C1 6
C 30 2 10 00 p_5 0V _ X7 R _0 4
C 3 00 2 20 p_ 50 V_ N P O_0 4
C 7 10 00 p_5 0V _ X7 R _0 4
15 16 C R T _V S Y N C R1 4 33 _04 VS Y N C
C 13
C 11
C 2 99 2 20p _5 0V _N PO_ 04
17 D AC _ V SY N C SY N C _ I N 2 S Y N C _ OU T2
GN D 1
GN D 2
5V S 1 3 BL U E
VC C _ S Y N C V I D E O_1
3 . 3V S 2 4 GR N
VC C _ V ID EO V I D E O_2
7 5 RE D
3. 3 VS VC C _ D D C V I D E O_3
8 6
BY P GN D
I P 47 72 C Z1 6
0. 2 2u _5 0V _0 6
0 . 22 u_ 50V _ 06
0. 22 u_ 50 V _06
C 3 05
C 30 6
C 303
C M20 09- 02Q R P N:6 -02 -200 90- B60

I P47 72C Z16 PN :6- 02- 4772 1-B 60
2 , 10 , 11, 1 2, 1 4, 15 , 16 , 17, 1 8, 1 9, 20 , 21 ,2 3, 2 4, 2 5, 26 , 27 ,2 8, 2 9, 30 , 31 , 35, 3 6 3. 3 V S

2, 1 7, 20 , 21 ,2 6, 2 7, 30 , 31 , 35, 3 6 5V S
B - 14 HDMI, CRT
Schematic Diagrams
IBEXPEAK - M 1/9
2 0m ils
RT C V CC
IBEXPEAK - M (HDA,JTAG,SATA)
V DD 3 1 A
20 mils C 408
1 5 p_ 5 0 V _ N P O_ 0 4
C 3 C 382 2 . 2 u_ 1 6 V _ X 5 R _ 0 6
R T C_ V B A T _ 1 2 A
2
1
R 299
2 0 K_ 1 % _ 0 4 X6 R 297
D 16 C M 20 0 S 3 2 7 6 8 12 2 0 _ 3 2. 76 8 K H z
B A T5 4 C S 3 1 0 M _ 04 U 20A
3
4
RTC CLEAR C 404
R 251 C4 0 5 J O PEN 2 1 5 p_ 5 0 V _ N P O_ 0 4 R T C_ X 1 B 13 D3 3
RT C X 1 FW H 0 / L AD 0 LP C_ A D 0 2 4 , 28
* OP E N _ 1 0 m i -l 1 M M R T C_ X 2 D 13 B3 3
RT C X 2 FW H 1 / L AD 1 LP C_ A D 1 2 4 , 28
10 m ils 1 K_ 0 4 2 . 2 u_ 1 6 V _ X 5 R _ 0 6
Z o= 50O ? 5% FW H 2 / L AD 2
C3 2
LP C_ A D 2 2 4 , 28
2
A3 2 LP C_ A D 3 2 4 , 28
R T C_ V B A T 1 R 300 R T C_ R S T # C 14 FW H 3 / L AD 3
J _ RT C 1 2 0 K_ 1 % _ 0 4 RT C RS T # C3 4
F W H 4 / L F R A ME # LP C _ F R A M E # 2 4 , 28
S R T C _R T C # D 17
1 S RT C RS T #
J_RTC1 A3 4
LPC
L D RQ 0 #
RTC
TPM CLEAR S M_ I N TR U D E R # A 16 F34
2 INT R UD E R # L D R Q1 # / G P I O 2 3
R2 9 4 C4 0 6 J O PEN 1
* OP E N _ 1 0 m i -l 1 M M R2 9 3 3 3 0 K_ 0 4 P C H _ I N T V R ME N A 14 AB9 S E R IRQ
R T CV CC INT V R M E N S E RIR Q S E R IRQ 2 4 ,2 8
1 2 8 5 2 05 -0 2 7 0 1 1M _ 0 4 2 . 2 u_ 1 6 V _ X 5 R _ 0 6
2
A 30
2 7, 29 H D A _ B I T C L K HD A _ B C L K AK7 S A T A R X N0
3 .3 V S
BIOS ROM 2 7, 29 H D A _ S Y N C
27 H D A_ SPKR
H DA _ S P K R
D 29
P1
HD A _ S Y NC
SPKR
S A TA 0R X N
S A T A 0 RX P
SATA0 TXN
S A TA 0 TX P
AK6
AK1 1
AK9
SATAR XP0
S A T A T X N0
SATATXP0
S A T A R X N0
SATAR XP0
SATATXN 0
SATATXP0
26
26
26
26
SATA HDD
N C1
S H O RT
C 21 7
0 . 1 u _1 0 V _ X 7 R _ 0 4
32Mbit 32Mbit
2 7, 29 H D A _ R S T # C 30
HD A _ RS T #
S A TA 1R X N
AH 6 S A T A R X N1
S A T A R X N1 26
Sheet 14 of 40
AH 5 SATAR XP1 SATAR XP1 26
S P I_ V D D 8
U1 0
V DD S I
5 SPI_ SI SPI_ VD D 8
U 11
VD D SI
5 SPI_ SI 27
29
HD A _ S D IN0
HD A _ S D IN1
G 30
F 30
HD A _ S D IN0
HD A _ S D IN1
S A T A 1 RX P
SATA1 TXN
S A TA 1 TX P
AH 9
AH 8
S A T A T X N1
SATATXP1
SATATXN 1
SATATXP1
26
26
SATA ODD IBEXPEAK - M 1/9
R 159 2 SPI_ SO 2 SPI_ SO AF1 1
3 .3 K _ 1 % _ 0 4 SO SO E 32 S A TA 2R X N AF9
HD A _ S D IN2 S A T A 2 RX P
IHDA
S P I_ W P # 3 1 SPI_ C S0 # SPI_ W P# 3 1 SPI_ C S1 # AF7
W P# C E# W P# C E# SATA2 TXN
F 32 AF6
SPI_ SC L K SPI_ SC L K HD A _ S D IN3 S A TA 2 TX P
R 152 6 6
3 .3 K _ 1 % _ 0 4 SC K SC K AH 3
S A TA 3R X N
S P I _ H OL D # 7 4 S P I _ H OL D #7 4 B 29 AH 1
HO L D# VS S HO L D# VS S 2 7, 29 H D A _ S D O U T HD A _ S D O S A T A 3 RX P
AF3
MX 2 5 L 3 20 5 D M2 I -1 2 G *M X 2 5 L3 2 0 5 D M 2 I -1 2 G SATA3 TXN AF1
R 298 1 K_ 0 4 H DA _ DO CK _ E N# H 32 S A TA 3 TX P
SATA
H D A _ D O C K _ E N # / GP I O3 3 S A T A R X N2
AD 9
J 30 S A TA 4R X N AD 8 SATAR XP2
SPI_* = 1.5"~6.5" HD A _ DO C K _ RS T # / G P IO 1 3 S A T A 4 RX P
D 17 R B7 5 1 V AD 6 S A T A T X N2
SATA4 TXN SATATXP2
C A AD 5
28 ME _ W E # S A TA 4 TX P
P C H _ JT A G _ T C K _B U F M3 AD 3
J TA G_ T C K S A TA 5R X N
1
AD 1
P C H _ JT A G _ T MS S A T A 5 RX P
J OP E N 3 K3 AB3
*O P E N _ 10 m i l -1 MM J TA G_ T MS SATA5 TXN AB1
S A TA 5 TX P
Flash Descriptor P C H _ JT A G _ T D I K1
J TA G_ T D I
2
1 .1 VS_ VT T
JTAG
Security Overide P C H _ JT A G _ T D O J2 AF1 6 S A T A I C OM P R8 9 37 . 4 _ 1 % _ 0 4
J TA G_ T D O S A T A ICO M P O
P C H _ JT A G _ R S T # J4 AF1 5
J TA G_ R S T # S A T A I C O MP I
SPI_ SC L K BA2 3 .3 V S
S P I _ C LK
SPI_ C S0 # S P I_ CS 0 # _ R AV3 R2 7 5 *1 0 K _ 0 4
SPI_ C S 0 #
SPI_ C S1 # S P I_ CS 1 # _ R AY3 T3 SATA_ L ED #
SPI_ C S 1 # S ATAL ED # S A T A _ LE D # 2 9 3 .3 VS
3 .3 V SPI_ SI AY1 Y9 O DD _ DE T E C T # R1 0 8 10 K _ 0 4
S P I _ M OS I SAT A0 G P / G PIO 2 1
SPI_ SO S P I _ S O_ R
SPI
R 262 33_04 AV1 V1 O D D _ D E TE C T # 2 6
SPI_ M ISO SAT A1 G P / G PIO 1 9
R 290 R 28 8 R 2 86 R 283
I b e xP e ak -M _ R e v 0 _ 9 SATA_ D ET# 1 R2 7 1 10 K _ 0 4
* 2 0K _1 % _ 0 4 * 20 0 _ 0 6 * 20 0 _ 0 6 * 2 00 _ 0 6
PC H _ J T A G_ T M S
PC
PC
PC
H _ J T A G_ T D I
H _ J T A G_ T D O
H _ J T A G_ R S T #
3 .3 VS
R 93 1 0 K _ 04 S E R IR Q
ESATA
R 2 78 *1 K _ 0 4 H DA _ S P K R
R 289 R 28 5 R 2 84 R 282 NO REBOOT STRAP: HDA_SPKR High Enable S A T A T XP 2 C 17 4 * 0 . 0 1 u_ 5 0 V _ X 7 R _ 0 4
* 1 0K _0 4 *1 0 0 _1 % _ 0 4 * 10 0 _ 1 % _ 04 * 1 00 _ 1 % _ 0 4 S A T A T XN 2 C 17 1 * 0 . 0 1 u_ 5 0 V _ X 7 R _ 0 4
3 .3 VS iTPM ENABLE/DISABLE
R 2 61 *1 K _ 0 4 S P I _S I S A T A RX N 2 C 16 1 * 0 . 0 1 u_ 5 0 V _ X 7 R _ 0 4
R2 8 1 *4 . 7 K _ 0 4 P C H _ JT A G_ T C K _B U F
TPM FUNCTION:SPI_SI High Enable S A T A RX P 2 C 17 0 * 0 . 0 1 u_ 5 0 V _ X 7 R _ 0 4
? ? ? ? , ESATA REDRIVER? ? ? ? ? ?
2 3, 25 , 2 8 , 2 9 , 3 1 , 3 2, 3 7 V D D 3
21 R T CV CC
2 , 4 , 6 , 7 , 1 5 , 1 6 , 1 9 , 20 , 2 1 , 3 4 , 3 5 , 3 6 1 . 1V S _ V T T
3 , 4 , 12 , 1 5 , 1 6 , 1 8 , 1 9, 20 , 2 1 , 2 3 , 2 4 , 2 5, 29 , 3 0 , 3 1 , 3 3 , 3 4, 3 5 3 . 3 V
2, 10 , 1 1 , 1 2 , 1 3 , 1 5, 16 , 1 7 , 1 8 , 1 9 , 2 0, 2 1 , 2 3 , 2 4 , 2 5 , 26 , 2 7 , 2 8 , 2 9 , 3 0, 31 , 3 5 , 3 6 3 . 3 V S
IBEXPEAK - M 1/9 B - 15
Schematic Diagrams
IBEXPEAK - M 2/9
IBEXPEAK - M (PCI-E,SMBUS,CLK) SM B_ C L K
R N 16
2 . 2 K _4 P 2 R _ 0 4
3 2
3 .3 V
SM B_ D ATA 4 1
U2 0 B R N 11
2 . 2 K _4 P 2 R _ 0 4
B G3 0 B9 P C H _ B T_ E N # S M L 0 _ DAT A 3 2
PE R N1 S MB A L E R T # / GP I O 1 1 PCH _ B T _ E N # 2 9
B J3 0 S M L 0 _ CL K 4 1
BF 2 9 PER P1 H 14 S M B _ C LK
P E T N1 S M B C LK S MB _ C L K 2
BH2 9 R N 13
PETP1 SM B_ D ATA
C 8 S MB _ D A T A 2 1 0 K _ 8 P 4 R _ 04
AW 3 0 S M B D A TA P C H _ B T _E N # 1 8
23 P C I E _ R X N 2 _N E W _C AR D PE R N2
BA3 0 18 U S B _O C #8 9 U S B _ OC # 89 2 7
23 P C IE _ RX P 2 _ N EW _ C A RD P C I E _ T XN 2 _ C PER P2 P C H _ U P E K _I N I T # L P D _ S P I_ IN T R#
C1 2 4 0 . 1 u _ 10 V _ X 7 R _0 4 BC3 0 J14 P CH _ UP E K _ INIT # 1 8 3 6
23 P C I E _T X N 2 _N E W _C AR D C1 2 5 0 . 1 u _ 10 V _ X 7 R _0 4 P C I E _ T XP 2 _C BD3 0 P E T N2 S M L 0 A L E R T # / GP I O 6 0 4 5
23 P C I E _T X P 2 _ N EW _ C A RD PETP2 C 6 S M L 0 _C L K
S ML 0 C LK S ML 0 _ C LK 23
AU3 0 R N 10
2 3 P CIE _ R X N3 _ W L A N PE R N3
SMBus
A T3 0 G 8 S M L 0 _D A T A 2 . 2 K _4 P 2 R _ 0 4
2 3 P CIE _ R X P 3 _ W L A N PER P3 S ML 0 D A TA S ML 0 _ D A T A 2 3
C1 3 1 0 . 1 u _ 10 V _ X 7 R _0 4 P C I E _ T XN 3 _ C AU3 2 S M D _ CP U _ T HE R M 3 2
2 3 P C IE _ T X N3 _ W L A N P C I E _ T XP 3 _C P E T N3 S M C _ CP U _ T HE R M
C1 3 0 0 . 1 u _ 10 V _ X 7 R _0 4 AV3 2 4 1
2 3 P C IE _ T X P 3 _ W L A N PETP3 L P D _ S P I _ I N TR #
M 14
S M L 1 A L E R T # / GP I O 7 4
BA3 2
2 5 P C I E _ R X N 4 _ GL A N PE R N4
BB3 2 E1 0 S M C _ C P U _ TH E R M
2 5 PC IE_ RXP4 _ G L AN P C I E _ T XN 4 _ C PER P4 S M L 1 C L K / GP I O 5 8 S M C_ C P U_ T H E RM 3 ,2 8
C1 2 6 0 . 1 u _ 10 V _ X 7 R _0 4 BD3 2
25 P C I E _ TX N 4 _ GL A N C1 2 7 0 . 1 u _ 10 V _ X 7 R _0 4 P C I E _ T XP 4 _C BE3 2 P E T N4 G 12 S M D _ C P U _ TH E R M
25 P C I E _ TX P 4 _ G L A N PETP4 S M L1 D A T A / GP I O 7 5 S M D_ C P U_ T H E RM 3 ,2 8
PEG _ CL KR EQ #
PCI-E*
BF 3 3 R 287 1 0K _0 4
BH3 3 PE R N5 T13
B G3 2 PER P5 C L_ C L K 1 L A N _ C L K R E Q# R 112 1 0K _0 4
B J3 2
P E T N5 Controller T11
Sheet 15 of 40 PCI-E x1 Usage

BA3 4
AW 3 4
PETP5
PE R N6
Link
CL _ D A T A 1
C L _R S T 1 #
T9
Lane 1 WLAN PER P6
IBEXPEAK - M 2/9 Lane

Lane
2
3
NEW CARD
3G
BC3 4
BD3 4 P E T N6
PETP6
P E G _A _ C L K R Q# / GP I O 4 7
H 1 P E G _ C LK R E Q #
10K pull-down to
GND
100-MHz Gen2 differential clock to PCIe Graphics
device.
A T3 4
AU3 4 PE R N7
Lane 4 GLAN / CARD READER PER P7
AU3 6 AD 4 3
Lane 5 X P E T N7 C L K O U T _ P E G_ A _ N
PEG
AV3 6 AD 4 5
PETP7 C LK OU T _ P E G _A _P
Lane 6 X B G3 4 AN 4
Lane 7 X PE R N8 C L K O U T _ D MI _ N C L K_ EXP_ N 4
B J3 4 AN 2 C L K_ EXP_ P 4
PER P8 C L K O U T _D M I _P
Lane 8 X B G3 6
B J3 6 P E T N8
PETP8 AT1 P C H _ C L K _ D P _N _ R R 26 4 * 10 m i l _ sh o rt
C LK OU T _D P _ N / C LK OU T _ B C L K 1 _ N P C H _ C L K _ D P _P _ R CL K _ D P _ N 4
AT3 R 26 5 * 10 m i l _ sh o rt CL K _ D P _ P 4
3 .3 V 3 .3 V S AK4 8 C L K O U T_ D P _ P / C L K O U T _ B C L K 1 _P
AK4 7 CL K O UT _ P C IE 0 N
CL K O UT _ P C IE 0 P 100-MHz differential clock from PCH to Processor.
R N8 AW 2 4 C L K _ P C IE _ IC H# 2
P C IE CL K RQ 0 # C L K I N _ D MI _ N Connect to PEG_CLK#/PEG_CLK pins of the
1 0 K_ 8 P4 R_ 0 4 P9 B A 24
From CLK BUFFER

P C I E C L K R Q0 # / GP I O 7 3 C L K I N _D M I _P C L K _ P C IE _ IC H 2 processo
1 8 P C I E C L K R Q1 #
2 7 P C I E C L K R Q0 #
3 6 P C I E C L K R Q5 # A M4 3 AP 3
CL K O UT _ P C IE 1 N C L K I N _B C L K _ N C L K _ B U F _ B C LK _N 2
4 5 P E G_ B _ C L K R Q # A M4 5 AP 1
CL K O UT _ P C IE 1 P C L K I N _ B C LK _P C L K _ B U F _ B C LK _P 2
P C IE CL K RQ 1 # U4
P C I E C L K R Q1 # / GP I O 1 8 F18
C L K I N _ D O T _9 6 N C L K _ B U F _ D O T 9 6_ N 2
E1 8
C L K I N _ D OT _ 9 6P C L K _ B U F _ D O T 9 6_ P 2
A M4 7
2 3 CL K _ P C IE _ N E W _ C A RD # CL K O UT _ P C IE 2 N
23 C L K _ P C I E _ N E W _ C A R D A M4 8
CL K O UT _ P C IE 2 P AH 1 3 C3 9 8 2 2 p _5 0 V _ N P O _0 4
C L K IN _ S A T A _ N / CK S S C D_ N C L K_ SATA# 2
R 279 0_04 C L K _ S L O T 2 _O E # N4 AH 1 2 C L K_ SATA 2
2 3 N E W C A R D _ C LK R E Q # P C I E C L K R Q2 # / GP I O 2 0 C L K I N _ S A T A _ P / C K S S C D _P
AH4 2 P4 1
2 3 C L K _ P C I E _ MI N I # CL K O UT _ P C IE 3 N RE F CL K 1 4 IN C L K _ BU F _ RE F 1 4 2
1
AH4 1 R 266
2 3 C LK _P C I E _M I N I CL K O UT _ P C IE 3 P X5
A8 J42 1 M _ 04 X 8 A 0 2 5 0 0 0F G1 H _2 5 M H z
2 3 W L A N _ C LK R E Q # P C I E C L K R Q3 # / GP I O 2 5 C L K I N _ P C I L O OP B A C K C L K _ P C I_ F B 1 8
2
A M5 1 AH 5 1 X T A L 2 5 _I N
2 5 C L K _ P C I E _ GL A N # CL K O UT _ P C IE 4 N X TA L2 5 _ I N
A M5 3 AH 5 3 X T A L 2 5 _O U T C3 9 5 2 2 p _5 0 V _ N P O _0 4
2 5 C L K _ P C I E _ GL A N CL K O UT _ P C IE 4 P X T A L 2 5 _ OU T
L A N _ CL K R E Q # M9 A F 38 X C L K _R C OM P R 87 9 0 . 9_ 1 % _ 0 4 90.9-O ? % pullup
P C I E C L K R Q4 # / GP I O 2 6 X C L K _ R C O MP 1 . 1 V S _V T T to +VccIO
(1.05V, S0 rail)
A J5 0 T45
Clock Flex
A J5 2 CL K O UT _ P C IE 5 N C L K O U T F L E X 0 / GP I O 6 4
CL K O UT _ P C IE 5 P
P C I E C L K R Q5 # H6 P4 3
P C I E C L K R Q5 # / GP I O 4 4 C L K O U T F L E X 1 / GP I O 6 5
AK5 3 T42
AK5 1 CL K O UT _ P E G _ B _ N C L K O U T F L E X 2 / GP I O 6 6
CL K O UT _ P E G _ B _ P
P E G_ B _ C L K R Q# P1 3 N 50
P E G _B _C L K R Q# / G P I O 5 6 C L K O U T F L E X 3 / GP I O 6 7
I b ex P ea k -M _ R e v 0 _ 9
3 .3 V S 2 , 1 0, 1 1 , 1 2 , 1 3 , 1 4 , 1 6, 1 7 , 1 8 , 1 9 , 2 0 , 2 1, 23 , 2 4 , 2 5 , 2 6 , 2 7, 28 , 2 9 , 3 0 , 3 1 , 3 5, 36
1 . 1 V S _ V T T 2 , 4 , 6 , 7 , 1 4 , 1 6 , 19 , 2 0 , 2 1 , 3 4 , 3 5 , 36
3 .3 V 3 , 4 , 12 , 1 4 , 1 6 , 1 8 , 1 9 , 20 , 2 1 , 2 3 , 2 4 , 2 5 , 2 9, 3 0 , 3 1 , 3 3 , 3 4 , 3 5
B - 16 IBEXPEAK - M 2/9
Schematic Diagrams
IBEXPEAK - M 3/9
IBEXPEAK - M (DMI,FDI,GPIO)
U2 0 C
B A 18 FD I _ T XN 0 3
B C2 4 F DI_ R XN 0 BH 1 7
3 D MI _ R XN 0 D M I0 RXN F DI_ R XN 1 FD I _ T XN 1 3
B J2 2 BD 1 6 FD I _ T XN 2 3
3 D MI _ R XN 1 D M I1 RXN F DI_ R XN 2
AW 2 0 BJ 1 6 FD I _ T XN 3 3
3 D MI _ R XN 2 B J2 0 D M I2 RXN F DI_ R XN 3 B A 16
3 D MI _ R XN 3 D M I3 RXN F DI_ R XN 4 FD I _ T XN 4 3
B E 14 FD I _ T XN 5 3
F DI_ R XN 5
B D2 4 B A 14 FD I _ T XN 6 3
3 D MI _ R XP 0 B G2 2 D M I0 RXP F DI_ R XN 6 BC 1 2
3 D MI _ R XP 1 D M I1 RXP F DI_ R XN 7 FD I _ T XN 7 3
BA2 0
3 D MI _ R XP 2 D M I2 RXP
B G2 0 B B 18 FD I _ T XP 0 3
3 D MI _ R XP 3 D M I3 RXP F DI _R XP0 B F 17
F DI _R XP1 FD I _ T XP 1 3
BE2 2 BC 1 6 FD I _ T XP 2 3
3 DM I _ T XN 0 D M I 0 TX N F DI _R XP2
3 DM I _ T XN 1 BF2 1 BG 1 6 FD I _ T XP 3 3
B D2 0 D M I 1 TX N F DI _R XP3 AW 1 6
3 DM I _ T XN 2 D M I 2 TX N F DI _R XP4 FD I _ T XP 4 3
BE1 8 BD 1 4 FD I _ T XP 5 3
3 DM I _ T XN 3 D M I 3 TX N F DI _R XP5
B B 14 FD I _ T XP 6 3
B D2 2 F DI _R XP6 BD 1 2
3 DM I _ T XP 0 D M I 0 TX P F DI _R XP7 FD I _ T XP 7 3
B H2 1
3 DM I _ T XP 1 D M I 1 TX P
3 DM I _ T XP 2 B C2 0
B D1 8 D M I 2 TX P BJ 1 4
3 DM I _ T XP 3 D M I 3 TX P F DI_ IN T F DI_ IN T 3
DMI
FDI
B F 13 F DI_ F S Y N C0 3
R2 5 9 4 9 . 9 _ 1 % _0 4 D MI _ C OM P _ R B H2 5 F D I_ F SY NC 0
1 . 1 V S _V TT D M I _ Z C O MP
BH 1 3 F DI_ F S Y N C1 3
F D I_ F SY NC 1
BF2 5
D M I _ I R C OM P BJ 1 2
F DI_ L S Y NC 0 F DI_ L S Y NC 0 3
BG 1 4
F DI_ L S Y NC 1 F DI_ L S Y NC 1 3
Sheet 16 of 40
FOR RESET SWITCH
IBEXPEAK - M 3/9
3 .3 VS R 11 1 1 0 K_ 0 4 S Y S _ RE S E T # T6 J12 P CI E _ W A K E # P CIE _ W A K E # 2 3 ,2 5
S YS_ R ESET# W A KE#
S Y S _ P W R OK M6 Y 1 P M_ C L K R U N # P M_ C L K R U N # 2 4
S YS _ P W RO K C L K R U N # / GP I O3 2
System Power Management

3 . 3V
S B _ P W RO K B1 7
P W R OK P CIE _ W A K E # R1 2 0 1K _0 4
P M _ MP W R O K K5 P8 S4 _ STATE# S 4_ S T A T E # 2 4 P M_ S L P _ L A N # R1 2 5 *1 0 K _ 0 4
M E P W RO K S U S _ S T A T # / GP I O6 1
S W I# R1 2 8 10 K _ 0 4
R2 9 1 1 0 K_ 0 4 A U X P P W R OK _ R A1 0 F3
L A N_ RS T # S U S C L K / GP I O6 2 S US _ P W R_ A C K
EXT-LAN R2 8 0 10 K _ 0 4
D9 E4 P W R_ BT N # R1 0 9 *1 0 K _ 0 4
4 P M_ D R A M _ P W R GD D R A MP W R O K S L P _ S 5 # / GP I O6 3
A C_ P R E S E N T R1 1 4 10 K _ 0 4
R S MR S T # C1 6 H 7
28 R SM RST # R S M R S T# SL P_ S4 # S U S C # 2 8 ,3 3
R2 9 5 1 0 K_ 0 4
P M_ B A T L O W # R2 9 2 8. 2K _0 4
S US _ P W R_ A C K M1 P1 2 S US B #
2 8 SU S_ PW R _ AC K S US _ P W R_ A C K / G P IO 3 0 SL P_ S3 # SU SB# 2 3 , 2 8, 31 3 . 3V S
P W R_ B T N # P5 K8 P M_ C L K R U N # R2 6 8 8. 2K _0 4
28 P W R _ B T N# P W R B T N# S LP _M #
A C_ PR E SE N T P7 N 2 A L L _S Y S _ P W R G D R1 3 9 10 K _ 0 4
1 8 ,2 8 A C _ P RE S E N T A CP R E S E NT / G P IO 3 1 TP2 3
P M _ B A T L OW # A6 BJ 1 0
B A T L OW # / GP I O 7 2 P MS Y N C H H _ P M_ S Y N C 4
S W I# F1 4 F6 P M_ S LP _L A N #
28 S W I# R I# S LP _L A N #
I b ex P e a k -M _R e v 0 _ 9
3 .3 V
3 .3 V
3 .3 V 3 .3 V R 135 * 1 0m i l _ sh o rt P M _ MP W R O K
U8 D
14
U 8A U 8C 74 L V C 0 8 P W R 140 * 1 0m i l _ sh o rt S B_ P W RO K
14
7 4 L VC0 8 PW U8 B 7 4 L V C 08 P W 12
14
7 4L V C 0 8 P W 9 3 5 V G F X _ V OR E _ P G 11 R 138 * 1 0m i l _ sh o rt S Y S _ P W R OK
14
4 , 36 D E L A Y _ P W R GD
4 8 13
4 , 3 3 , 3 4 1 . 1 V S _ V T T _ P W R GD A L L _ S Y S _ P W R GD
1 6 10
3 3 D D R 1 . 5 V _ P W R GD 3 1 . 1 V S _V TT _ E N 5 R 141
7
SU SB# 2
7
1 0 K_ 0 4
7
A L L _S Y S _ P W R G D 12 , 2 8
7
3 4 1 .1 VS _ V T T _ EN
R 13 7 2K _ 04
H _V TT P W R G D 4
ON
R 13 4
1 K_ 0 4
3 .3 V S 2, 10 , 1 1 , 1 2 , 1 3 , 14 , 1 5 , 1 7 , 1 8 , 1 9, 2 0 , 2 1 , 2 3 , 2 4, 25 , 2 6 , 2 7 , 2 8, 29 , 3 0 , 3 1 , 3 5 , 36
3 .3 V 3, 4, 12 , 1 4 , 1 5 , 1 8, 19 , 2 0 , 2 1 , 2 3 , 24 , 2 5 , 2 9 , 3 0 , 3 1, 3 3 , 3 4 , 3 5
1 . 1 V S _ V T T 2 , 4 , 6 , 7 , 1 4 , 15 , 1 9 , 2 0 , 2 1 , 3 4, 3 5 , 3 6
Schematic Diagrams
IBEXPEAK - M 4/9
IBEXPEAK - M (LVDS,DDI)
U20D
12 BLON T48 L_BKLTEN SDVO_TVCLKI NN BJ46

12 NB_ENAVDD T47 L_VDD_EN SDVO_TVCLKINP BG46
Y48 L_BKLTCTL SDVO_STALL N BJ48
SDVO_STALLP BG48
12 P_DDC_CLK AB48
3. 3VS Y45 L_DDC_ CLK BF45
12 P_DDC_DATA L_DDC_ DATA SDVO_I NTN BH45
R96 *1 0K_04 L_CTRL_CLK AB46 SDVO_INTP
L_CTRL_DATA L_CTRL_CLK
R97 *1 0K_04 V48 L_CTRL_DATA
R83 2.37K_1%_04 LVDS_IBG AP39 T51
LVD_IBG SDVO_CTRLCLK
AP41 T53
LVD_VBG SDVO_CTRL DATA

AT43
AT42 LVD_VREFH BG44
LVD_VREFL DDPB_AUXN BJ44
DDPB_ AUXP
DDPB_HPD AU38
AV53
L VDS
12 LVDS- LCLKN LVDSA_CLK#
AV51 BD42
D isp lay Por t B
SD VO
12 LVDS- LCLKP LVDSA_CLK DDPB_0 N
Sheet 17 of 40 12 LVDS- L0N BB47
BA52
LVDSA_DATA#0
DDPB_0P
DDPB_1 N
BC42
BJ42
BG42
Digi tal Displ ay Inter face

12 LVDS- L1N LVDSA_DATA#1 DDPB_1P
AY48 BB40
IBEXPEAK - M 4/9 12 LVDS- L2N
AV47 LVDSA_DATA#2
LVDSA_DATA#3
DDPB_2 N
DDPB_2P
DDPB_3 N
BA40
AW38
RN5
2. 2K_4P2R_04
12 LVDS- L0P BB48 LVDSA_DATA0 DDPB_3P BA38 3 2 3.3VS
12 LVDS- L1P BA50 LVDSA_DATA1 4 1
12 LVDS- L2P AY49 LVDSA_DATA2
AV48 LVDSA_DATA3 DDPC_CTRLCLK Y49 HDMI _CTRL CLK 13
AB49 HDMI _CTRL DATA 13
DDPC_CTRL DATA
AP48
AP47 LVDSB_CLK# BE44
LVDSB_CLK DDPC_AUXN
DDPC_ AUXP BD44 PCH_DDPC_HPD
AY53 LVDSB_DATA#0 DDPC_HPD AV40
AT49 LVDSB_DATA#1
AU52 BE40 HDMIB_D2BN_C C132 0.1u_10V_X7R_04
EMI
D isp lay Por t C

LVDSB_DATA#2 DDPC_0 N HDMI B_D2BN 13
AT53 LVDSB_DATA#3 DDPC_0P BD40 HDMIB_D2BP_C C133 0.1u_10V_X7R_04 HDMI B_D2BP 1 3
13 DAC_BL UE R105 *15mil_short DAC_BLUE_R BF41 HDMIB_D1BN_C C118 0.1u_10V_X7R_04 HDMI B_D1BN 13
C180 AY51 DDPC_1 N BH41 HDMIB_D1BP_C C119 0.1u_10V_X7R_04
LVDSB_DATA0 DDPC_1P HDMI B_D1BP 1 3
13 DAC_GREEN *33 p_50V_NPO_04R99 *15mil_short DAC_GREEN_R AT48 BD38 HDMIB_D0BN_C C120 0.1u_10V_X7R_04 HDMI B_D0BN 13
C176 AU50 LVDSB_DATA1 DDPC_2 N BC38 HDMIB_D0BP_C C121 0.1u_10V_X7R_04
DAC_RED_R LVDSB_DATA2 DDPC_2P HDMIB_CLKBN_C HDMI B_D0BP 1 3
13 DAC_RED *33 p_50V_NPO_04R91 AT51 LVDSB_DATA3 DDPC_3 N BB36 C122 0.1u_10V_X7R_04 HDMI B_CLKBN 13
C172 *15mil_short BA36 HDMIB_CLKBP_C C123 0.1u_10V_X7R_04
DDPC_3P HDMI B_CLKBP 13
*33 p_50V_NPO_04
R1 04 15 0_1%_04 DAC_BLUE_R AA52 CRT_BLUE DDPD_CTRLCLK U50
R9 8 15 0_1%_04 DAC_GREEN_R AB53 U52
NEAR PCH R9 2 15 0_1%_04 DAC_RED_ R AD53 CRT_GREEN
CRT_RED
DDPD_CTRL DATA 5VS
BC46 Q18
G
DDPD_AUXN
13 DAC_DDCACLK V51 CRT_DDC_CLK DDPD_ AUXP BD46 MTN7002ZHS3
13 DAC_DDCADATA V53 CRT_DDC_DATA DDPD_HPD AT38 PCH_DDPC_HPD S D PORTC_HPD 13
BJ40
D isp lay Por t D

DDPD_0 N
13 DAC_HSYNC Y53 BG40
Y51 CRT_HSYNC DDPD_0P BJ38 R339
13 DAC_VSYNC CRT_VSYNC DDPD_1 N BG38
DDPD_1P BF37 100K_ 04
C RT
DAC_I REF_R DDPD_2 N
R88 1K_1%_04 AD48 DAC_IREF DDPD_2P BH37
AB51 CRT_IRTN DDPD_3 N BE36
DDPD_3P BD36
IbexPeak-M_Rev0_9
Connec t to GND
PCH_DDPC_HPD R342 *0_04 PORTC_HPD
No Conn ect
Ext ernal Gra phics (P CH Integr ated Gra phics Dis able)
Extern al Graphi cs (PCH Integrat ed Graphi cs Disab le)
2,10,11, 12,13,14 ,15,16,1 8,19,20, 21,23,24, 25,26,27, 28,29,30 ,31,35,3 6 3.3VS

2, 13,20,21, 26,27,30 ,31,35,3 6 5VS
Schematic Diagrams
IBEXPEAK - M 5/9
IBEXPEAK - M (PCI,USB,NVRAM)
U2 0E
H40 AY 9
N34 AD 0 NV_ CE#0 BD 1
AD 1 NV_ CE#1
C44 AP1 5
Boot BIOS Strap A38
AD 2
AD 3
NV_ CE#2
NV_ CE#3 BD 8
C36
J34 AD 4 AV9
PCI_GNT#0 PCI_GNT#1 Boot BIOS Location AD 5 NV_ DQS0
A40 BG 8
D45 AD 6 NV_ DQS1
AD 7
E36 AP7
0 0 LPC H48 AD 8 NV_D Q0 / NV_ IO0 AP6
AD 9 NV_D Q1 / NV_ IO1
0 1 Reserved (NAND) E40
AT6
C40 AT9
1 0 PCI M48 AD 11 NV_D Q3 / NV_ IO3 BB1
1 1 SPI M45 AV6
F53 AD 13 NV_D Q5 / NV_ IO5 BB3
M40 AD 14 NV_D Q6 / NV_ IO6 BA4
M43 AD 15 NV_D Q7 / NV_ IO7 BE4
NVRAM
R11 6 *1 K_ 04 PC I_G NT#0 J36 AD 16 NV_D Q8 / NV_ IO8 BB6
K48 AD 17 NV_D Q9 / NV_ IO9 BD 6
R11 8 *1 K_ 04 PC I_G NT#1 F40 AD 18 NV_ DQ1 0 / NV_I O10 BB7
C42 AD 19 NV_ DQ1 1 / NV_I O11 BC 8
K46 AD 20 NV_ DQ1 2 / NV_I O12 BJ 8
M51 AD 21 NV_ DQ1 3 / NV_I O13 BJ 6
J52 AD 22 NV_ DQ1 4 / NV_I O14 BG 6
AD 23 NV_ DQ1 5 / NV_I O15
K51 AD 24
L34 BD 3
F42 AD 25 NV_ AL E AY 6
J40 AD 26 N V_CL E
Understand the RED FONT define AD 27
G46
AD 28 NV_ RCO MP
R12 1 *1 K_04 PC I_ GNT#3
F44
M47
H36
AD 29
AD 30
NV_R COMP AU 2
AV7
R 26 3 3 2.4 _1 %_ 04
Sheet 18 of 40
PCI
AD 31 N V_RB#
J50
G42
H47
C/BE0#
C/BE1#
C/BE2#
NV_W R#0 _RE#
NV_W R#1 _RE#
AY 8
AY 5 IBEXPEAK - M 5/9
G34 AV1 1
C/BE3# N V_WE# _CK0 BF5
3. 3VS IN T_PI RQA# G38 N V_WE# _CK1
IN T_PI RQB# H51 PI RQ A#
PI RQ B#
4 5 INT_PIR QE# IN T_PI RQC # B37 H 18 U SB_ PN0 30
RN2 3 3 6 PC I_ IRD Y# IN T_PI RQD # A44 PI RQ C# USBP0N J 18 USB PORT0
PI RQ D# U SBP0 P U SB_ PP0 30
8.2 K_8P4 R_0 4 2 7 I NT_ PIRQ D# A1 8
PCI_ FRAME# PCI_ REQ# 0 USBP1N U SB_ PN1 30 USB PORT1
1 8 F51 C 18
PC I_ PER R# PCI_ REQ# 1 REQ0# U SBP1 P U SB_ PP1 30
4 5 A46 REQ1# / G PI O5 0 USBP2N N 20 U SB_ PN2 23
RN1 2 3 6 PCI _LO CK# B45 P2 0 U SB_ PP2 23
WLAN
REQ2# / G PI O5 2 U SBP2 P
8.2 K_8P4 R_0 4 2 7 PCI_ DEVSEL# PCI_ REQ# 3 M53 J 20 U SB_ PN3 23
1 8 PC I_ SER R# REQ3# / G PI O5 4 USBP3N L 20 NEW CARD
PCI _REQ #1 PCI_ GN T#0 U SBP3 P U SB_ PP3 23
4 5 F48 F2 0
PC I_ TRD Y# PCI_ GN T#1 GNT0# USBP4N U SB_ PN4 30 USB PORT2
RN2 2 3 6 K45 GNT1# / GPIO 51 U SBP4 P G 20 U SB_ PP4 30
8.2 K_8P4 R_0 4 2 7 I NT_ PIRQ H# BA CKL IG HT CO NTR OL FR OM IG PU/ DG PU DG PU_PWM_SELEC T# F36 A2 0
GNT2# / GPIO 53 USBP5N U SB_ PN5 24
1 8 PCI _REQ #0 PCI_ GN T#3 H53 C 20 U SB_ PP5 24
CCD
GNT3# / GPIO 55 U SBP5 P M22
4 5 I NT_ PIRQ G# IN T_PI RQE# B41 USBP6N N 22
RN2 4 3 6 I NT_ PIRQ C# IN T_PI RQF# K53 PI RQ E# / GPI O2 U SBP6 P B2 1
8.2 K_8P4 R_0 4 2 7 INT_PIR QA# IN T_PI RQG # A36 PI RQ F# / GPI O3 USBP7N D 21
? ? ? ?
PI RQ G# / GPIO 4 U SBP7 P
1 8 PC I_ STOP# IN T_PI RQH # A48 H 22
PI RQ H# / GPIO 5 USBP8N
4 5 INT_PIR QB# J 22
RN2 0 3 6 INT_PIR QF# K6 U SBP8 P E2 2
USB
PC IR ST# USBP9N U SB_ PN9 2 4
8.2 K_8P4 R_0 4 2 7 PCI _REQ #3 F2 2
U SB_ PP9 2 4
3G
1 8DG PU_PW M_SELEC T# PCI_ SERR# E44 U SBP9 P A2 2
SER R# USBP10N
PCI_ PERR# E50 C 22
PER R# USBP10 P
G 24 U SB_ PN11 29
USBP11N H 24 BT
PCI_ IR DY# USBP11 P U SB_ PP1 1 2 9
A42 L 24
H44 IRD Y# USBP12N M24
PAR USBP12 P
PCI_ DEVSEL# F46 A2 4
DEVSEL # USBP13N
PCI_ FRAME# C46 C 24
FR AME# USBP13 P
PCI_ LO CK# D49
PL OCK# B2 5 USB_ BI AS R 29 6 2 2.6 _1 %_ 06
PCI_ STOP# D41 USBRBI AS#
STOP#
PCI_ TR DY# C48 D 25
TRD Y# U SBR BIAS
M7
28 PME# PME# N 16
PIN PL T_RS T# to Buf fer PLT_ RST# D5 OC 0# / GPI O59 J 16 USB_ OC# 23
USB_O C#0 1 30
2 4 PLT_RST# PL TR ST# OC 1# / GPI O40 USB_O C#2 3 23 3. 3V
F1 6 USB_ OC# 45
OC 2# / GPI O41 USB_ OC# 67
N52 L 16
CL K_ PCI_ FB_R CLKOU T_ PCI0 OC 3# / GPI O42 USB_ OC# 89
1 5 CL K_ PCI _FB R1 23 22_ 04 P53 E1 4 USB_O C#8 9 15
R1 19 22_ 04 CL K_ PCI_ KBC_R P46 CLKOU T_ PCI1 OC 4# / GPI O43 G 16 USB_ OC# 101 1
2 8 PCLK_ KBC CLKOU T_ PCI2 O C5 # / G PIO9
P51 F1 2 USB_ OC# 121 3 R 12 4 1 0K_0 4
R3 43 *22_ 04 PC LK_TPM_PC H P48 CLKOU T_ PCI3 OC 6# / GPI O10 T15 R 11 0 1 0K_0 4
2 4 PCLK_ TPM CLKOU T_ PCI4 OC 7# / GPI O14 GPIO 14 R 11 3 *0_ 04
AC_ PRESENT 1 6,2 8
I bex Peak -M_Re v 0_9
3.3 V
3 .3 VS
USB_OC #6 7 5 4
C1 91 *0. 1u _10 V_X7 R_ 04 USB_OC #1 011 6 3 RN1 4
USB_OC #4 5 7 2 10K_ 8P4R _04
5
U6 PCH _UPEK_I NI T# 8 1
PL T_R ST# 1 MC74 VHC1 G0 8DFT1G 15 PC H_ UPEK_ IN IT#
4 BUF_ PL T_ RST# 4 ,2 3, 25, 28
2
R 117
3
1 00K_ 04
2, 10, 11 ,12 ,1 3,1 4, 15, 16 ,1 7,1 9, 20, 21 ,23 ,2 4, 25, 26 ,27 ,2 8,2 9, 30, 31 ,3 5,3 6 3. 3VS
3 ,4, 12 ,1 4,1 5, 16, 19 ,20 ,2 1, 23, 24 ,25 ,2 9,3 0, 31, 33 ,3 4,3 5 3. 3V
Schematic Diagrams
IBEXPEAK - M 6/9
IBEXPEAK - M (GPIO,VSS_NCTF,RSVD)
U20F
EDP_CARD_DET# Y3 AH45
BMBUSY# / GPIO0 CLKOUT_PCIE6N
0213 S_GPIO CHANGE TO EDP_CARD_DET# AH46
SMI# C38 CLKOUT_PCIE6P
R270 1K_1%_04 EDP_CARD_DET# 28 SMI# TACH1 / GPIO1
3.3VS DGPU_HPD_INTR#
DGPU HDP (NV CONTROL BYSELF) D37
TACH2 / GPIO6
MISC
AF48
R269 SCI# J32 CLKOUT_PCIE7N AF47
28 SCI# TACH3 / GPIO7 CLKOUT_PCIE7P
*0_04 PCH_MUTE# F10 R272 10
K_04 3.3VS
27 PCH_
MUTE# GPIO8
R349 *10K_04 K9 U2
3.3V LAN_PHY_PWR_CTRL / GPIO12 A20GAT
E GA20 28
HOST_ALERT
#1 T7
BIOS_
REC GPIO15
3.3VS R101 10K_04
R350 *10K_04 AA2 AM3
3.3VS SATA4GP / GPIO16 CLKOUT_
BCLK0_N / CLKOUT_PCIE8N BCLK_CPU_
N 4
B IO S R E CO VE R Y R102 R351 *10K_04 F38 AM1 R254 *10K_04

3.3VS TACH0 / GPIO1
7 CLKOUT_BCLK0_P/ CLKOUT
_PCIE8
P BCLK_CPU_
P 4 1.1VS_VT
T
D IS A BL E -- -- N O S TU FF (D E FA U LT ) BIOS_
REC H_PECI_R
*0_04 Y7 BG10 R258 0_04
GPIO
SCLOCK / GPIO22 PECI H_PECI 4,28
E NA B LE - -- -- S TU F F
Sheet 19 of 40 12 SB_BLON
SB_BLON
H10
AB12
MEM_LED / G
GPIO27
PIO24 RCIN#
PROCPWRGD
T1
BE10
R274 10K_04
3.3VS
KBC_RST# 28
H_CPUPWRGD 4
R277 *10K_04 CRB_SV_DET
IBEXPEAK - M 6/9
CPU
3.3VS
SPI_CS#2 V13 BD10 R257 56_04 R253 56_04
GPIO28 THRMTRI P# 1.1VS_VTT
R276 ST
P_PCI # M11
C RB / SV DE T EC T ST
P_PCI # / GPIO34 H_THRMTRIP# 4
N O S TU F F [ DE TE C T] 1
00K_04 GPIO35 V6 Connected to PCH (THRMTRIP#)
SATACL
KREQ# / GPIO35
Routing guidelines available in
3.3VS R352 *1K_04 AB7 BA22 Calpella Design Guide.
SATA2GP / GPIO36 TP1
DGPU_PRSNT# AB13 AW22 NOTE: CRB uses a 54.9 O ? %
SATA3GP / GPIO37 TP2 series resistor and 56-O pull-up.
3.3VS R95 10K_04 SV_SET_UP
MFG_MODE V3 BB22
SL
OAD / GPIO38 TP3
R100 CRB_SV_DET P3 AY45
SDATAOUT0 / GPIO39 TP4
*0_04 H3 AY46
PCIECLKRQ6# / GPIO45 TP5
DRAMRST_CTRL F1 AV43
4, 9 DRAMRST_CTRL PCIECLKRQ7# / GPIO46 TP6
SV_SET_UP AB6 AV45
SDATAOUT1 / GPIO48 TP7
R267 *0_04 CRIT_
TEMP_REP#_R AA4 AF13
3.3V 3 CRIT_TEMP_REP# SATA5GP / GPIO49 TP8
R126 1
0K_
04 PCH_GPIO57 F8 M18
GPIO57 TP9
R107 1K_04 HOST_ALERT
#1 N18
TP10
RN9 A4 AJ24
VSS_NCTF_1 TP11
10K_8P4R_04 A49
RSVD
1 8 PCH_MUTE# A5 VSS_NCTF_2 AK41
2 7 SPI_CS#2 A50 VSS_NCTF_3 TP12
3 6 DRAMRST _CTRL A52 VSS_NCTF_4 AK42
VSS_NCTF_5 TP13
4 5 A53
VSS_NCTF_6
B2 M32
B4 VSS_NCTF_7 TP14
B52 VSS_NCTF_8 N32
VSS_NCTF_9 TP15
B53
3.3VS VSS_NCTF_10
BE1 M30
RN21 BE53 VSS_NCTF_11 TP16
10K_8P4R_04 BF1 VSS_NCTF_12 N30
SCI# VSS_NCTF_13 TP17
1 8 BF53
SMI# VSS_NCTF_14
2 7 BH1 H12
3 6 MFG_MODE BH2 VSS_NCTF_15 TP18
NCTF
4 5 STP_PCI# BH52 VSS_NCTF_16 AA23
VSS_NCTF_17 TP19
BH53
VSS_NCTF_18
RN4 BJ1 AB45
10K_8P4R_04 BJ2 VSS_NCTF_19 NC_1
1 8 DGPU_HPD_ I NTR# BJ4 VSS_NCTF_20 AB38
VSS_NCTF_21 NC_2
2 7 CRIT_TEMP_REP#_R BJ49
DGPU_PRSNT# VSS_NCTF_22
3 6 BJ5 AB42
GPIO35 VSS_NCTF_23 NC_3
4 5 BJ50
BJ52 VSS_NCTF_24 AB41
BJ53 VSS_NCTF_25 NC_4
VSS_NCTF_26
D1 T39
VSS_NCTF_27 NC_5
D2
D53 VSS_NCTF_28
R103 *10K_04 DGPU_PRSNT# E1 VSS_NCTF_29 P6
VSS_NCTF_30 INIT3_3V#
E53
VSS_NCTF_31
C10
LOW: DGPU PRESENT TP24
I bexPeak-M_Rev0_9
2,4,6,7,14,15,16
, 20,21,34,35,36 1.1VS_VTT
3,4,12,14, 1
5,16,18,20,21,23,24,25,29, 30,31,33,34,35 3.3V
2
, 10,11,12,13,14,15,16,17, 1
8,20,21,23,24,25,26,27,28, 29,30,31,35,36 3.3VS
Schematic Diagrams
IBEXPEAK - M 7/9
IBEXPEAK - M (POWER)
3 .3 V S
R 90 *0 _ 0 6
1 .1 V S _ V T T V C C A _D A C _ 3 . 3 V S L12 5 VS
U 2 0G POWER H C B 1 6 0 8K F -1 2 1 T 25 U5
AB 2 4
VC CC O RE [1 ] V C CA DA C [1 ]
AE5 0 . 4
OU T IN
5
AB 2 6
C 182 C1 5 7 AB 2 8 VC CC O RE [2 ] AE5 2 C 400 C 399 C 47 0 C1 5 1 C 139 C 152 R 80 C 15 6
AD 2 6 VC CC O RE [3 ] V C CA DA C [2 ]
VC CC O RE [4 ]
0 . 1 u _ 1 0 V _ X 7 R _ 04
2 2 u _6 . 3 V _X 5 R _ 0 8
0 . 1 u _ 1 0 V _ X 7 R _ 04
2 2 u _ 6 . 3 V _ X 5 R _ 08
1 u _ 6. 3V _ X 5 R _ 0 4
1 0 u _ 6 .3 V _ X 5 R_ 0 6 1 u _ 6 . 3 V _ X 5R _ 0 4 AD 2 8 AF5 3 0 . 0 1 u _ 5 0 V _ X 7R _ 0 4 1 0u _ 6 . 3 V _ X 5 R _0 6 1 7 .4 K _ 1 % _ 0 4 1
CRT
VC CC O RE [5 ] V S S A _ DA C [1 ] SH D N
AF 2 6 3 2
AF 2 8 VC CC O RE [6 ] AF5 1 A DJ G N D
VCC CORE
AF 3 0 VC CC O RE [7 ] V S S A _ DA C [2 ] R 81 S C 1 5 63 I S K -3 . 0 T R T
VC CC O RE [8 ]
AF 3 1
VC CC O RE [9 ]
AH 2 6 1 0 K_ 1 % _ 0 4
VC CC O RE [ 1 0]
AH 2 8 3 . 3 V S _ V C C A _ LV D 3. 3V S
AH 3 0 VC CC O RE [ 1 1]
VC CC O RE [ 1 2]
AH 3 1 A H 38 R8 6 *1 5 m i l _ sh o rt _ 0 6
VC CC O RE [ 1 3] V CC A L V D S
AJ 3 0
AJ 3 1 VC CC O RE [ 1 4] A H 39 C 1 62
1 .1 VS_ VT T VC CC O RE [ 1 5] V SSA_ L VD S
1 0 u _ 6. 3 V _X 5 R _ 0 6
AP4 3 1 . 8 V S _ V C C TX _ L V D 1 .8 VS
1 .1 VS_ VC C APL L _ EXP

VC
VC
VC
CT X _ L V D
CT X _ L V D
CT X _ L V D
S[1 ]
S[2 ]
S[3 ]
AP4 5
AT4 6
L11
H C B 1 6 0 8K F -1 2 1 T 25
.
Sheet 20 of 40
LVDS
AK 2 4 AT4 5
V C C I O[ 2 4 ] VC CT X _ L V D S[4 ]
L29
* B K P 10 0 5 H S 1 2 1 _0 4
. BJ 2 4
V C CA PL L E X P
AB3 4
C1 4 6
0 . 0 1 u_ 5 0 V _ X 7 R _ 0 4
C 14 5
0 . 0 1 u _5 0 V _ X 7 R _ 04
C 14 1
1 0 u _6 . 3 V _X 5 R _ 0 6
C 140
1 0 u _ 6 . 3 V _ X 5R _ 0 6
IBEXPEAK - M 7/9
V C C3 _ 3 [2 ]
C 378
AN 2 0 AB3 5
1 0 u _ 6 .3 V _ X 5 R_ 0 6 AN 2 2 VC CI O[ 2 5 ] V C C3 _ 3 [3 ]
VC CI O[ 2 6 ]
HVCMOS
AN 2 3 A D 35 3. 3V S
VC CI O[ 2 7 ] V C C3 _ 3 [4 ]
AN 2 4
AN 2 6 VC CI O[ 2 8 ]
AN 2 8 VC CI O[ 2 9 ]
1 .1 VS_ VT T VC CI O[ 3 0 ]
BJ 2 6 C1 6 5
VC CI O[ 3 1 ]
BJ 2 8
AT2 6 VC CI O[ 3 2 ] 0 . 1 u _1 0 V _ X 7 R _0 4
AT2 8 VC CI O[ 3 3 ]
VC CI O[ 3 4 ]
C 38 1 C1 6 6 C 167 C 142 C1 4 7 AU 2 6
VC CI O[ 3 5 ] 1. 5V S _ 1 . 8 V S
AU 2 8
1 0 u _6 . 3 V _X 5 R _ 0 6 1 u_ 6 . 3 V _ X 5 R _ 04 1 u _ 6 .3 V _ X 5 R_ 0 4 1 u _ 6 . 3 V _ X 5R _ 0 4 1 u _6 . 3 V _X 5 R _ 0 4 AV 2 6 VC CI O[ 3 6 ]
AV 2 8 VC CI O[ 3 7 ] AT2 4
VC CI O[ 3 8 ] VC C V RM [2 ]
AW 2 6
VC CI O[ 3 9 ]
AW 2 8
BA 2 6 VC CI O[ 4 0 ] AT1 6 1. 1V S _ V T T
DMI
BA 2 8 VC CI O[ 4 1 ] V C C DM I[ 1 ]
VC CI O[ 4 2 ]
BB 2 6 A U 16
VC CI O[ 4 3 ] V C C DM I[ 2 ]
BB 2 8
BC 2 6 VC CI O[ 4 4 ] C 1 34
BC 2 8 VC CI O[ 4 5 ]
PCI E*
VC CI O[ 4 6 ]
BD 2 6 1u _ 6 . 3 V _ X 5 R _ 0 4
VC CI O[ 4 7 ]
BD 2 8
BE 2 6 VC CI O[ 4 8 ] A M 16
BE 2 8 VC CI O[ 4 9 ] VC C PN A ND [1 ] AK1 6
VC CI O[ 5 0 ] VC C PN A ND [2 ] V _ N V R A M_ V C C Q 1 .8 V S 3 .3 V S
BG 2 6 AK2 0
VC CI O[ 5 1 ] VC C PN A ND [3 ]
BG 2 8 AK1 9
BH 2 7 VC CI O[ 5 2 ] VC C PN A ND [4 ] AK1 5 R 76 * 0 _0 4
VC CI O[ 5 3 ] VC C PN A ND [5 ] AK1 3
VC C PN A ND [6 ]
AN 3 0 A M 12 C1 5 8 R 75 * 1 5 m il _ s h o rt _ 0 6
V C C I O[ 5 4 ] VC C PN A ND [7 ]
AN 3 1 A M 13
NAND / SPI
1 . 5 V S _ 1. 8V S 3 .3 V S V C C I O[ 5 5 ] VC C PN A ND [8 ] A M 15 0 . 1 u _1 0 V _ X 7 R _0 4
VC C PN A ND [9 ]
AN 3 5
1 .1 V S _ V T T 1 .1 V S _ VC C A P L L _ F DI V C C3 _ 3 [1 ]
L28 AT2 2
V C CV RM [1 ] 3 .3 V S 3 .3 V
* H C B 1 0 0 5 K F - 12 1 T 2 0
BJ 1 8 AM 8 V C C ME 3 . 3 V
V C CF DI P L L V C C ME 3 _ 3 [ 1 ] AM 9 R 79 *1 5 m i l_ s h o rt _ 0 6
V C C ME 3 _ 3 [ 2 ]
C3 7 7 AM 2 3 AP1 1
FDI
V C C I O[ 1 ] V C C ME 3 _ 3 [ 3 ]
AP9 R 82 * 0_04
*1 0 u _ 6 . 3 V _ X 5 R _ 0 6 V C C ME 3 _ 3 [ 4 ]
C 14 4
I b e x P e a k -M_ R e v 0 _ 9 0 . 1 u _ 10 V _X 7 R _ 0 4
1 .1 V S _ V T T 1 . 1 V S _V C C D P L L _F D I
R2 5 5 * 1 5 m il _ s h o rt _ 0 6
3, 4, 12 , 1 4 , 1 5 , 1 6 , 1 8 , 1 9 , 2 1 , 2 3, 24 , 2 5 , 2 9 , 3 0 , 3 1 , 3 3 , 3 4 , 3 5 3 .3 V
2 3 ,3 1 ,3 6 1 .5 V S
2 , 1 3, 17 , 2 1 , 2 6 , 2 7 , 3 0 , 3 1 , 3 5 , 3 6 5 VS
21 1 .5 V S _ 1 .8 V S
7 ,3 3 1 .8 V S
2 , 1 0 , 1 1 , 1 2 , 1 3 , 1 4 , 1 5, 16 , 1 7 , 1 8 , 1 9 , 2 1 , 2 3 , 2 4 , 2 5, 26 , 2 7 , 2 8 , 2 9 , 3 0 , 3 1 , 3 5 , 3 6 3 .3 V S
2, 4, 6, 7, 14 , 1 5 , 1 6 , 1 9 , 2 1 , 3 4 , 3 5 , 3 6 1 .1 V S _ VT T
1 .5 V S 1. 8V S 1 .5 V S _ 1 .8 V S
R 256 *1 5 m i l _s h o rt _ 0 6
R 252 *0 _ 0 4
Schematic Diagrams
IBEXPEAK - M 8/9
V ol ta ge Ra il V ol tag e S0 Ic cm ax Cu rr en t (A)
IBEXPEAK - M (POWER) V _C PU _I O
V 5R EF
1. 1/1 .0 5 < 1 ( mA )
5 < 1 ( mA )
V 5R EF _S us 5 < 1 ( mA )
L32 1. 1 V S _ V C C A _ C L K U2 0 J PO WE R 1. 1 V S _ V T T
V cc 3_ 3 3. 3 0.3 57
*H C B 1 0 0 5K F -12 1 T 20 52mA
1 .1 VS _ V T T A P 51 V2 4 V cc AC lk 1. 05 0.0 52
VC CAC L K[1 ] VC CIO [5 ]
V2 6
C 3 91 C 39 2 A P 53 VC CIO [6 ] Y2 4 C 15 3 V cc AD AC 3. 3 0.0 69
VC CAC L K[2 ] VC CIO [7 ]
Y2 6 V cc AD PL LA 1. 05 0.0 68
1 0 u _6 . 3 V _ X 5R _0 6 * 0. 1 u _ 10 V _ X 5 R _ 04 VC CIO [8 ] 1 u _6 . 3 V _ X 5R _0 4
A F 23 V2 8 V cc AD PL LB 1. 05 0.0 69
V C C L A N [ 1] V C C S U S 3_ 3 [ 1 ] U2 8 3 .3 V
320mA V C C S U S 3_ 3 [ 2 ] V cc ap ll EXP 1. 05 0.0 40
1 . 1 V S _ V TT A F 24 U2 6 142.6mA
V C C L A N [ 2] V C C S U S 3_ 3 [ 3 ] U2 4
V C C S U S 3_ 3 [ 4 ] V cc Co re 1. 05 1.4 32
C 1 49 P2 8
T P _ P C H _V C C D S W Y 20 V C C S U S 3_ 3 [ 5 ] P2 6 C 18 7 V cc DM I 1. 05 0.0 58
1 u _ 6. 3 V _ X 5 R _ 04 D CP S U S B Y P V C C S U S 3_ 3 [ 6 ] N2 8
V C C S U S 3_ 3 [ 7 ] V cc DM I 1. 1 0.0 61
C 17 8 N2 6 0 . 1 u_ 1 0 V _ X7 R _ 0 4
A D 38 V C C S U S 3_ 3 [ 8 ] M2 8 V cc FD IP LL 1. 05 0.0 37
0 . 1 u _1 0 V _ X7 R _0 4 VC CM E[1 ] V C C S U S 3_ 3 [ 9 ] M2 6
A D 39 V C C S U S 3 _3 [ 1 0 ] L 28 V cc IO 1. 05 3.0 62
VC CM E[2 ] V C C S U S 3 _3 [ 1 1 ] L 26
1849mA V cc LA N 1. 05 0.3 20
V C C S U S 3 _3 [ 1 2 ]
USB
A D 41 J 28
1 . 1 V S _ V TT VC CM E[3 ] V C C S U S 3 _3 [ 1 3 ] 3. 3 V _ V C C P U S B V cc ME 1. 05 1.8 49
J 26
C 3 79 C 15 4 A F 43 V C C S U S 3 _3 [ 1 4 ] H2 8
VC CM E[4 ] V C C S U S 3 _3 [ 1 5 ] V cc ME 3_ 3 3. 3 0.0 85
H2 6 R 10 6 * 15 m i _l s ho rt _ 0 6
2 2 u _6 . 3 V _ X 5R _0 8 1 u _ 6. 3 V _ X 5R _ 04 A F 41 V C C S U S 3 _3 [ 1 6 ] G2 8
VC CM E[5 ] V C C S U S 3 _3 [ 1 7 ] V cc pN AN D 1. 8 0.1 56
G2 6 C 18 4
A F 42 V C C S U S 3 _3 [ 1 8 ] F28 V cc RT C 3. 3 2 ( mA )
VC CM E[6 ] V C C S U S 3 _3 [ 1 9 ]
F26 0 . 1 u_ 1 0 V _ X7 R _ 0 4 V cc SA TA PLL 1. 05 0.0 31
V 39 V C C S U S 3 _3 [ 2 0 ] E2 8
Sheet 21 of 40 VC CM E[7 ] V C C S U S 3 _3 [ 2 1 ]
V C C S U S 3 _3 [ 2 2 ]
E2 6 V cc Su s3 _3 3. 3 0.1 63
Cl oc k a nd M is ce ll an eo us
C 3 80 C 14 8 V 41 C2 8
VC CM E[8 ] V C C S U S 3 _3 [ 2 3 ] V cc Su sH DA 3. 3 0.0 06
C2 6 1 . 1 V S _ V TT
V C C S U S 3 _3 [ 2 4 ]
IBEXPEAK - M 8/9 2 2 u _6 . 3 V _ X 5R _0 8 1 u _ 6. 3 V _ X 5R _ 04 V 42
Y 39
VC CM E[9 ]
V C C M E [ 1 0]
V C C S U S 3 _3 [ 2 5 ]
V C C S U S 3 _3 [ 2 6 ]
V C C S U S 3 _3 [ 2 7 ]
B2 7
A2 8
A2 6 5 V _ P C H _V C C 5 R E F S U S
D 11 R B 5 5 1V 3 0
V cc VR M
V cc VR M
1. 8/1 .5
1. 05
0.1 96
< 1 ( mA )
V cc AL VD S 3. 3 < 1 ( mA )
Y 41 U2 3 C A
V C C M E [ 1 1] V C C S U S 3 _3 [ 2 8 ] 3 .3 V V cc TX _L VDS 1. 8 0.0 59
Y 42 V2 3 R1 2 2
1 .1 V S_ VT T V C C M E [ 1 2] V C C I O[ 5 6 ] 5V
C 1 83 0 . 1u _ 1 0V _X 7 R _ 0 4 1 0 0_ 1 % _0 4
L 31 1 . 1V S _V C C A _ A _ D P L F24 C 18 8
V 5 REF _ S U S
H C B 1 00 5 K F -1 2 1T 2 0
V CCR T CE X T V9 1 u _6 . 3 V _ X5 R _0 4 D1 0 R B 5 51 V 3 0
D CP R T C V C C5 RE F C A 3 . 3V S
C3 9 3 C 3 89 1 . 5 V S _ 1. 8 V S
+ C3 9 4 R2 6 0 K4 9 R 1 15 1 00 _ 1 %_ 0 4 5V S
22 u _ 6. 3 V _ X 5R _ 08 1u _ 6. 3V _ X 5 R _ 0 4 A U 24 V 5 RE F
68mA V C C V R M[ 3 ]
*2 2 0u _ 4 V _V _B *0 _ 0 4 C1 8 9
PCI /G PI O/ LP C
L 30 J 38 3 .3 VS
1 . 1 V S _ V C C A _B _D P L V C C 3_ 3 [ 8 ]
H C B 1 00 5 K F -1 2 1T 2 0 69mA B B 51 1 u_ 6 . 3 V _ X5 R _ 0 4
B B 53 V C C A D P L LA [ 1] L 38 C 17 5
V C C A D P L LA [ 2] V C C 3_ 3 [ 9 ]
C3 8 6 C 3 85 M3 6 0 . 1 u_ 1 0 V _ X7 R _ 0 4
V C C 3 _3 [ 1 0 ]
+ C3 9 0 B D 51
22 u _ 6. 3 V _ X 5R _ 08 1u _ 6. 3V _ X 5 R _ 0 4 B D 53 V C C A D P L LB [ 1] N3 6
V C C A D P L LB [ 2] V C C 3 _3 [ 1 1 ]
*2 2 0u _ 4 V _V _B
C1 6 0 1 u _ 6. 3 V _ X 5R _ 04 A H 23 P3 6 3 .3 VS
V C C I O [ 2 1] V C C 3 _3 [ 1 2 ]
A J 35
A H 35 V C C I O [ 2 2] U3 5 C 18 6
V C C I O [ 2 3] V C C 3 _3 [ 1 3 ]
C1 3 8 1 u _ 6. 3 V _ X 5R _ 04 A F 34 0 . 1 u_ 1 0 V _ X7 R _ 0 4
VC CIO [2 ] A D1 3
VCCIO 3062mA V C C 3 _3 [ 1 4 ]
1 .1 VS _ V T T A H 34
VC CIO [3 ] L33
C1 6 3 1 u _ 6. 3 V _ X 5R _ 04 A F 32 1. 1 V S _ V C C A P L L *H C B 1 0 0 5K F -12 1 T 20
VC CIO [4 ] AK3
V C CS A T A P L L [1 ] 1 .1 VS _ V T T
V 12 AK1
D CP S S T V C CS A T A P L L [2 ] C 39 6 C 39 7
C 1 81 0 . 1u _ 1 0V _X 7 R _ 0 4 V CCS S T
* 1u _ 6 . 3V _ X 5 R _ 0 4 *1 0 u _6 . 3 V _ X 5R _ 06
C 1 79 0 . 1u _ 1 0V _X 7 R _ 0 4 1 .1 V _ INT _ V CC S US Y 22
D CP S U S A H2 2
V C CIO [9 ]
20.4mA
3. 3 V P 18 A T 20 1. 5V S _ 1 . 8 V S
V C C S U S 3 _3 [ 2 9 ] V CC V RM [4 ]
C 19 4 U 19
V C C S U S 3 _3 [ 3 0 ] A H1 9
SATA
V C C I O[ 1 0 ]
PC I/ GPI O/ LP C
0 . 1 u _1 0 V _ X7 R _0 4 U 20
V C C S U S 3 _3 [ 3 1 ] A D2 0
V C C I O[ 1 1 ]
U 22
V C C S U S 3 _3 [ 3 2 ] AF2 2 1. 1 V S _ V T T
V C C I O[ 1 2 ]
357mA A D1 9
VCC I O[ 1 3 ]
3. 3 V S V 15 AF2 0
V C C 3 _ 3 [ 5] VCC I O[ 1 4 ] AF1 9 C 17 3
VCC I O[ 1 5 ]
C 18 5 V 16 A H2 0
V C C 3 _ 3 [ 6] VCC I O[ 1 6 ] 1 u _6 . 3 V _ X 5R _0 4
14 RT CV CC
0 . 1 u _1 0 V _ X7 R _0 4 Y 16 AB1 9 2, 1 0 , 1 1, 1 2 , 1 3, 14 , 1 5 , 16 , 1 7 , 18 , 1 9 , 20 , 2 3 , 2 4, 2 5 , 2 6, 2 7 , 2 8, 2 9 , 3 0, 31 , 3 5 , 36 3 .3 V S
V C C 3 _ 3 [ 7] VCC I O[ 1 7 ] AB2 0
VCC I O[ 1 8 ] 20 1 . 5 V S _ 1. 8 V S
AB2 2 2, 1 3 , 1 7, 2 0 , 2 6, 2 7 , 3 0, 31 , 3 5 , 36 5 VS
VCC I O[ 1 9 ] A D2 2
<1mA VCC I O[ 2 0 ] 4 , 9 , 1 0, 1 1 , 2 3, 2 7 , 2 9, 31 , 3 3 , 36 1 .5 V
1 . 1 V S _ V TT A T 18 2 4, 2 7 , 3 0, 31 , 3 3 , 34 5V
V _ C P U _ I O[ 1 ] AA3 4
V C C ME [ 1 3 ] 1 . 1V S _V T T 3 , 4 , 12 , 1 4 , 15 , 1 6 , 18 , 1 9 , 2 0, 2 3 , 2 4, 2 5 , 2 9, 3 0 , 3 1, 33 , 3 4 , 35 3 .3 V
CP U
C1 5 0 C 1 43 C 16 8 Y3 4 2, 4 , 6 , 7 , 1 4, 1 5 , 1 6, 1 9 , 2 0, 34 , 3 5 , 36 1 . 1 V S _ V TT
A U 18 V C C ME [ 1 4 ] Y3 5
V _ C P U _ I O[ 2 ] V C C ME [ 1 5 ]
1 u _6 . 3 V _ X5 R _0 4 0 . 1 u _1 0 V _ X 7R _0 4 0 . 1 u _1 0 V _ X7 R _0 4 AA3 5
V C C ME [ 1 6 ] 1. 5 V _ V C C S U S H D A 1 .5 V 3 .3 V
2mA A 12 L 30 R 12 7 * 15 m i _l s ho rt _ 0 6
RT C V CC
RT C
VC CR T C V C CS U S HD A
C 1 92 C 19 3 HDA C 19 5 R 12 9 *0 _ 04
I be x P e a k-M _R e v 0 _9
0 . 1 u _1 0 V _ X 7R _0 4 0 . 1 u _1 0 V _ X7 R _0 4 1 u _ 6. 3 V _ X 5R _ 04
Schematic Diagrams
IBEXPEAK - M 9/9
U 20I
IBEXPEAK - M (GND) AY 7
B 11
B 15
VS S[ 1 59 ]
VS S[ 1 60 ]
V SS [ 2 59 ]
V SS [ 2 60 ]
H 49
H5
J 24
B 19 VS S[ 1 61 ] V SS [ 2 61 ] K 11
B 23 VS S[ 1 62 ] V SS [ 2 62 ] K 43
B 31 VS S[ 1 63 ] V SS [ 2 63 ] K 47
B 35 VS S[ 1 64 ] V SS [ 2 64 ] K7
B 39 VS S[ 1 65 ] V SS [ 2 65 ] L 14
B 43 VS S[ 1 66 ] V SS [ 2 66 ] L 18
B 47 VS S[ 1 67 ] V SS [ 2 67 ] L2
VS S[ 1 68 ] V SS [ 2 68 ]
B7 L 22
VS S[ 1 69 ] V SS [ 2 69 ]
U 20 H BG 1 2 L 32
VS S[ 1 70 ] V SS [ 2 70 ]
AB 1 6 B B 12 L 36
VS S [0 ] VS S[ 1 71 ] V SS [ 2 71 ]
B B 16 L 40
AA 1 9 AK 3 0 B B 20 VS S[ 1 72 ] V SS [ 2 72 ] L 52
AA 2 0 VS S [1 ] VS S[ 8 0] AK 3 1 B B 24 VS S[ 1 73 ] V SS [ 2 73 ] M 12
A M1 9 VS S [3 ] VS S[ 8 2] AK 3 4 B B 34 VS S[ 1 75 ] V SS [ 2 75 ] M 20
AA 2 4 VS S [4 ] VS S[ 8 3] AK 3 5 B B 38 VS S[ 1 76 ] V SS [ 2 76 ] N 38
VS S [7 ] VS S[ 8 6] VS S[ 1 79 ] V SS [ 2 79 ]
AA 3 0 AK 4 6 BB5 M 42
VS S [8 ] VS S[ 8 7] VS S[ 1 80 ] V SS [ 2 80 ]
AA 3 1 AK 4 9 BC 1 0 M 46
VS S [9 ] VS S[ 8 8] VS S[ 1 81 ] V SS [ 2 81 ]
AA 3 2 AK 5 BC 1 4 M 49
VS S [1 0 ] VS S[ 8 9] VS S[ 1 82 ] V SS [ 2 82 ]
AB 1 1 AK 8 BC 1 8 M5
VS S [1 1 ] VS S[ 9 0] VS S[ 1 83 ] V SS [ 2 83 ]
AB 1 5 AL 2 BC 2 M8
AB 2 3 VS S [1 2 ] VS S[ 9 1] AL 5 2 BC 2 2 VS S[ 1 84 ] V SS [ 2 84 ] N 24
AB 3 0 VS S [1 3 ] VS S[ 9 2] AM1 1 BC 3 2 VS S[ 1 85 ] V SS [ 2 85 ] P 11
AB 3 1 VS S [1 4 ] VS S[ 9 3] BB 4 4 BC 3 6 VS S[ 1 86 ] V SS [ 2 86 ] A D 15
AB 3 2 VS S [1 5 ] VS S[ 9 4] AD 2 4 BC 4 0 VS S[ 1 87 ] V SS [ 2 87 ] P 22
VS S [1 8 ] VS S[ 9 7] VS S[ 1 90 ] V SS [ 2 90 ]
AB 4 7
AB 5
AB 8
VS S [1 9 ]
VS S [2 0 ]
VS S [2 1 ]
VS S[ 9 8]
VS S[ 9 9]
VS S[ 1 0 0]
AM2 4
AM2 6
AM2 8
BH 9
BD 4 8
BD 4 9
VS S[ 1 91 ]
VS S[ 1 92 ]
VS S[ 1 93 ]
V SS [ 2 91 ]
V SS [ 2 92 ]
V SS [ 2 93 ]
P 34
P 42
P 45
Sheet 22 of 40
A C2 BA 4 2 BD 5 P 47
A C 52
A D 11
A D 12
VS S [2 2 ]
VS S [2 3 ]
VS S [2 4 ]
VS S[ 1 0 1]
VS S[ 1 0 2]
VS S[ 1 0 3]
AM3 0
AM3 1
AM3 2
B E 12
B E 16
B E 20
VS S[ 1 94 ]
VS S[ 1 95 ]
VS S[ 1 96 ]
V SS [ 2 94 ]
V SS [ 2 95 ]
V SS [ 2 96 ]
R2
R 52
T12
IBEXPEAK - M 9/9
A D 16 VS S [2 5 ] VS S[ 1 0 4] AM3 4 B E 24 VS S[ 1 97 ] V SS [ 2 97 ] T41
VS S [3 0 ] VS S[ 1 0 9] VS S[ 2 02 ] V SS [ 3 02 ]
A D 34 AU 2 0 B E 46 U 30
VS S [3 1 ] VS S[ 1 1 0] VS S[ 2 03 ] V SS [ 3 03 ]
A U 22 AM4 6 B E 48 U 31
VS S [3 2 ] VS S[ 1 1 1] VS S[ 2 04 ] V SS [ 3 04 ]
A D 42 AV 2 2 B E 50 U 32
VS S [3 3 ] VS S[ 1 1 2] VS S[ 2 05 ] V SS [ 3 05 ]
A D 46 AM4 9 BE6 U 34
A D 49 VS S [3 4 ] VS S[ 1 1 3] AM7 BE8 VS S[ 2 06 ] V SS [ 3 06 ] P 38
A D7 VS S [3 5 ] VS S[ 1 1 4] AA 5 0 BF3 VS S[ 2 07 ] V SS [ 3 07 ] V 11
AE 2 VS S [3 6 ] VS S[ 1 1 5] BB 1 0 B F 49 VS S[ 2 08 ] V SS [ 3 08 ] P 16
AE 4 VS S [3 7 ] VS S[ 1 1 6] AN 3 2 B F 51 VS S[ 2 09 ] V SS [ 3 09 ] V 19
AF 1 2 VS S [3 8 ] VS S[ 1 1 7] AN 5 0 BG 1 8 VS S[ 2 10 ] V SS [ 3 10 ] V 20
Y 13 VS S [3 9 ] VS S[ 1 1 8] AN 5 2 BG 2 4 VS S[ 2 11 ] V SS [ 3 11 ] V 22
A H 49 VS S [4 0 ] VS S[ 1 1 9] AP 1 2 BG 4 VS S[ 2 12 ] V SS [ 3 12 ] V 30
A U4 VS S [4 1 ] VS S[ 1 2 0] AP 4 2 BG 5 0 VS S[ 2 13 ] V SS [ 3 13 ] V 31
VS S [4 2 ] VS S[ 1 2 1] VS S[ 2 14 ] V SS [ 3 14 ]
AF 3 5 AP 4 6 BH 1 1 V 32
VS S [4 3 ] VS S[ 1 2 2] VS S[ 2 15 ] V SS [ 3 15 ]
AP 1 3 AP 4 9 BH 1 5 V 34
VS S [4 4 ] VS S[ 1 2 3] VS S[ 2 16 ] V SS [ 3 16 ]
A N 34 AP 5 BH 1 9 V 35
VS S [4 5 ] VS S[ 1 2 4] VS S[ 2 17 ] V SS [ 3 17 ]
AF 4 5 AP 8 BH 2 3 V 38
AF 4 6 VS S [4 6 ] VS S[ 1 2 5] AR 2 BH 3 1 VS S[ 2 18 ] V SS [ 3 18 ] V 43
AF 4 9 VS S [4 7 ] VS S[ 1 2 6] AR 5 2 BH 3 5 VS S[ 2 19 ] V SS [ 3 19 ] V 45
AF 5 VS S [4 8 ] VS S[ 1 2 7] AT1 1 BH 3 9 VS S[ 2 20 ] V SS [ 3 20 ] V 46
AF 8 VS S [4 9 ] VS S[ 1 2 8] BA 1 2 BH 4 3 VS S[ 2 21 ] V SS [ 3 21 ] V 47
A G2 VS S [5 0 ] VS S[ 1 2 9] AH 4 8 BH 4 7 VS S[ 2 22 ] V SS [ 3 22 ] V 49
A G5 2 VS S [5 1 ] VS S[ 1 3 0] AT3 2 BH 7 VS S[ 2 23 ] V SS [ 3 23 ] V5
A H 11 VS S [5 2 ] VS S[ 1 3 1] AT3 6 C 12 VS S[ 2 24 ] V SS [ 3 24 ] V7
VS S [5 3 ] VS S[ 1 3 2] VS S[ 2 25 ] V SS [ 3 25 ]
A H 15 AT4 1 C 50 V8
VS S [5 4 ] VS S[ 1 3 3] VS S[ 2 26 ] V SS [ 3 26 ]
A H 16 AT4 7 D 51 W2
VS S [5 5 ] VS S[ 1 3 4] VS S[ 2 27 ] V SS [ 3 27 ]
A H 24 AT7 E 12 W 52
VS S [5 6 ] VS S[ 1 3 5] VS S[ 2 28 ] V SS [ 3 28 ]
A H 32 AV 1 2 E 16 Y 11
AV 1 8 VS S [5 7 ] VS S[ 1 3 6] AV 1 6 E 20 VS S[ 2 29 ] V SS [ 3 29 ] Y 12
A H 43 VS S [5 8 ] VS S[ 1 3 7] AV 2 0 E 24 VS S[ 2 30 ] V SS [ 3 30 ] Y 15
A H 47 VS S [5 9 ] VS S[ 1 3 8] AV 2 4 E 30 VS S[ 2 31 ] V SS [ 3 31 ] Y 19
A H7 VS S [6 0 ] VS S[ 1 3 9] AV 3 0 E 34 VS S[ 2 32 ] V SS [ 3 32 ] Y 23
A J 19 VS S [6 1 ] VS S[ 1 4 0] AV 3 4 E 38 VS S[ 2 33 ] V SS [ 3 33 ] Y 28
AJ2 VS S [6 2 ] VS S[ 1 4 1] AV 3 8 E 42 VS S[ 2 34 ] V SS [ 3 34 ] Y 30
A J 20 VS S [6 3 ] VS S[ 1 4 2] AV 4 2 E 46 VS S[ 2 35 ] V SS [ 3 35 ] Y 31
VS S [6 4 ] VS S[ 1 4 3] VS S[ 2 36 ] V SS [ 3 36 ]
A J 22 AV 4 6 E 48 Y 32
VS S [6 5 ] VS S[ 1 4 4] VS S[ 2 37 ] V SS [ 3 37 ]
A J 23 AV 4 9 E6 Y 38
VS S [6 6 ] VS S[ 1 4 5] VS S[ 2 38 ] V SS [ 3 38 ]
A J 26 AV 5 E8 Y 43
VS S [6 7 ] VS S[ 1 4 6] VS S[ 2 39 ] V SS [ 3 39 ]
A J 28 AV 8 F 49 Y 46
VS S [6 8 ] VS S[ 1 4 7] VS S[ 2 40 ] V SS [ 3 40 ]
A J 32 AW 14 F5 P 49
A J 34 VS S [6 9 ] VS S[ 1 4 8] AW 18 G 10 VS S[ 2 41 ] V SS [ 3 41 ] Y 5
A T5 VS S [7 0 ] VS S[ 1 4 9] AW 2 G 14 VS S[ 2 42 ] V SS [ 3 42 ] Y 6
AJ4 VS S [7 1 ] VS S[ 1 5 0] BF 9 G 18 VS S[ 2 43 ] V SS [ 3 43 ] Y 8
AK 1 2 VS S [7 2 ] VS S[ 1 5 1] AW 32 G2 VS S[ 2 44 ] V SS [ 3 44 ] P 24
A M4 1 VS S [7 3 ] VS S[ 1 5 2] AW 36 G 22 VS S[ 2 45 ] V SS [ 3 45 ] T43
A N 19 VS S [7 4 ] VS S[ 1 5 3] AW 40 G 32 VS S[ 2 46 ] V SS [ 3 46 ] A D 51
AK 2 6 VS S [7 5 ] VS S[ 1 5 4] AW 52 G 36 VS S[ 2 47 ] V SS [ 3 47 ] A T8
VS S [7 6 ] VS S[ 1 5 5] VS S[ 2 48 ] V SS [ 3 48 ]
AK 2 2 AY 1 1 G 40 A D 47
VS S [7 7 ] VS S[ 1 5 6] VS S[ 2 49 ] V SS [ 3 49 ]
AK 2 3 AY 4 3 G 44 Y 47
VS S [7 8 ] VS S[ 1 5 7] VS S[ 2 50 ] V SS [ 3 50 ]
AK 2 8 AY 4 7 G 52 A T12
VS S [7 9 ] VS S[ 1 5 8] VS S[ 2 51 ] V SS [ 3 51 ]
A F 39 A M6
I be x Pe ak -M_R e v 0_ 9 H 16 VS S[ 2 52 ] V SS [ 3 52 ] A T13
H 20 VS S[ 2 53 ] V SS [ 3 53 ] A M5
H 30 VS S[ 2 54 ] V SS [ 3 54 ] A K45
H 34 VS S[ 2 55 ] V SS [ 3 55 ] A K39
H 38 VS S[ 2 56 ] V SS [ 3 56 ] A V14
H 42 VS S[ 2 57 ] V SS [ 3 66 ]
VS S[ 2 58 ]
Ibe x P ea k -M _R e v 0 _9
Schematic Diagrams
New Card, Mini PCIE
3 . 3V
C 46 1 *0 . 1 u_ 1 0 V _X 7 R _ 0 4 3. 3V
NEW CARD(Port 8)
5
B U F _ P L T_ R S T# 1 U2 6
4 MC 74 V H C 1 G0 8 D F T 1 G
2 R3 2 4 R3 2 5 C2 1 8 C2 3 4 C 2 30
*1 0 0 K _0 4 *1 0 0 K _0 4 0 . 1u _ 1 0V _X 7 R _ 0 4 0 . 1u _ 1 0V _X 7 R _ 0 4 0 . 1 u _1 0 V _ X7 R _0 4
3
1. 5 V S 3 . 3 V S 3. 3 V
U2 4 J _N E W 1
17 8 NC _ RS T # NC_ P E R S T # 13
AUX IN P E R S T# PE RS T #
15 N C _ 3. 3 V A U X 36mils 12
A U XO U T +3 . 3 V A U X
2 3 N C _ 3. 3 V 48mils 14
3. 3 V I N 3. 3V O U T 15 +3 . 3 V
+3 . 3 V
1. 5V O U T
11 N C _ 1. 5 V 48mils 10
+1 . 5 V
9
12 +1 . 5 V
1. 5 V I N N C_ CP P E #
10 17
CP P E # 9 N C_ CP US B # 4 CP P E #
C PUS B # P C I E _W A K E # CP U S B #
1 6 , 25 P C I E _ W A K E # 11
6 16 W AKE#
4 , 1 8 , 2 5, 2 8 B U F _P L T _ R S T # SYSR ST # 1 5 N E W C A R D _ C L K R E Q# CL K RE Q #
1 8 U S B _ OC #2 3 19 3. 3 V S R1 6 6 1 0K _ 0 4
OC # 19
1 5 C L K _ P C I E _N E W _ C A R D R E F C LK +
1 6 , 2 8, 31 SU SB# 1 1 5 C L K _ P C I E _N E W _ C A R D # 18
S TB Y # R E F C LK -
3 . 3V R3 3 3 1 0 K _ 04
4 18 N C _ R C L K E N R 32 6 *1 0 K _0 4 22
NC R C LK E N N C _ S H D N # R 33 7 3 . 3V 15 PCIE _ RX P2 _ NEW _ C A RD P E Tp 0
Sheet 23 of 40 1 .5 VS 3. 3 V S 3 .3 V
5
13
14
16
NC
NC
NC
S HD N#
GN D
20
7
21
*1 0 K _0 4 15
15
15
P C I E _ R X N 2_ N E W _ C A R D
P C I E _T X P 2 _N E W _ C A R D
P C I E _T X N 2 _ N E W _ C A R D
21
25
24
P E Tn 0
PE Rp 0
PE Rn 0
R E SE RV E D
R E SE RV E D
5
6
NC GN D
New Card, Mini W 8 3L 3 5 1Y G

Port 3 1 8 US B _ P P 3
1 8 US B _ P N 3
3
2 US B _ D+
US B _ D-
GN D
1
C4 4 9 C4 6 6 C 4 53 20
6-02-83351-9Q0
PCIE 0 . 1 u_ 1 0 V _X 7 R _ 0 4 0 . 1 u_ 1 0 V _X 7 R _ 0 4 0 . 1 u _1 0 V _ X 7R _0 4
EN E P2 231 p in 3, 4,1 5, 22
1 5 S M L 0_ D A TA
1 5 S M L 0_ C LK
8
7
S MB _ D A T A
S MB _ C L K
GN D
GN D
GN D
GN D 1
23
26
G ND 1
G ND 2
ha s in ter na ll y GN D 2
1 30 8 0 1-0 2
pu ll ed hi gh ( 17 0Ko hm )
6-21-G3A60-126 Connect
6-21-G3A60-126-S ? ?
MINI CARD (WLAN,Port 5)

L ayou t Sho w "WL AN( Wimax, 802 .11N) "Not e
20 mil 3. 3 V
J _ MI N I 1 W L A N1 .5 V 1 .5 V
P C I E _W A K E # 1 2
R3 4 0 *0 _ 04 3 W AKE# 3 . 3V A U X _ 0 6 20 mil R 3 15 * 1 5m i l _s h o rt _0 6
29 B T _E N # CO E X1 1 .5 V _ 0 U I M_ P W R _1
3 .3 V S R 3 05 1 0 K _ 04 2 8 ,2 9 B T _E N R3 4 1 * 10 m i _l s h ort 5 8
CO E X2 UIM _ P W R 10 U I M_ D A T A _ 1 C 4 44
U I M_ D A T A U I M_ C L K _ 1
1 5 W L A N _ C L K R E Q# 7 12
11 C L K R E Q# U I M_ C L K 14 U I M_ R S T _ 1 * 0 . 1u _ 1 0V _X 7 R _ 0 4
1 5 CL K_ P CIE _ M INI# RE F CL K - U I M_ R E S E T U I M_ V P P _ 1
1 5 CL K _ P CIE _ M INI 13 16
9 RE F CL K + U I M_ V P P
GN D 0
15 4
GN D 1 G ND 5
KEY
21 18
GN D 2 G ND 6
27 26
29 GN D 3 G ND 7 34 R 3 16
GN D 4 G ND 8 3 .3 V S
40 * 1 0K _ 0 4
35 G ND 9 50
2 8 W LA N _ D E T # GN D 1 1 G ND 1 0
15 P C I E _ R XN 3 _W L A N 23
25 PET n 0 20
15 P CIE _ RX P 3 _ W L A N PET p 0 W _ D I S A B LE # B U F _ P LT _ R S T # W LA N _ E N 2 8 , 2 9
15 P C I E _ T XN 3 _W L A N 31 22
33 P E R n0 PER SET # 30
15 P C I E _ TX P 3 _ W L A N P E R p0 S MB _ C L K
32 BT _ DE T #
17 S MB _ D A T A 36 28
28
28
8 0 D E T#
3 IN1 19
37
R e s e rv ed 0
R e s e rv ed 1
GN D 1 2
U S B_ D-
US B _ D +
38
20 mil
USB _ P N 2 1 8
USB _ P P2 1 8 Port 2
39 24 3 .3 V AUX _ 1 R 3 17 * 1 5m i l _s h o rt _0 6
3 .3 V 3 . 3V A U X _ 3 3 . 3V A U X _ 1 3. 3 V
41 28
3 . 3V A U X _ 4 1 .5 V _ 1
43
GN D 1 3 1 .5 V _ 2
48 40 mil W L A N1 .5 V
MI N I _ C L K 1 45 52
MI N I _ D A T A 1 R e s e rv ed 2 3 . 3V A U X _ 2 3 .3 V
47 42 20 mil
MI N I _ R S T # 1 49 R e s e rv ed 3 LE D _ W W A N # 44
R e s e rv ed 4 L ED_ W L A N #
V DD 3 R3 0 6 *1 5 mi l _ sh o rt _ 06 51 46 80 C LK 28
R e s e rv ed 5 LE D _ W P A N #
8 8 91 0 -5 20 4 M-0 1
4 , 9 , 10 , 1 1 , 21 , 2 7 , 2 9, 3 1 , 3 3, 3 6 1 . 5 V
2 0 , 3 1, 3 6 1 . 5 V S
3 , 4 , 12 , 1 4 , 1 5, 1 6 , 1 8, 1 9 , 2 0, 2 1 , 2 4 , 25 , 2 9 , 30 , 3 1 , 33 , 3 4 , 3 5 3 . 3 V
2, 1 0 , 1 1, 12 , 1 3 , 14 , 1 5 , 16 , 1 7 , 1 8, 1 9 , 2 0, 2 1 , 2 4, 2 5 , 2 6 , 27 , 2 8 , 29 , 3 0 , 31 , 3 5 , 3 6 3 . 3 V S
14 , 2 5 , 28 , 2 9 , 31 , 3 2 , 3 7 V D D 3
B - 24 New Card, Mini PCIE

Schematic Diagrams
CCD, 3G, TPM
MINI CARD 3G(Port 6) 3G POWER

R 17 8 * 0 _0 6
Layo ut Sho w "3.5G(HSDPA)" No te
3G _ 3. 3 V 3 .3 V Q 14 3 G_ 3. 3 V
3A 120mils A O3 4 15 3A 120mils
J_ 3 G1 6 0mi ls S D
1 2
W A KE# 3 .3 V A UX _ 0
3 6
5 C OE X 1 1 .5 V _ 0 8 UIM _ PW R
C OE X 2 U I M_ P W R
G
10 UIM _ DAT A C 1 96 +C 2 48 C 2 41 R1 7 0 C2 4 2
7 U I M_ D A T A 12 UIM _ CL K C 20 1 C 25 1
C L K R E Q# U I M_ C L K UIM _ RST
11 14 0 . 1 u _1 0 V _ X7 R _ 0 4 2 2 0 u_ 4 V _ V _B 10 0 K _ 04 0. 1 u _ 10 V _ X 7R _ 04
13 R EF CL K- U I M_ R E S E T 16 UIM _ VPP 0 . 1 u _1 0 V _X 7 R _ 0 4 1 0 u_ 6 . 3 V _X 5 R _ 0 6 1u _ 6 . 3V _ X 5 R _ 04 R 1 68
9 R EF CL K+ U I M_ V P P
15 G ND 0 4 20 K _ 1 %_ 0 4
G ND 1 G ND 5 R 1 67
KE Y
D
10 0 K _ 04 Q1 3
21 18
G ND 2 G ND 6
27 26 28 3 G_ P O W E R G MT N 70 0 2 Z H S 3
29 G ND 3 G ND 7 34
G ND 4 G ND 8
40
35 G ND 9 50
28 3 G _D E T# 23 G N D 11 GN D 1 0
P E Tn 0
F ro m SB G PIO Pin de f au lt HI
25 20
31 P E Tp 0 W _ D I S A B LE # 22 3 G_ E N 28 L19 Po w er Pl a ne : Su sp en d
P E Rn 0 PER SET#
33 30 *W C M2 0 12 F 2 S -1 61 T 0 3-s h o rt
P E Rp 0 S MB _ C L K 32 3 4 S3: De fi n ed
3 G_ 3 . 3V S MB _ D A T A US B _ P N9 18
17 36
R e se rv e d 0 US B _ D-
Sheet 24 of 40
19 38 2 1
R e se rv e d 1 US B _ D + US B _ P P 9 18
37
39 G N D 12 24 R1 5 6 * 1 5m i l_ s h ort _ 0 6
3 .3 V A UX _ 3 3 .3 V A UX _ 1 3 G_ 3. 3 V
41 28
C2 2 1
0. 1 u _ 10 V _ X 7R _0 4
C4 2 0
10 u _ 6. 3 V _ X 5R _ 06
43
45
47
3 .3 V A UX _ 4
G N D 13
R e se rv e d 2
1 .5 V _ 1
1 .5 V _ 2
3 .3 V A UX _ 2
48
52
42
6 0mil s
3 G_ 3 . 3 V
SIM CONN CCD, 3G, TPM
49 R e se rv e d 3 L E D_ W W A N # 44 R1 3 6 4 . 7K _0 4
R e se rv e d 4 L E D_ W L A N # +C 20 6
51 46 C 4 21
R e se rv e d 5 L E D_ W P A N #
88 9 1 0-5 2 04 M -01 *0 . 1u _ 1 0V _ X 5 R _ 04 2 2 0u _ 4 V _V _ B
J _S I M 1
R 30 7 L OCK R3 0 4
* 10 m i l_ s ho rt ( TO P V IE W) *1 0 m il _ sh o rt
U I M_ C L K C 3 C7 U I M_ D A T A
U I M_ R S T U I M_ C LK U I M_ D A TA U I M_ V P P
C 2 C6
U I M_ P W R C 1 U I M_ R S T U I M _V P P C5
C 4 30 U I M_ P W R U I M _G N D
C4 1 1 C4 1 0 C 4 12
2 2 p _5 0 V _ N P O _0 4 OPE N
C 1 7 70 6 6 1-1 2 2p _ 5 0V _ N P O_ 04 2 2p _ 5 0V _ N P O_ 04 22 p _5 0 V _ N P O _0 4
S I ML O C K
3 . 3V S
TPM 1.2
* 0. 1 u _ 10 V _ X 7 R _ 0 4
*0 . 1 u _1 0 V _ X 7R _0 4
*0 . 1 u_ 1 0V _ X 7 R _ 0 4
CCD
[ PVT- 1] U1 4 5V Q4 5 V_ CC D
26 10 C2 8 3 M TP 3 4 0 3N 3 48 mil
1 4, 2 8 L PC _A D 0 LA D 0 VDD 1
1 4, 2 8 L PC _A D 1 23 19 L1 * 15 m i l_ s h ort _ 0 6 S D
20 LA D 1 VDD 2 24 *1 u _6 . 3 V _ X5 R _0 4
C2 8 7
C 26 6
C2 9 0
1 4, 2 8 L PC _A D 2 17 LA D 2 VDD 3
1 4, 2 8 L PC _A D 3 LA D 3 MJ_CCD1
C 3 C2 R9 C5 C8 C9
G
21 TPM 1
1 8 P C L K _T P M LC LK
3 . 3V S 1 u _6 . 3 V _ X5 R _0 4 1 00 K _ 0 4 1u _ 6. 3V _ X 5R _ 04 0. 1 u _ 10 V _ X 7R _0 4 1u _ 6 . 3V _ X 5 R _ 04
22 5 0. 1 u _ 10 V _ X 7R _0 4
1 4 ,2 8 L P C _F R A ME # LF R A ME # VS B
18 P L T _ RS T # 16 R 8 5
27 LR E S E T # C2 6 5
1 4 ,2 8 S E RIRQ S E RIR Q
16 P M _ CL K RU N# 15 1 0 0K _ 0 4
CL K RU N# *0 . 1 u_ 1 0 V _X 7 R _ 0 4 J_ C C D 1
R 19 7 * 0 _0 4 TP M _L P C P D # 28 6 T P M3 0 04 R 7 3 3 0 K _0 4
1 6 S 4 _ S T A TE # LP C P D # GP I O 1
2 T P M3 0 05 18 U S B_ PN5
D
TP M _B A D D 9 GP I O 2 2
TE S T B I / B A D D 18 US B _ P P 5 3
13 XTAL I Q 5 C C D _D E T#
T P M_ P P 7 XT AL I CC D_ E N G M TN 70 0 2 Z H S 3 2 8 CC D_ DE T # 4
PP 28 CC D_ E N 5
X3
S
14 XTAL O 4 1 * C M2 0 0 S 32 7 6 81 2 2 0_ 3 2. 7 6 8 K H z 85 2 0 5-0 5 0 01
T P M3 0 01 1 X TA L O
3 2 From H8 default HI
T P M3 0 02 3 NC_ 1 4 C 2 54 C 26 0
T P M3 0 03 1 2 NC_ 2 GN D_ 1
11
NC_ 3 GN D_ 2 18 * 18 p _5 0 V _ N P O _0 4 * 18 p _ 50 V _ N P O _0 4
GN D_ 3
8 25
TE S T I GN D_ 4
*S L B 9 6 35 T T
As se rte d be fore e nte rin g S 3 3, 4 , 1 2 , 14 , 1 5 , 16 , 1 8 , 19 , 2 0 , 21 , 2 3 , 25 , 2 9 , 30 , 3 1, 33 , 3 4, 35 3 . 3 V
P C LK _ T P M R1 8 5 *3 3 _0 4 C 27 8 * 1 0p _ 50 V _ N P O _ 06 2, 1 0 , 11 , 1 2 , 13 , 1 4 , 15 , 1 6 , 17 , 1 8 , 19 , 2 0 , 21 , 2 3 , 25 , 2 6 , 27 , 2 8 , 29 , 3 0, 31 , 3 5, 36 3 . 3 V S
L PC r es et timing : 2 1 , 27 , 3 0, 31 , 3 3, 34 5 V
L PCPD# ina ct ive t o L RST# in ac tive 3 2~96 us 3 .3 V S
T P M _L P C P D # R1 9 8 *1 0 K _ 04
HI: ACCESS T P M _P P R1 9 0 *1 0 K _ 04
T PM _PP LOW: NORMAL ( Int er nal PD) T P M _B A D D R1 8 8 *1 0 K _ 04
HI: 4E/ 4F H
T PM _BADD LOW: 2E/ 2F H R1 8 4 *1 0 K _ 04
CCD, 3G, TPM B - 25

Schematic Diagrams
Card Reader, LAN (JMB251)
Sw it ch in g Re gu la to r S5 WAKE ON LAN
cl os e to P IN 6
JMC251 S D _C L K R 18 7 2 2 _0 4 ( >2 0m il )
REG L X
L35
. DV DD
D V DD
V D D3
3 .3 V_ L AN 3 .3 V _ L A N
( >2 0m il ) 2A
S W F 25 2 0 C F -4 R 7M -M C 4 36 C2 9 3
3 .3 V
M DI O Si ng le 1 0 u _6 . 3 V _ X 5R _ 06 0 . 1u _ 1 0V _X 7 R _ 0 4 C 47 2 3 . 3V _ L A N
Fo r JM C2 51 /2 61 Pin#7 Pin#7 U 27 L37
2A
M D I O 12
E nd = 5 0
SD _ BS
S D_ W P
S D_ D0
S D _D 1
M D I O7
*0 . 1 u_ 1 0 V _ X7 R _0 4 4 1 2 1
S D_ D2
S D_ D3
O hm on ly 5 V IN V O UT
3 .3 V_ L AN V IN H C B 2 0 1 2 K F -5 00 T 4 0
R 1 75 4 .7 K _ 0 4 S D _ CD # 3 2
2 8 S 5 _ L A NO N EN GN D
48
47
46
45
44
42
40
39
38
37
36
35
34
33
43
41
U1 3 R 17 8 R1 88 R4 32 C5 66 F un ct io n R 34 5 *G 52 4 3 A
R 1 76 1 0 K _ 04 M S _ INS# 0 NC NC NC Di sa bl e D3 E
V DD IO
M DIO 0
M D I O1
M DIO 2
M DIO 3
MD I O 4
M D I O5
M D I O6
M DIO 7
M DIO 8
M DIO 1 0
M D I O1 2
V DD IO
GN D
MD I O9
MD I O1 1
NC NC 0 NC En ab le D 3E (1 ) *1 0 0 K _ 04
V C C_ C A RD
NC 10 0K NC 0. 1u En ab le D 3E (2 )
R N2 5 L A N_ L E D0 49 32
1 0 K _8 P 4 R _0 4 L A N_ L E D1 50 L ED 0 G ND 31 M DIO 1 3 1. For JM C251/JMC261 on ly.
Card Reader
L ED 1 M D I O1 3
8 1 SD _ W P
D VDD 51
VD D M D I O1 4
30 M DIO 1 4 2. MPD co nnect to Main Po wer or
7 2 SD _ BS 52 29 C R1 _ L E DN
6 3 M D I O 13 53 G ND S MB _ S D A / C R _ LE D N 28 RSTN for D3E applicaion, t o AUX Power
26 L A N _M D I P 0 V I P _1 T EST N V CC_ C A RD
5 4 54 27 po wer ot herwise.
26 L A N _M D I N 0
D VDD 55
56
V I N_ 1
A V D D 12 JMC251 V D DIO
V DD
26
25
3 .3 V_ L AN
D VD D
3. 3V _ L A N
3 .3 V_ L AN
Card Reader Pull 26 L A N _M D I P 1
57 V I P _2 V C C3 O 24 S D _ CD #
V C C _C A R D
High/Low
26 L A N _M D I N 1
58
59
V I N_ 2
G ND JMC261 C R _C D 0 N
C R _C D 1 N
23
22
M S _ INS #
L A N _L E D 2
L A N _L E D 2
C R1 _ L E DN
R 1 77
R 1 72
* 4. 7 K _ 0 4
* 4. 7 K _ 0 4 R 3 30
Sheet 25 of 40 Resistors 26
26
3 .3 V _ L A N
L A N _M D I P 2
L A N _M D I N 2
D VDD
L A N_ M DIP 2
L A N_ M DIN 2
60
61
62
A V D D 33
V I P _3 (N C )
V I N _ 3 (N C )
(LQFP 64)
S MB _ S C L/ L E D 2
C R E QN
M PD
21
20
19
R3 0 9
R3 1 0
* 0 _0 4
* 1 00 K _ 0 4
3 .3 VS
7 5 _ 1% _ 0 4
A V D D 12 (N C ) W AKEN L A N _ P CIE _ W A K E # 2 8
Card Reader,
L A N_ M DIP 3 63 18 C2 4 7 * 0 . 1u _ 1 0V _X 5 R _ 0 4
3 .3 VS 26 L A N _M D I P 3 V I P _4 (N C ) RS T N
L A N_ M DIN 3 64 17 D VD D R3 0 8 0 _0 4
26 L A N _M D I N 3 V I N _ 4 (N C ) A V DD X
V D DR E G
R 1 86 * 10 K _ 0 4 M D I O 7
V D DX 3 3
S5 WAKE ON LAN
A VD DH
LAN (JMB251)
C L KP
R EXT
X O UT
CL KN
F B1 2
GN D
R XN
GN D
T XN
RXP
T XP
R 3 12 * 20 0 K _ 0 4 M D I O 12
X IN
LX
R 1 74 * 20 0 K _ 0 4 M D I O 14
JM C 2 5 1 PC Ie D if fe re nt ia l B U F _ P L T _ R S T # 4 , 18 , 2 3 , 2 8
10
11
12
13
14
15
3 .3 V_ L AN
1
2
3
4
5
6
7
8
9
16
R 346 0_04 2009/11/17
Pa ir s = 10 0 Oh m
R3 4 7 * 1 0K _ 0 4
LA N X O U T
C 2 49 0 . 1 u_ 1 0 V _ X7 R _0 4 D 22
L ANX IN
P C I E _ R X P 4 _ GL A N 1 5
RE G L X
C 2 50 0 . 1 u_ 1 0 V _ X7 R _0 4
D VDD
P C I E _R X N 4 _ GL A N 15 P C I E _W A K E # L A N _ P CIE _ W A K E #
1 6 , 2 3 P C I E _W A K E # A C L A N _ P CIE _ W A K E # 2 8
R1 9 9
12 K _ 1 % _ 04 *S C S 7 5 1 V -4 0
P C I E _ T XN 4 _G L A N 1 5
P C I E _T X P 4 _ GL A N 15
DV D D
3. 3 V _ L A N 3. 3V _ L A N
C LK _P C I E _ GL A N 1 5
C 2 96
C L K _ P C I E _ GL A N # 1 5 4 IN 1 SOCKET SD/MMC/MS/MS Pro
0 . 1 u _ 10 V _ X 7 R _ 0 4
Pin#26
J _ C A R D -R E V 1
3 . 3 V _ LA N
S D_ C D# P1
S D_ D 2 C D_ S D
P2
DV D D C 24 4 C 44 8 S D_ D 3 P3 D A T 2_ S D
Fo r JM C2 51 /2 61 C D / D A T 3_ S D
S D_ B S P4
0 . 1 u _1 0 V _ X 7R _ 04 1 0u _ 6 . 3 V _X 5 R _ 0 6 on ly P5 C MD _S D
V S S _S D
P6
C 2 94 C2 7 5 C 2 45 C 4 31 Pin#8 Pin#8 V CC _ CA R D S D _ C LK P7 V D D_ S D
C LK _S D
C 4 26 P8
0 . 1 u _ 10 V _ X 7 R _ 0 4 0 . 1 u_ 1 0 V _ X7 R _0 4 0 . 1 u _ 10 V _ X 7 R _ 0 4 1 0 u _6 . 3 V _ X 5 R _ 0 6 S D_ D 0 P9 V S S _S D
Pin#51 Pin#62 Pin#55 Pin#55 0 . 1 u _ 10 V _ X 7 R _ 0 4 S D_ D 1 P1 0 D A T 0_ S D
LA N X OU T S D_ W P D A T 1_ S D
Reserved P1 1
P1 2 W P _S D
V S S _M S
V CC _ CA R D P1 3
S D _ C LK P1 4 V C C_ M S
3 .3 V_ L AN S D_ D 3 S C L K _ MS
C 4 25 P1 5
R1 8 3 1 M_ 0 4 L A N XI N MS _ I N S # P1 6 D A T 3_ M S
I N S _ MS
0 . 1 u _ 10 V _ X 7 R _ 0 4 S D_ D 2 P1 7
X4 S D_ D 0 P1 8 D A T 2_ M S
C 2 95 C2 3 5 2 1 S D_ D 1 P1 9 S D I O/ D A T 0 _M S
S D_ B S D A T 1_ M S
P2 0 P2 2
0 . 1 u _ 10 V _ X 7 R _ 0 4 0 . 1 u_ 1 0 V _ X7 R _0 4 X 8 A 0 2 50 0 0 F G1 H _2 5 MH z P2 1 BS_ M S G ND P2 3
V S S _M S G ND
Pin#38 Pin#27 C 2 58 C2 7 1
M D R 0 19 -C 0 -10 4 2
22 p _ 50 V _ N P O_ 0 4 2 2p _ 5 0 V _N P O _0 4
3 .3 V_ L AN
V C C_ C A RD V C C_ CA RD
C 4 63 C4 1 9 C 2 72 C 2 82
S D _C L K
1 0 u _6 . 3 V _ X 5 R _ 0 6 0 . 1 u_ 1 0 V _ X7 R _0 4 0 . 1 u _ 10 V _ X 7 R _ 0 4 0 . 1 u _ 10 V _ X 7 R _ 0 4
Pin#59 Pin#59 Pin#2 Pin#11 C2 8 1 C4 2 8 C4 2 9 C4 5 6 C 2 46
Reserved
*1 0 p _5 0 V _ N P O_ 0 6 0 . 1 u_ 1 0 V _ X7 R _0 4 4 . 7 u_ 6 . 3 V _ X5 R _0 6 0 . 1 u_ 1 0 V _ X7 R _0 4 0 . 1 u _ 10 V _ X 7 R _ 0 4
Place all capac itors clo sed to chip .

The subscript in eac h CAP incicat es th e pi n Near Cardreader CONN
n umber of JM C251/JMC261 tha t should b e 14 , 2 3 , 2 8, 2 9 , 3 1 , 32 , 3 7 V D D 3
26 D V DD
closed to . 2 , 1 0 , 1 1, 1 2 , 1 3 , 14 , 1 5 , 1 6, 1 7 , 1 8 , 19 , 2 0 , 2 1, 23 , 2 4 , 2 6, 2 7 , 2 8 , 29 , 3 0 , 3 1, 3 5 , 3 6 3 . 3V S
3 , 4 , 1 2, 1 4 , 1 5 , 16 , 1 8 , 1 9, 20 , 2 1 , 2 3, 2 4 , 2 9 , 30 , 3 1 , 3 3, 3 4 , 3 5 3 . 3V
B - 26 Card Reader, LAN (JMB251)

Schematic Diagrams
LAN (JMC251), SATA HDD, ODD
GIGA LAN (JMC251)

L2 6 L P2
*S B 0 4 02 T L -04 0 -s ho rt J _R J 1
L A N _ MD IP 0 12 13 L MX 1 + 1 8 D L MX 1 + 1 GN D 1
25 L A N _ MD IP 0 TD 4+ MX 4 + DA + s h ei l d
L A N _ MD IN0 11 14 L MX 1 - 2 7 D L MX 1 - 2 GN D 2
25 L A N _ MD IN0 L A N _ MD IP 1 9 TD 4- MX 4 - 16 L MX 2 + 3 6 D L MX 2 + 3 DA - s h ei l d
25 L A N _ MD IP 1 TD 3+ MX 3 + DB +
L A N _ MD IN1 8 17 L MX 2 - 4 5 D L MX 2 - 6
25 L A N _ MD IN1 TD 3- M X 3- L P1 DB - G ND
*S B 0 4 02 T L -04 0 -s ho rt
L A N _ MD IP 2 6 19 L MX 3 + 4 5 D L MX 3 + 4
25 L A N _ MD IP 2 T D 2+ MX 2 + DC +
L A N _ MD IN2 5 20 L MX 3 - 3 6 D L MX 3 - 5
25 L A N _ MD IN2 L A N _ MD IP 3 3 T D 2- MX 2 - 22 L MX 4 + 2 7 D L MX 4 + 7 DC -
25 L A N _ MD IP 3 T D 1+ MX 1 + DD +
L A N _ MD IN3 2 T D 1- MX 1 - 23 L MX 4 - 1 8 D L MX 4 - 8
25 L A N _ MD IN3 DD -
D V DD 10 15 P J S -0 8S L3 B
7 TC T4 MC T4 18
TC T3 MC T3
4 21
1 TC T2 MC T2 24
TC T1 MC T1
R2 7
GS T 5 00 9 L F
*0 _ 04 PN:6-19-41001-239
4 0 mil NM
NM
NM
CT _ 1
CT _ 2
CT _ 3
R2 3
R2 4
R2 5
7 5 _ 1%
7 5 _ 1%
7 5 _ 1%
_ 0 4 NM CT _ R
_04
_04
Sheet 26 of 40
C3 0 C2 7 C2 5 C2 3 NM CT _ 4 R3 1 7 5 _ 1% _04
0 . 01 u _ 50 V _ X 7R _ 04 0 . 01 u _ 50 V _ X 7R _ 04 0. 01 u _ 50 V _ X 7R _ 04 0. 0 1 u _5 0 V _ X 7R _0 4 C 3 26 LAN (JMC251),
1 0 0 0p _ 2 K V _ X7 R _1 2
SATA HDD, ODD
SATA HDD
SATA ODD
J_ H D D 1
S 1
S 2 S A T A _T X P 0 C 4 27 0 . 01 u _ 50 V _ X 7R _ 04 J _ OD D 1
S A T A T X P 0 14
S 3 S A T A _T X N 0 C 4 24 0 . 01 u _ 50 V _ X 7R _ 04 S1
S A T A T X N0 1 4 SATA_ TXP1
S 4 S2 C3 8 8 0 . 0 1 u _5 0 V _ X7 R _0 4 S A T A TX P 1 1 4
S 5 S A T A _R X N 0 C 4 23 0 . 01 u _ 50 V _ X 7R _ 04 S3 S A T A _ T X N1 C3 8 7 0 . 0 1 u _5 0 V _ X7 R _0 4
S A T A _R X P 0 S A T A R XN 0 14 S A T A TX N 1 1 4
S 6 C 4 22 0 . 01 u _ 50 V _ X 7R _ 04 S A T A R XP 0 1 4 S4
S 7 S5 S A T A _ RX N 1 C3 8 4 0 . 0 1 u _5 0 V _ X7 R _0 4
S A T A _ RX P 1 S A T A RX N1 1 4
3 .3 V S S6 C3 8 3 0 . 0 1 u _5 0 V _ X7 R _0 4 S A T A RX P 1 1 4
S7
P 1
P 2
P 3 C 4 18 C 4 17
P 4 P1 5V S
P 5 0 . 0 1 u_ 5 0 V _ X7 R _ 0 4 * 10 u _ 6. 3V _ X 5 R _ 0 6 P2 OD D _ D E T E C T# 1 4
P 6 P3
P 7 5 VS P4
P 8 P5 C3 6 8 C3 7 0 C 3 65 C3 7 5 C3 7 6 C 37 4 + C 37 2
P 9 P6
P 10 *0 . 1 u _1 0 V _ X 5R _0 4 0 . 1 u_ 1 0 V _X 7 R _ 0 4 0 . 1 u _1 0 V _ X 7R _0 4 *0 . 1 u _1 0 V _ X5 R _0 4 1 u_ 6 . 3 V _X 5 R _ 0 4 1 0 u _6 . 3 V _ X5 R _0 6 1 0 0u _ 6 . 3V _B _ A
0 . 1 u _1 0 V _ X 7 R _ 0 4
0 . 1 u _1 0 V _ X 7 R _ 0 4
0 . 1 u _1 0 V _ X 7 R _ 0 4
1 u _ 6. 3 V _ X 5 R _ 0 4
P 11 HD D_ NC 0 C 1 8 55 3 -1 13 0 5 -L
2 2 u _6 . 3 V _ X 5 R _ 08
2 2 u _6 . 3 V _ X 5 R _ 08
P 12 P I N GN D 1 ~ 2 = GN D
P 13 HD D_ NC 1
P 14 HD D_ NC 2
P 15 HD D_ NC 3 C 21 1
+
A C E S -9 19 0 7 -02 2 0 A -H 0 1
P I N GN D 1 ~ 2 = GN D * 10 0 u _6 . 3 V _ B _ A
5 VS 2 , 13 , 1 7 , 20 , 2 1 , 2 7, 3 0 , 3 1, 3 5 , 3 6
C 4 16
C 4 15
C 4 13
C 4 14
C 2 00
C 19 9
5 VS DV DD 25
3 .3 V 3 , 4, 1 2 , 1 4, 1 5 , 1 6 , 18 , 1 9 , 20 , 2 1 , 23 , 2 4 , 2 5, 2 9 , 3 0, 3 1 , 3 3, 34 , 3 5
1 .5 V 4 , 9, 1 0 , 1 1, 2 1 , 2 3 , 27 , 2 9 , 31 , 3 3 , 36
3 .3 V S 2 , 10 , 1 1 , 12 , 1 3 , 1 4, 1 5 , 1 6, 1 7 , 1 8, 1 9 , 2 0 , 21 , 2 3 , 24 , 2 5 , 27 , 2 8 , 2 9, 3 0 , 3 1, 3 5 , 3 6
C 28 5 C 81 C 4 39
0 . 0 1u _ 5 0V _X 7 R _ 0 4 0 . 0 1u _ 5 0V _ X 7 R _ 0 4 0. 0 1 u _5 0 V _ X7 R _0 4
LAN (JMC251), SATA HDD, ODD B - 27

Schematic Diagrams
Audio Codec VIA 1812
CODEC (VIA1812 /ALC272) 3 .3 V S 1 .5 V

P IN2 5, PI N3 8 ? 1? 1 0u F/. 1u F
R 31 9 *1 5 m li _ s ho rt _ 0 6
D1 9 *R B 5 51 V 3 0
R 31 3 *0 _0 4 C 29 1 C4 4 2 C A
5 V S_ A UD 5V
0 . 1 u _1 0 V _ X7 R _ 0 4 10 u _ 6. 3 V _ X 5R _ 06
PC BEEP D1 8
B A T 5 4C S 3
3. 3 V S 3. 3 V S _ A U D
C 4 38 C4 6 7
L2 3 . H C B 1 6 0 8K F -12 1 T 25
5V S
L 21 . H C B 1 6 0 8K F -12 1 T 25 AU DG
0 . 1 u _1 0 V _ X 7R _0 4 1 0u _ 6 . 3V _ X 5 R _ 0 6 C4 3 3 C 29 2
1 A C 2 88 C4 6 5 C 46 4 C2 7 3 *0 . 1 u_ 1 0V _X 5 R _ 0 4
28 K B C _B E E P * 1u _ 6 . 3V _X 5 R _ 0 4
C 3 BEEP 0. 1 u _ 10 V _ X 7R _ 04 1 0u _ 6 . 3V _ X 5 R _ 0 6 0 . 1 u_ 1 0 V _X 7 R _ 0 4 0 . 1 u_ 1 0 V _X 7 R _ 0 4 L3 6 * 1 5m i _l s h ort _0 6
A U DG C 4 69 0 . 1u _ 1 0V _X 7 R _ 0 4
2 A C 4 68 0 . 1u _ 1 0V _X 7 R _ 0 4
14 HD A _ S P K R
C 4 47 *0 . 1 u_ 1 0 V _ X7 R _ 0 4 C 2 67 0 . 1u _ 1 0V _X 7 R _ 0 4
C 4 32 0 . 1u _ 1 0V _X 7 R _ 0 4
25
38
4
7
1
9
U2 3 C 4 43 0 . 1u _ 1 0V _X 7 R _ 0 4
A L C_ V RE F C 4 52 1 0 u_ 6 . 3 V _X 5 R _ 0 6
D VSS2
A V DD1
A V DD 2
D V D D -I O
D VDD
DV SS 1
C4 5 8 2 2 p _5 0 V _ N P O _0 4
FOR EMI
C2 8 0 * 2 2p _ 5 0V _ N P O_ 0 4
MI C 2_ L C2 6 8 * 0 . 1u _ 1 0V _ X 5 R _ 0 4 A LC _G P I O0 2 A U DG A U DG
MI C 2_ R C2 6 9 * 0 . 1u _ 1 0V _ X 5 R _ 0 4 C2 7 4 * 2 2p _ 5 0V _ N P O_ 0 4 A LC _G P I O1 3 G P I O0 / D MI C - D A T A 1 / 2 27
G P I O1 / D MI C - D A T A 3 / 4 V RE F
MI C 1_ L C2 6 3 * 0 . 1u _ 1 0V _ X 5 R _ 0 4 R3 3 1 2 2 _ 04 A Z _ S DO UT _ R 5
MI C 1_ R C2 5 2 * 0 . 1u _ 1 0V _ X 5 R _ 0 4
1 4, 2 9 H D A _ S D O U T
1 4, 2 9 H D A _ B I T C L K R3 2 9 2 2 _ 04 A Z _ B IT CL K _ R 6
S D A T A -OU T
28 M I C 1 -V R E F O A 1 MI C 1 -V R E F O -R R3 2 1 4 . 7 K _0 4 M I C 1 -R L ay ou t No te :
R3 2 3 2 2 _ 04 A Z _ S D I N 0 _R 8 B I T -C LK MI C 1 -V R E F O
14 H DA_ S D IN0 S D A T A -I N V er y clo se t o A ud io C ode c
R3 2 2 2 2 _ 04 A Z _ S Y N C_ R 10 3 C D2 0
1 4, 29 H D A _ S Y N C S Y NC
A UD G R3 1 8 2 2 _ 04 A Z _ RS T # _ R 11 37 B A T 5 4A S 3
1 4 , 2 9 H D A _ R S T# R ESET# MO N O -OU T A 2 MI C 1 -V R E F O -L R 32 0 4 . 7 K _0 4 M I C 1 -L
E A P D _M OD E 47
DIGITAL
C4 4 5 2 2 p _5 0 V _ N P O _0 4 EAP D
La yo ut No te :
Sheet 27 of 40 Ver y cl os e t o Au di o C od ec C4 5 1 2 2 p _5 0 V _ N P O _0 4
48
45
46
S P D I F O1
S P D I F O2
CP V E E
C BN
CB P
31
30
29
C 45 9
C 45 7
2 . 2 u _ 16 V _ X 5R _0 6
2 . 2 u _ 16 V _ X 5R _0 6 La yo ut N ote :
Ne ar MI C con ne ct
D MI C -C L K 1 / 2
Audio Codec BEEP R3 1 1 1 0K _ 0 4 PC BEEP_ C C 43 5 1u _ 6. 3V _ X 5 R _ 0 4 P CB E E P _ R

44
43
12
D MI C -C L K 3 / 4
N C LO U T 1 -L
35
36
F R ON T-L
F R ON T-R
A UDG
VIA1812
P C B E E P -I N L OU T 1 -R
R3 1 4 5 . 1K _1 % _ 04
C4 3 4 1 00 p _ 50 V _ N P O _ 04 M I C _ S E N S E R 1 81 2 0 K _ 1% _ 0 4 JD 1 13 39
A UD G 30 MI C _ S E N S E H P _S E N S E R 3 34 JD 2 S e n s e A ( JD 1) LO U T 2 -L
5 . 1 K _ 1% _ 0 4 34 41
30 HP _ S E NS E C2 6 2 * 10 0 p _5 0 V _ N P O _0 4 S e n s e B ( JD 2) L OU T 2 -R
R314 C 25 5 *0 . 1 u_ 1 0 V _X 7 R _ 0 4 C2 8 9 * 10 0 p _5 0 V _ N P O _0 4 14 33
1. 5V V IA 181 2 10 K C 28 6 *0 . 1 u_ 1 0 V _X 7 R _ 0 4 15 L I N E 2-L
L I N E 2-R
ANALOG H P OU T -L
H P O U T -R
32
H E A D P H ON E -L 30
H E A D P H ON E -R 3 0
3. 3V V IA 181 2 5. 1K I N T _ MI C R 17 9 1 K _ 04 I N T _ MI C _R
C 2 56
C 2 57
4 . 7u _ 6 . 3V _X 5 R _ 0 6
4 . 7u _ 6 . 3V _X 5 R _ 0 6
MI C 2 _L
MI C 2 _R
16
17
M I C 2 -L LI N E 1 -L
23
24
M I C 2 -R L I N E 1 -R
AL C27 2 1K 18 NEAR CODEC MI C 2- V R E F O J_INTMIC1
MI C 2 -V R E F O 19 L I N E 1-V R E F O 40 J DR E F R1 9 1 5 . 1K _ 1 % _ 04 2 1
M I C 2 -V R E F O JD R E F
20 R7 8
L I N E 2-V R E F O
M I C 1 -L R 18 2 7 5 _1 % _ 04 M I C 1 _ L_ C C 2 61 4 . 7u _ 6 . 3V _X 5 R _ 0 6 MI C 1 _L 21 C2 7 9 * 1 00 p _5 0 V _ N P O _ 04 2 . 2 1K _ 1 % _0 4
30 M I C 1 -L
A VSS2
M I C 1 -L
AVSS1
M I C 1 -R R 18 0 7 5 _1 % _ 04 M IC1 _ R_ C C 2 53 4 . 7u _ 6 . 3V _X 5 R _ 0 6 MI C 1 _R 22 J _ I N T MI C 1
30 MI C 1-R M I C 1 -R I N T _ MI C
1
2
C4 4 1 C 44 0 V T 18 1 2 A UD G C1 2 9
L ay ou t N ot e:
26
42
8 8 2 66 -0 2 00 1
6 80 p _ 50 V _ X 7R _ 04 6 8 0p _ 5 0V _X 7 R _ 0 4 V ery c lo se to A ud io Co de c 3 30 p _ 50 V _ X 7R _ 04 P C B F o o t pri n t = 88 2 6 6-2 L
R311 VIA1812 5.1K_1%_04
A UD G A UD G
A UDG
ALC272 20K_1%_04
5 V S _ RE A R L3 4 5 VS
H C B 10 0 5 K F -12 1 T 20
L ay ou t N ot e:
C ode c pi n 1 ~ p in 11 a nd p in 44 ~ pi n 48 AMP (N7010) C4 5 5 C 4 46 C4 3 7 C 45 0
a re Di gi tal s ig na ls. 10/16 change
T he ot he rs ar e An alo g si gn als . footprinter 0 . 1 u_ 1 0 V _X 7 R _ 0 4 * 1 u_ 6 . 3 V _X 5 R _ 0 4 10 u _ 6. 3V _ X 5 R _ 06 *1 0 u _6 . 3 V _ X 5R _0 6 J_SPK1
2 1
U 22
PIN 13 ,PIN34 JD_SENSE F R O N T -L R 3 35 0_04 C4 6 0 1 u _6 . 3 V _ X5 R _0 4 LI N -
LI N +
5
L IN- P V DD
6
AUD G C2 6 4 1 u _6 . 3 V _ X5 R _0 4 9 15 A UD G
L IN+ P V DD 16
F R O N T -R RIN - V DD
R 3 38 0_04 C4 6 2 1 u _6 . 3 V _ X5 R _0 4 17 J _S P K L1
C2 7 0 1 u _6 . 3 V _ X5 R _0 4 RIN + 7 R IN- 4 S P K OU T L + L 22 F C M 1 00 5 K F -1 2 1T 0 3 S P K OU T L + _R
AUD G R IN+ L OU T + . S P K OU T L -_ R 1
Thermal Pad
8 S P K OU T L - L 20 F C M 1 00 5 K F -1 2 1T 0 3 2
SPK_ EN LO U T - .
3 . 3V S 19 8 5 2 04 -0 2 00 1
R3 3 2 10 0 K _ 04 SD # P C B F oo t p ri nt = 8 5 2 04 -0 2 R
A UD G GA I N 0
5 VS R1 9 6 *1 00 K _ 0 4 2 18 S P K O UT R + 3 0 C2 7 7 C 2 84
GA I N 1 3 G AIN0 R OU T + L24
G AIN1
R1 8 9 *1 00 K _ 0 4 14 S P K O U T R - 30 *1 0 m li _ sh o rt 18 0 p _5 0 V _ N P O _0 4 18 0 p _5 0 V _ N P O _0 4
R3 2 7 10 0 K _ 04 1 RO UT -
A UD G G ND
R3 2 8 11
13 G ND 10 A MP _ B Y P A S S
G ND BY PASS FOR E MI
Low mute! 10 0 K _ 04 C 4 54 20
? 6 db 21 G ND 12 C 2 59
C A *0 . 1u _ 1 0V _X 5 R _ 0 4 E X P OS E D P A D NC
19 P C H _ M U T E #
D2 1 * S CS 3 5 5 V Gain Settings N 7 01 0 4 . 7 u _ 6. 3 V _ X 5R _ 06
5
GAIN0 GAIN1 AV(inv) INPUT IMPEDANCE

E A P D _M OD E R 3 36 0 _0 4 E A P D _ MO D E _ R 1
4 SPK_ EN
0
0
0
1
6 dB
10 dB
90 k
70 k
A UDG 6-02-07010-AL0 AU DG
2
2 8 K B C _ MU TE # 1 0 15.6 dB 45 k
U 25 1 1 21.6 dB 25 k
3
M C 7 4V H C 1 G 08 D F T1 G
1 .5 V 4 , 9 , 10 , 1 1 , 21 , 2 3 , 2 9, 3 1 , 3 3, 3 6
3 .3 V 3 , 4 , 12 , 1 4 , 15 , 1 6 , 1 8, 1 9 , 2 0, 2 1 , 2 3, 2 4 , 2 5, 2 9 , 3 0 , 31 , 3 3 , 34 , 3 5
3 .3 V S 2 , 1 0, 1 1 , 1 2, 1 3 , 1 4, 15 , 1 6 , 17 , 1 8 , 19 , 2 0 , 21 , 2 3 , 2 4, 2 5 , 2 6, 2 8 , 2 9, 3 0 , 3 1, 3 5 , 3 6
5V 2 1 , 24 , 3 0 , 31 , 3 3 , 34
5 VS 2 , 1 3, 1 7 , 2 0, 2 1 , 2 6, 30 , 3 1 , 35 , 3 6
B - 28 Audio Codec VIA 1812

Schematic Diagrams
KBC-ITE IT8502E
R3 4 8 *1 5 m li _ sh o rt _ 06 K B C _A V D D L17
V D D3 H C B 1 0 05 K F -1 2 1 T2 0
C 2 16 C2 4 3 C 24 0 C 2 36 C2 0 3
. V D D3 V DD 3
C 2 28 C2 2 9 C2 3 2
0 . 1 u _1 0 V _ X 7R _0 4 1 0u _ 6. 3V _ X 5 R _ 0 6 0 . 1 u_ 1 0 V _X 7 R _ 0 4 0 . 1 u _1 0 V _ X7 R _0 4 0. 1 u _ 10 V _ X 7 R _ 04
0 . 1 u _ 10 V _ X 7R _0 4 *0 . 1 u_ 1 0 V _ X5 R _ 0 4 *0 . 1 u_ 1 0 V _X 5 R _ 0 4
R1 5 4
C 2 37
L 18 1 00 K _ 0 4
H C B 1 00 5 K F -1 21 T 2 0 0. 1 u _ 10 V _ X 7R _ 04 K B C _A G N D
E C _V C C K B C_ W R E S E T #
3 .3 V S .
C2 2 4
121
11 4
12 7
J_ K B 1
11
26
92
74
50
3
U1 2 8 5 20 1 -2 40 5 1 1 u_ 6 . 3 V _ X5 R _ 0 4
VS TBY
VS TBY
VST BY
V CC
AVC C
VST BY
VST BY
VST BY
VBAT
10 58 K B -S I 0 4
1 4, 2 4 L P C _A D 0 LA D 0 K S I 0/ S TB # K B -S I 1
1 4, 2 4 L P C _A D 1 9 59 5
8 LA D 1 K S I1 /A F D# 60 K B -S I 2 6
1 4, 2 4 L P C _A D 2 LA D 2 K S I 2 / I N I T# K B -S I 3
1 4, 2 4 L P C _A D 3 7 61 8
P C L K _K B C 13 LA D 3 K S I3 /S L I N# 62 K B -S I 4 11
18 P CL K _ K B C LP C C L K K S I4 K B -S I 5 1 24
1 4, 24 L P C _ F R A ME # 6 63 12 J_KB1
5 LF R A ME # K S I5 64 K B -S I 6 14
1 4, 2 4 S E RIR Q SE RIR Q LPC K/B MATRIX K S I6 K B -S I 7
EC MODULE CHOOSE (FOR DIFFERENCE K/B TYPE)
4 , 1 8 , 23 , 2 5 B U F _ P L T _R S T # 22 65 15
LP C R S T # / W U I 4/ G P D 2 ( P U ) K S I7
K B C _ W R E S E T# 14 36 K B -S O0 1
W RS T # K S O0 / P D 0 V ER . RX V OL TA GE MO DE L_I D
37 K B -S O1 2
K S O1 / P D 1 K B -S O2
126 38 3 V 1. 0 R1 53 10 K/ R 149 X 3. 3V E4120
19 GA 2 0 GA 2 0 / GP B 5 K S O2 / P D 2
4 39 K B -S O3 7
37 A C_ IN # K B R S T # / GP B 6( P U ) K S O3 / P D 3 K B -S O4
29 LE D _ A C I N # 16 40 9 R1 53 X /R 14 9 1 0K 0V
20 P W U R E Q# / G P C 7 ( P U ) K S O4 / P D 4 41 K B -S O5 10
3 TH E R M _A LE R T # L8 0 L LA T / G P E 7 ( P U ) K S O5 / P D 5 K B -S O6
42 13
23 K S O6 / P D 6 43 K B -S O7 16
30 A P _K E Y # 15 E C S C I # / GP D 3( P U ) K S O7 / P D 7 44 K B -S O8 17 MO D E L _ I D R1 5 3 1 0K _ 0 4
3 0 W E B _E MA I L # E C S M I # / GP D 4( P U ) K S O8 / A C K # V DD 3
45 K B -S O9 18
K S O9 / B U S Y 46 K B -S O1 0 19 R1 4 9 *1 0 K _ 04
DAC
30 C P U _F A N
S 5 _ L A NO N
76
77
78
DA C
DA C
0/ G
1/ G
PJ 0
PJ 1
K S O1 0 / P E
K S O1 1/ E R R #
K S O 12 / S L C T
51
52
53
K B -S O1 1
K B -S O1 2
K B -S O1 3
20
21
22
R N 19
2. 2K _ 4 P 2 R _ 0 4
V DD3
RX Sheet 28 of 40
25 S 5 _ LA N ON 79 DA C 2/ G PJ 2 K S O 13 54 K B -S O1 4 23 S M D_ B A T 3 2
2 3 , 29 W L A N _E N
24
27
3 G_ P O W E R
K B C _ MU T E #
80
81
DA C
DA C
DA C
3/ G
4/ G
5/ G
PJ 3
PJ 4
PJ 5
IT8502E
K S O 14
K S O 15
55 K B -S O1 5 24 S M C_ B A T 4 1
KBC-ITE IT8502E
ADC FLASH VDD 3
B A T_ D E T 66 100
37 B A T _ DE T B A T_ V O LT 67 ADC 0/ G P I0 F L F R A M E #/ G P G2 101 KB C_ S P I_ CE # 3 G _D E T # R 1 43 1 0 K _ 04
C U R _S E N S E _ R ADC 1/ G P I1 F L A D0 /S CE# KB C_ S P I_ S I C C D _D E T #
68 102 R 1 46 1 0 K _ 04
69 ADC 2/ G P I2 F L A D1 /S I 103 KB C_ S P I_ S O
3 TH E R M _V OL T L A N _ C A B L E _ D E TE C T 7 0 ADC 3/ G P I3 F LA D 2 / S O
104
2 5 LA N _ P C I E _ W A K E # 3 G _D E T # 71 ADC 4/ G P I4 F L A D 3/ G P G6 105 KB C_ S P I_ S CL K
24 3 G_ D E T# C C D _D E T # ADC 5/ G P I5 F LC LK / S C K
24 CCD _ DE T # 72 106 CC D_ E N 24
M OD E L_ I D 73 ADC 6/ G P I6 ( P D )F L R S T # / W U I 7 / T M/ G P G0
ADC 7/ G P I7
GPIO 56
S M C_ B A T
SMBUS ( P D )K S O1 6/ G P C 3 S USB # 16 , 2 3 , 31
37 S M C_ B A T 110 57 S USC # 16 , 3 3
S M D_ B A T 111 S MC LK 0 / G PB3 ( P D )K S O1 7/ G P C 5 C2 2 3
37 S M D_ B A T S MD A T0 / G PB4 P CL K _ K B C
115 93 S US _ P W R _ A CK 1 6 R1 6 0 *1 0_ 0 4 P C L K _ K B C _ R
116 S MC LK 1 / G P C1 ( PD )I D 0/ G P H0 94
S M C _ C P U _ TH E R M 1 1 7 S MD A T1 / G P C2 ( PD )I D 1/ G P H1 ME _ W E # 14
3 , 15 S M C _ C P U _ TH E R M 95 A C _ P R E S E N T 1 6 , 18 * 10 p _ 50 V _ N P O_ 06
S M D _ C P U _ TH E R M 1 1 8 S MC LK 2 / G PF6 ( PU ) ( PD )I D 2/ G P H2 96
3 , 15 S M D _ C P U _ TH E R M S MD A T2 / G PF7 ( PU ) ( PD )I D 3/ G P H3 D D _O N _ L A T C H 31
97 W L A N _ D E T# 2 3
( PD )I D 4/ G P H4 98
L C D_ B RIG HT NE S S
PWM ( PD )I D 5/ G P H5 B T _D E T # 29
24 99 D D _O N 31
K B C_ B E E P 25 PW M0 / G P A 0( PU ) ( PD )I D 6/ G P H6
27 K B C_ B E E P PW M1 / G P A 1( PU )
2 9 L E D _ S C R OL L # 28 107 3 G_ E N 24 C2 0 9
29 PW M2 / G P A 2( PU ) ( P D )I D 7/ G P G1 B A T _ V OL T
29 L E D _ N U M# PW M3 / G P A 3( PU ) 3 7 B A T_ V O LT
29 L E D_ C A P # 30 EXT GPIO
31 PW M4 / G P A 4( PU ) 82 1 u _ 6. 3 V _ X 5R _ 04
LOW ACTIVE 2 9 L E D _B A T_ C H G# 32 PW M5 / G P A 5( PU ) ( P D )E GA D / GP E 1 83 S MI # 19
2 9 LE D _ B A T _F U L L# PW M6 / G P A 6( PU ) ( P D )E G C S # / GP E 2 S CI# 19
34 84
29 L E D_ PW R# PW M7 / G P A 7( PU ) ( P D )E G C L K / GP E 3 P W R _B T N # 1 6
8 0 CL K 85
PS/2 WAKE UP 35
23 80 C L K P S 2 C L K 0 / GP F 0 ( PU ) ( P D )W U I 5 / GP E 5 RS M RS T # 1 6
3 IN 1 86 17 S M C _ C P U _ TH E R M
23 3I N 1 8 0 DE T # 87 P S 2 D A T 0 / GP F 1 ( PU ) ( P D )L P C P D #/ W U I 6 / GP E 6 K B C _ R S T# 1 9 4 ,1 9 H _P E C I R1 7 3 *0 _ 0 4
23 8 0 DE T # P S 2 C L K 1 / GP F 2 ( PU )
88 PWM/COUNTER
18 PM E# 89 P S 2 D A T 1 / GP F 3 ( PU ) 47
30 T P_ CL K P S 2 C L K 2 / GP F 4 ( PU ) ( P D )T A C H 0/ G P D 6 CP U _ F A NS E N 30
90 48 MC H _ TS A TN _E C
30 T P _ DA T A P S 2 D A T 2 / GP F 5 ( PU ) ( P D )T A C H 1/ G P D 7
WAKE UP 120
125 ( P D )TM R I 0 / W U I 2/ G P C 4 124 V CO RE _ O N 3 6
37 V C H G_ S E L P W R S W / GP E 4 ( P U ) ( P D )TM R I 1 / W U I 3/ G P C 6 A L L_ S Y S _ P W R G D 1 2 , 16 V DD 3
CIR C2 1 0 KBC_SPI_*_R = 0.1"~0.5"
31 PW R_ S W #
18
RI1 # /W UI0 /G P D0 ( P U ) ( P D )C R X/ G P C 0
119 0 . 1 u _1 0 V _ X7 R _0 4 51 2K bit
21 123
1 2, 3 0 L ID_ S W # RI2 # /W UI1 /G P D1 ( P U ) ( P D )C T X / GP B 2 U9
8 5 K B C_ S P I_ S I_ R 1 4 R N 18 KBC _ S P I_ S I C 2 26 *3 3 p_ 5 0 V _N P O_ 0 4
33
GP INTERRUPT LPC/WAKE UP 19 VD D SI 2 K B C _ S P I _ S O_ R 2 3 15 _ 4 P 2R _ 04 KBC _ S P I_ S O C 2 27 *3 3 p_ 5 0 V _N P O_ 0 4
3 0 W E B _W W W # GI N T/ G P D 5 ( P U ) ( P D )L8 0 H L A T / GP E 0 S W I# 16 SO K B C_ S P I_ CE # _ R 1 KBC _ S P I_ CE #
? ? ? 1 4 R N 17 C 1 97 *3 3 p_ 5 0 V _N P O_ 0 4
112 R1 3 1 1 K _ 0 4 CE # 6 K B C _ S P I _ S C L K _ R2 3 15 _ 4 P 2R _ 04 KBC _ S P I_ S CL K C 1 98 *3 3 p_ 5 0 V _N P O_ 0 4
( P D )R I N G# / P W R F A I L #/ LP C R S T # / GP B 7 C H G_ E N 37 K B C_ F L A S H SCK
UART 3
108 WP #
2 3, 2 9 B T _E N RX D/G P B 0 ( P U ) CLOCK CK 3 2 K E
AVSS
109 2
VS S
VS S
VSS
VSS
VSS
VSS
VSS
12 B K L_ E N TX D / GP B 1 ( P U ) C K 32 K E 128 CK 3 2 K R 1 5 8 4 . 7 K _ 04
C K 32 K K B C _ H O LD #
R 16 5 * 10 M_ 0 4 7 4
I T 85 0 2 E -J H OL D # VSS
1
122
27
91
75
X2
12
49
11 3
E N 2 5 P 05 -5 0 GC P
C M2 0 0S 3 2 7 68 1 2 20 _ 3 2. 7 6 8 K H z
R1 6 4 *0 _ 0 4 E C _V S S 1 4
2 3
C2 3 3 0 . 1 u _1 0 V _ X 7R _0 4 C2 3 8 C 2 31 V DD 3 14 , 2 3 , 25 , 2 9 , 31 , 3 2 , 3 7
3 . 3V S 2, 1 0 , 1 1, 1 2 , 1 3, 14 , 1 5 , 16 , 1 7 , 18 , 1 9 , 20 , 2 1 , 23 , 2 4 , 2 5, 2 6 , 2 7, 2 9 , 3 0, 3 1 , 3 5, 3 6
0 _0 4 FO R I T8 51 2CX /E X 1 2p _ 5 0V _N P O_ 0 4 1 2 p _5 0 V _ N P O _0 4
0 .1 U_ 04 FO R IT E85 12 -J (I TE8 50 2- J W/ 0 CI R) N C3 S HO RT
E C Co st Do wn
R1 4 7 * 10 m i _l s ho rt L C D_ B RIG HT NE S S K B C _ A GN D
12 B RIG HT NE S S
C2 1 9 *0 . 1 u_ 1 0 V _X 5 R _ 0 4
KBC-ITE IT8502E B - 29
Schematic Diagrams
LED, MDC, BT
3 V_ BT
Bluetooth(Port8) 3 .3 V
COSTDOWN J _B T1
Port 11 1
2
18 U S B _P N 1 1 3
MJ_MDC1
20 MIL 1. 5 V
R3 4 4
18 U S B _P P 11 4
11 28 B T _ DE T # B T_ E N # 5
12 23 B T_ E N #
R 16 3 *1 5 m li _ sh o rt _ 06 47 K _ 0 4 6
2 1 3 .3 V 8 7 2 12 -0 6 G0
3 .3 V R3 0 2 *0 _ 04
B T _ DE T # 15 P C H _ B T_ E N #
J _ MD C 1
1 2 R 1 62 *0 _ 06 3 .3 V
R1 6 1 3 3_ 0 4 H D A _ S D O U T _ R 3 GN D RE S E R VE D 4 C4 7 3 R3 0 3
From EC default HI
1 4 , 27 H D A _ S D O U T
5 A za l ai _ S D O
GN D
RE S E R VE D
3 . 3V Ma ni / a u x
6 M D C _3 . 3 V 10mil L1 6 *1 5m i l _s h o rt _0 6 3. 3 V
R1 5 7 3 3_ 0 4 H D A _ S Y N C _ R 7 8 * 18 0 p _5 0 V _ N P O _0 4 1 0K _0 4 3 V _B T
1 4 , 27 H D A _ S Y N C A za l ai _ S Y N C G ND R3 0 1
R1 5 5 2 2_ 0 4 H D A _ S D I N 1_ R 9 10 50m il 50m il
14 H DA _ S DIN 1 R1 5 1 3 3_ 0 4 H D A _ R S T # _R 11 A za l ai _ S D I G ND 12 H D A _B I T C LK _ R R 14 8 3 3 _ 04 B T_ E N #
1 4 , 27 H D A _ R S T # A za l ai _ R S T # A z al i a_ B C LK H D A _B I T C LK 1 4 , 2 7
D
8 8 01 8 -1 20 G C2 2 5 C 22 0 * 15 m i _l s h ort _ 0 6
Q1 7 C4 7 4 C 40 9 C 4 07
0 . 1u _ 1 0V _ X 7 R _ 0 4 2 2 p_ 5 0 V _N P O_ 0 4 G MT N 70 0 2 Z H S 3
2 3, 28 BT_ EN
1 0 u_ 6 . 3 V _X 5 R _ 0 6 1 0 u _6 . 3 V _ X5 R _0 6
1 80 p _5 0 V _ N P O _0 4
S
U2 1
G ND 4 1
V IN V OU T
5
V IN
B T _E N 3 2
EN G ND
* G5 2 43 A
Sheet 29 of 40 PN:G5 24 3A-- 6-0 2- 05 243 -9 C0
LED, MDC, BT LED 3 .3 V S 3 .3 V S 3. 3 V S 3. 3 V S

3. 3 V S 3 .3 V S V DD 3 V DD 3 V D D3 V D D3
E
R 6 R5 R1 9 2 R1 9 3 R 19 5 R 19 4
B R2 R 3 R 4 2 2 0_ 0 4 2 2 0_ 0 4 2 20 _ 0 4 2 20 _ 04 2 2 0_ 0 4 2 2 0_ 0 4
S A T A _L E D # 14
Q 3 22 0 _ 04 2 2 0_ 0 4 2 2 0 _0 4 POWER ON BAT LED
C
D T A 1 14 E U A BT WLAN
3
1 LED
R1 LED 1 3 D1 LED D 12 D1 3
SG
2
HDD/ODD NUM CAPS SCROLL
SG
SG
Y
Y
22 0 _ 04 D 3 D4 D5 2 4 R Y -S P 15 5 H Y Y G 4 R Y -S P 1 5 5 H Y Y G4 R Y -S P 15 5 H Y Y G 4
LED LOCK LOCK LOCK
4
R Y -S P 1 72 Y G 34
R Y -S P 1 7 2 Y G3 4
R Y -S P 17 2 Y G3 4
LED LED LED
A
D 2
C
R Y -S P 1 72 Y G 34
L E D_ P W R # 2 8 L E D _B A T _ F U L L # 28
B
W L A N_ E N 2 3, 2 8
L E D _A C I N # 2 8 LE D _ B A T _C H G # 2 8
C
Q2
L E D _ N U M# 2 8 L E D _C A P # 28 L E D _ S C R OL L # 28 D TC 11 4 E U A
E
C
B
BT_ EN 2 3, 2 8
Q 1
4 , 9 , 10 , 1 1 , 21 , 2 3 , 27 , 3 1 , 33 , 3 6 1. 5V
D TC 1 14 E U A
E
3 , 4, 1 2 , 1 4, 1 5 , 1 6, 18 , 1 9, 20 , 2 1 , 23 , 2 4 , 25 , 3 0 , 31 , 3 3 , 34 , 3 5 3. 3V
14 , 2 3 , 25 , 2 8 , 31 , 3 2 , 37 V D D 3
2, 1 0 , 1 1, 1 2 , 1 3, 1 4 , 1 5, 1 6 , 1 7, 1 8 , 1 9, 20 , 2 1, 23 , 2 4 , 25 , 2 6 , 27 , 2 8 , 30 , 3 1 , 35 , 3 6 3. 3V S
H2 H1 H 12 H 10 H 8
C 1 5 8 D 1 58 C 1 58 D 1 5 8 H 6_ 3 D 3 _ 8 H 6_ 3 D 3 _ 8 H 6 _3 D 4_ 4 H 11 H7 H2 4 H 27 H1 5 H1 4
9 9 9 9 9 9
3 8 3 8 3 8 3 8 3 8 3 8
4 1 7 4 1 7 4 1 7 4 1 7 4 1 7 4 1 7
M2 M6 M7 M8 M1 5 6 5 6 5 6 5 6 5 6 5 6
M-M A R K 1 M -MA R K 1 M-MA R K 1 M-M A R K 1 M -MA R K 1
MT H 3 1 5D 1 11 MT H 3 1 5 D 1 11 MT H 31 5 D 1 1 1 MT H 3 1 5D 1 11 MT H 31 5 D 1 1 1 M TH 3 15 D 1 1 1
H 20 H 16 H 13 H1 7 H 19 2009/11/5
M5 M3 M4 H 6 _0 D 3_ 7 H 6_ 0 D 3 _ 7 H 6_ 0 D 3 _ 7 H 4 _ 7 B 6_ 0 D 3 _ 7 H 4_ 7 B 6 _0 D 3_ 7 H 9 H4 H 5 H3 H2 6
M-MA R K 1 M-M A R K 1 M -MA R K 1 9 9 9 9 9
3 8 3 8 3 8 3 8 3 8
4 1 7 4 1 7 4 1 7 4 1 7 4 1 7
5 6 5 6 5 6 5 6 5 6
MT H 3 1 5D 1 11 MT H 31 5 D 1 1 1 MT H 3 1 5D 1 11 MT H 31 5 D 1 1 1 M TH 3 15 D 1 1 1
H 25 H 6 H 23 H2 2 H2 1 H 18
C 6 7D 6 7 C 67 D 67 C 15 8 D 1 5 8 C1 5 8 D1 5 8 H 4 _ 0B 7_ 0 D 3 _ 7 H 4_ 0 B 7 _0 D 3 _ 7
B - 30 LED, MDC, BT
Schematic Diagrams
USB, Fan, TP, Multi Con1
USB PORT*2(Port 0,Port1) FAN CONTROL

5 V S _F A N 5 VS U1 9
U4 F O N# 1 8
5V U S B _F L G # 5 6 U S B V C C 01 2 F ON GN D 7
F L G # V OU T1 V IN GN D
100 MIL 3 6
2 7 4 V OU T GN D 5
VIN 1 V OU T2 28 CP U_ F A N VSET GN D
C 10 0 3 8 C1 1 7 C 12 8 C 13 5 G9 9 0 P 11 U
VIN 2 V OU T3
1 0 u_ 6 . 3 V _ X5 R _ 0 6 4 1 0 . 1u _ 1 0V _ X 7 R _ 0 4 0 . 1 u_ 1 0 V _X 7 R _ 0 4 * 10 u _ 6. 3 V _ X 5R _0 6
EN # GN D
31 , 3 3 D D _O N # R T 97 1 5 B GS
5 VS 5V S _F A N
J _F A N 1
1
C4 0 2
US B V C C0 1 C 4 01 2
3
0 . 1u _ 1 0V _ X 7 R _ 04
L 10 U S B _ V C C 0 1_ 0 1 0 u _6 . 3 V _ X5 R _0 6 8 5 2 05 -0 3 70 1
H C B 16 0 8 K F -1 21 T 25 60 mil
.
+C 9 8 C8 7
1 00 u _ 6. 3 V _ B _ A 0. 1 u _ 10 V _ X 7R _0 4 Port 0 28 C P U _ F A N S E N
R2 7 3 4 . 7 K _0 4
3 .3 V S
JFAN
1
J _U S B 1
V+
3
1
Sheet 30 of 40
18
18
U S B _ P N0
US B _ P P 0
4
1
L9
2
3
*W C M2 0 1 2F 2 S -1 6 1T 0 3 -sh o rt
2
3
DA T A _ L
DA T A _ H CLICK CONN FO R CL IC K BO AR D
USB, Fan, TP,
Multi Con
GN D 1
G ND2
GN D 3
G ND4
4
GN D
3 .3 V 3 .3 V
C 1 07 7 0 -10 4 A 3
GN D 1
G ND2
GN D 3
GN D 4
R7 4 R 77 5 V S _T P
1 0K _ 0 4 *1 0 K _ 04 U S B _ V CC0 1 _ 0
R9 4 *1 5m i l _s h or t _0 6
U S B _ F L G# 5 VS
18 U S B _ OC # 0 1
80 mil C1 6 4 C 1 69
R7 3 R 85 R 84
*0 _ 04 *1 0 u _6 . 3 V _ X5 R _0 6
C1 3 6 C 1 77 J _T P 1 1 0 K _0 4 1 0 K _ 04 1u _ 6 . 3V _ X 5 R _ 04
+
10 0 u _6 . 3 V _ B _ A 0 . 1 u _1 0 V _ X7 R _0 4 1
2 TP _ D A TA 28
TP _ C LK 28
Port 1 3
4
8 5 20 1 -04 0 5 1
C 15 9 C 15 5
J _ US B 2 4 7 p_ 5 0 V _N P O_ 0 4 4 7 p_ 5 0 V _N P O_ 0 4
1
V+
18 U S B _ P N1 4 L1 3 3 2
D A TA _ L
18 US B _ P P 1 1 2 3
*W C M2 0 1 2F 2 S -1 6 1T 0 3 -sh o rt D A TA _ H
POWER SWITCH CONN.

G ND 1
GN D 2
G ND3
GN D 4
4
G ND
C 1 0 7 70 -1 0 4A 3
CLOSE TO J_SW1
G ND 1
GN D 2
G ND3
GN D 4
FO R PO WE R SW IT CH B OA RD AP_ KEY#
AP_ KEY # 2 8
3 . 3V S 3 .3 V
3 .3 VS 3 . 3V
D
C2 0 C1 9 Q 6 J _ SW 2
G
2 0m il
Audio/B CONN.(Port 2) MT N 7 0 0 2Z H S 3 1
2
S
5V 0 . 0 1u _ 5 0V _ X 7 R _ 04 0 . 01 u _ 50 V _ X 7R _0 4 M BTN R1 7 1 00 K _ 0 4 M _B TN #
3 W E B _W W W #
1.1A 60mils 4 W E B _E M A I L #
C 2 22 0 . 0 1 u_ 5 0 V _X 7 R _ 0 4 J_ S W 1 5 L I D _S W #
2 0m il 6
F OR A UD IO B OA RD 1
2 M _ B TN # _R
R 20 1 00 K _ 0 4 7
8
A P _K E Y #
J _ A U D I O1 M _B T N # 31
R1 5 0 * 1 5m i l_ s h ort _ 0 6 3 W E B _W W W # 8 8 4 86 -0 80 1
M I C 1 -R 1 4 W E B _E MA I L # W EB_ W W W # 2 8
27 M I C 1 -R 2 5 W E B _ EM A IL # 2 8
27 M I C 1 -L M IC1 -L L I D _S W #
3 6 L I D _ S W # 1 2, 2 8
H E A D P H ON E -R 4 7 A P _O N
2 7 H E A D P H O N E -R 5 8 A P _O N 31
H E A D P H ON E -L
2 7 H E A D P H O N E -L M IC_ SE NS E 6 9 3 , 4 , 1 2, 1 4 , 1 5, 1 6 , 1 8, 1 9 , 2 0, 2 1 , 2 3, 2 4 , 2 5, 2 9 , 3 1, 3 3 , 3 4, 3 5 3 . 3V
27 M I C _ S E N S E SPK_ H P# 7 10 VIN 2, 1 3 , 1 7, 2 0 , 2 1, 2 6 , 2 7, 3 1 , 3 5, 3 6 5 V S
U S B N4 _ R H P _S E N S E 8 2 1, 2 4 , 2 7, 3 1 , 3 3, 3 4 5 V
18 U S B _P N 4 R 1 69 *1 0 mi l _ sh o rt 27 H P _S E N S E
U S B N4 _ R 9 *5 0 50 0 -01 0 4 1-0 0 1 L
U S B P 4 _R U S B P 4 _R 10 1 2, 3 1 , 3 2, 3 3 , 3 4, 3 5 , 3 6, 3 7 V I N
18 U SB_ PP4 R 1 71 *1 0 mi l _ sh o rt 2 , 1 0, 1 1 , 1 2, 1 3 , 1 4, 1 5 , 1 6, 1 7 , 1 8, 1 9 , 2 0, 2 1 , 2 3, 2 4 , 2 5, 2 6 , 2 7, 2 8 , 2 9, 3 1 , 3 5, 3 6 3 . 3V S
11
S P K O UT R+ 12
27 S P K O U T R + 13
27 S P K O U T R - S P K O UT R-
14
8 7 21 3 -1 40 0 G
If system has APON function, uses J_SW1

If system has no APON function, uses J_SW2
USB, Fan, TP, Multi Con1 B - 31

Schematic Diagrams
5VS, 3VS, 1.05VS
VA V IN V IN 1
S Y S 5V SY S5 V
PC 6 5 P C 64 PC 6 3
0 . 1 u _5 0 V _ Y 5 V _ 0 6 0 . 1 u_ 5 0 V _ Y 5 V _ 0 6 0 . 1 u _ 50 V _ Y 5V _0 6
ON P R1 9 3 P R1 9 4
DD_ON "L " TO
PU 3 1 0 K_ 0 4 10 K _ 0 4
1 8 "H" FROM EC
VA VA V IN1 V IN 1
2 7 D D _ ON # S US B
V IN VIN D D _ ON _L A T C H D D _O N _ L A T C H 28 D D _ ON # 3 0 ,3 3
3 6
30 M _B TN # M_ B T N # P W R_ S W # PW R _ SW # 2 8
P Q4 5 A 6 P Q4 5 B 3
P_ SW 1 4 5 P R 85 MT D N 7 0 02 Z H S 6 R D MT D N 7 0 0 2Z H S 6 R D
30 A P _ ON I N S T A N T -ON GN D
*T J G -53 3 -S -T / R 1 0 K _ 04
2 1 P 2 8 08 A 1 2 G P C1 8 9 5 G P C1 9 0
V DD 3 28 D D _O N S 1 6 , 2 3, 2 8 S US B # S
4 3 ON
1 * 0 . 1 u_ 1 0 V _ X5 R _0 4 4 *0 . 1 u_ 1 0 V _ X 5R _ 04
P R 19 2 ON P R 1 95
6
5
DEBUG USE
1 0 0K _ 0 4 1 0 0K _0 4
EVT? ? ?
5V
ON
ON
C2 1 2 C2 7 6 C9 7
Sheet 31 of 40 0 . 0 1u _ 5 0 V _X 7 R _0 4 0 . 0 1u _ 5 0V _X 7 R _ 0 4 0. 0 1 u _ 50 V _ X 7 R _ 0 4
5VS, 3VS, 1.05VS

5V 5VS 1.5VS
P Q 47 NMO S
S Y S 1 5 V V D D5 P 1 2 03 B V S Y S 1 5V V D D5 P Q4 6 5 VS SYS1 5 V 1 .5 V
NMO S 1 .5 V S
8 5V P 12 0 3 B V P Q1 6
7 3 8 P 1 20 3 B V
3A 6 2 3A 5V 7 3 8
PR 9 8 5 1 Power Plane P R 97 6 2 P R1 9 7 7 3
5 1 6 2
1 M _0 4 1 M_ 0 4 1M _ 04 5 1
4
P C1 9 3 P C 19 2 P C 1 91
4
Z 3 5 06 Z 3 50 7 P R 19 6
4
6 0 . 1 u _ 10 V _ X 7 R _ 0 4 1 .5 V S _ E N 0 . 1 u_ 1 0 V _ X7 R _ 04 1 0 u_ 6 . 3 V _ X 5R _ 0 6
D PQ 1 5 A 3 1 00 _ 1 % _0 4
P C 74 M T D N 70 0 2 Z H S 6R P C 73 D P Q1 5 B
2 G D D _ ON # M T D N 7 00 2 Z H S 6R P C1 9 4 6 3Z 3 5 1 5
4 7 0 p_ 5 0 V _ X7 R _ 04 S 4 7 0p _ 5 0V _X 7 R _ 0 4 5 G D P Q4 8 A D
S USB 33
1
1 S 22 0 0 p _5 0 V _ X 7R _ 04 M T D N 7 00 2 Z H S 6 R P Q 48 B
S US B
1
PJ 1 1 4 2 G 5 G M TD N 7 0 0 2Z H S 6 R
P J1 2 S S
4 0 m il 1 4
2
4 0m i l
2
VA 37
1. 5V S _C P U 4, 7
3 .3 V S
ON ON 1. 5V 4 , 9, 10 , 1 1 , 2 1, 2 3 , 2 7 , 2 9, 3 3 , 3 6
1. 5V S 2 0, 2 3 , 3 6
3 .3 V
SYS5 V 3 2, 3 7
5V 2 1, 2 4 , 2 7 , 3 0, 3 3 , 3 4
3. 3V 3 , 4, 12 , 1 4 , 1 5, 1 6 , 1 8 , 1 9, 2 0 , 2 1 , 2 3, 2 4 , 2 5 , 29 , 3 0 , 3 3 , 34 , 3 5
C 13 7 C 105 C 1 90 V IN1 32
0 . 0 1 u_ 5 0 V _ X7 R _ 04 0 . 0 1 u _5 0 V _ X 7 R _ 0 4 0 . 0 1 u_ 5 0 V _ X 7R _ 04 1.5VS_CPU V IN
V DD 5
1 2, 3 0 , 3 2 , 3 3, 3 4 , 3 5 , 3 6, 3 7
32
3.3V 3.3VS 1 .5 V
PJ 4
O P E N _2 A
1 . 5V S _ C P U
PJ3 MUST SHORT

V DD 3
3. 3V S
SYS1 5 V
1 4, 2 3 , 2 5 , 2 8, 2 9 , 3 2 , 3 7
2 , 10 , 1 1 , 1 2 , 13 , 1 4 , 1 5 , 16 , 1 7 , 1 8, 19 , 2 0 , 2 1, 2 3 , 2 4 , 2 5, 2 6 , 2 7 , 2 8, 2 9 , 3 0 , 35 , 3 6
32
5V S 2 , 13 , 1 7 , 2 0 , 21 , 2 6 , 2 7 , 30 , 3 5 , 3 6
2 1
P Q 41
P 1 2 03 B V S Y S 15 V NMO S SY S1 5 V
S Y S 1 5 V V D D3 8 3 .3 V VDD 3 P Q1 3 3. 3V S PQ 3
7 3 P 1 2 03 B V * P 1 20 3 B V
NM OS
3A 6 2 3A 8 8 P R 60
5 1 Power Plane PR9 6 7 3 PR 6 3 7 3
P R 1 74 6 2 6 2 *2 2 0 _ 04
1 M_ 0 4 5 1 * 1M _ 04 5 1
4
1 M _0 4 P C 70 PC 7 2 P C2 8 PC 2 7
Z 35 1 6
P R9 5
4
4
Z 3 5 08 Z 35 0 9 0 . 1 u_ 1 0 V _ X 7R _ 04 1 0 u _6 . 3 V _ X 5 R _ 0 6 1 .5 V S _ CP U E N *0 . 1 u_ 1 0 V _ X5 R _ 04 * 10 u _ 6 . 3 V _X 5 R _0 6
* 1 00 _ 0 4
6 PQ 1 4 A
P C 1 70 D M T D N 70 0 2 Z H S 6R PC7 1 3 Z 35 1 0 PC 2 9 6 3
D D P Q1 2 D P Q 2A D P Q2 B
2 2 0 0p _ 5 0 V _X 7 R _0 4 2 G D D _ ON # 2 20 0 p _ 50 V _ X 7 R _ 0 4 * MT N 70 0 2 Z H S 3 * 22 0 0 p _5 0 V _ X 7R _ 04 *2 N 7 00 2 K D W *2 N 7 0 0 2K D W
S 5 G SU SB G 2 G SU SB 5 G
1 S S S
S
4 1 4
P Q1 4 B
M T D N 70 0 2 Z H S 6R
ON ON
B - 32 5VS, 3VS, 1.05VS

Schematic Diagrams
Power 3.3V/5V
S Y S 5V
PC 1 6 8 C A
SY S5 V
0 . 0 1u _ 5 0 V _ X 7R _ 04
L G ATE1 Z 3 6 13 PD 6 RB 0 5 4 0 S 2
C9 4
A C
V IN 1 VI N 0 . 0 1u _ 5 0 V _ X7 R _ 04 SY S1 0 V
PD 5 RB 0 5 4 0 S 2 P C1 6 4
Z 3 6 04 P R1 8 6 2_06
A C 2 20 0 p _ 50 V _ X 7 R _ 0 4
P C1 8 4 P C1 8 5 PC 1 6 9 C A
2. 2 u _ 1 6 V _ X5 R _ 06 1 00 0 p _ 5 0V _X 7 R _ 0 4 P R 1 78 P D 1 6 R B 0 5 4 0S 2 0 . 0 1u _ 5 0 V _ X 7R _ 04
I N TV C C 2 Z 3 6 14 PD 4 RB 0 5 4 0 S 2
6 -1 3- 42 23 1 -2 8B 2 _ 06
A C
SY S1 5 V
P R1 8 5 4 2 2 K _ 1 %_ 0 6 S G ND 4 Z 3 6 05
PD 3 RB 0 5 4 0 S 2 P C1 6 5
Z 3 60 6
P R 18 7 2 20 0 p _ 50 V _ X 7 R _ 0 4
PR 1 7 2 P R1 7 7 7 5K _0 4 P C4 8 P C5 3 P C5 4
PU8 P C1 8 2
21
5
1 0 K_ 0 4 20 K _ 1 % _ 0 4 1u _ 2 5 V _ 08
4 . 7u _ 2 5 V _ X 5 R _ 0 8
4. 7 u _ 2 5V _X 5R _ 0 8
0. 1u _ 5 0 V _ Y 5 V _ 06
N C
FB
V DD A
V O UT
FBL
PAD
S GN D 4 S G ND 4
Z3602 20 6 Z 3 60 7
E NL VIN
Z3603 19
RT O N V L DO
7
Z 3 60 8
P C1 7 3
1 u_ 2 5 V _ 0 8
IN T V CC 2
VDD5
5
6
7
8
18 8
A GN D SC418 BST PQ 1 0 S YS5 V V DD 5
Z3601 17 9 Z 3 60 9 4 I R F 8 7 07 P B F P L8
E N/P S V DH P J 19
4 . 7 U H _ 6 . 8* 7 . 3 *3 . 5
5A
Sheet 32 of 40
1
2
3
16 1 0 Z 3 61 0 1 2 1 2
P G O OD
IL IM LX
PG N D
V DD P
RP S V
PC 1 7 4 P C1 8 0 P R1 8 0 P C1 7 6 P R 17 5 * OP E N -5 m m
D L
5
6
7
8
Power 3.3V/5V
C
1 0 0 0 p_ 5 0 V _ X 7 R _ 0 4
P Q6 P R 19 8 P C 1 86 PR 1 9 0
*0 . 1 u _1 0 V _ X 5 R _0 4
15
14
12
11
LG A T E 1 4 I RF 8 7 0 7 P B F PD 7
13
*2 . 2 _ 0 6 * 2 20 p _ 5 0V _0 4 9 1 K _ 1 %_ 0 6
1 u _ 2 5V _0 8
10 K _ 0 4
1 37 K _ 1 % _ 0 4
OCP
1
2
3
S K 3 4S A
P C 16 6 P C5 5 P C 1 71
A
Z3611 P R1 7 3 1 0K _1 % _ 0 4 P C 19 5 + + P R1 9 1
0 . 1 u _5 0 V _ Y 5V _0 6 * 1 5m i l _ sh o rt _ 0 6
PR 1 6 8 Z3612 P R1 6 9 *1 0 0 K _ 04 P C 1 87 PR 1 8 3 *1 5 0 u _6 . 3 V _ V _ A 1 5 0 u _ 6. 3 V _ V _ A
*2 2 0 0 p_ 5 0 V _ X 7R _ 0 4
11 3 K _ 1 % _ 04 P C1 6 7 P C 1 78 * 1 00 p _ 5 0 V _ N P O _ 04 1 0 K _ 1 %_ 0 4
S G N D4
SG ND 4 S G ND 4 S GN D 4 S G ND 4 1u _ 2 5 V _ 08 1 u _2 5 V _ 0 8
S GN D 4
S YS5 V INT V C C2
P R1 8 4 P R1 8 2
0_06 *0 _ 06
PR 1 7 0 *9 . 1 K _ 0 4
SY S5 V
A
P R 18 9 V IN
P D1 7 *1 5 m i _l s h o rt _ 06
OCP R B 0 5 4 0S 2
10 0 p _ 5 0V _N P O _0 4
Ra P C5 8 PC 5 6 P C 57
C
P R1 7 1 1 0 K _ 1 % _0 4
5
6
7
8
4 . 7 u_ 2 5 V _ X 5 R _ 0 8
P R1 7 6 P R 1 81
P C 18 8
Z 3 6 25
Z3618 4 0. 1u _ 5 0 V _ Y 5 V _ 0 6 4 . 7 u _ 25 V _ X 5 R _ 0 8
1 0 K_ 0 4 1 0 K _ 1% _ 0 4 P R1 7 9
VDD3
1
2
3
0_04 PC 1 7 9 PQ 7
PU 9 I R F 87 0 7 P B F
13
14
16
15
S C 4 12 A 0 . 1 u _ 50 V _ Y 5 V _ 06 S YS3 V
PJ 1 8 V D D3
5A
D H
IL IM
N.C
N.C
Z3615 12 1 Z3619 1 2 1 2
EN LX
11 2 Z3620 PL 9 * OP E N -5 m m
P GD B ST 4. 7 U H _ 6 . 8 *7 . 3 *3 . 5
C
5
6
7
8
Z3616 10 3 Z3621 PR 2 0 1
V OU T VC C
P Q4 2 PD 1 4 P C4 6 PC 4 5 P C1 7 5
Z3617 9 4 Z3622 4 I RF 8 7 0 7 P B F * 2 . 2_ 0 6 + +
FB D L
S K 3 4S A *1 5 0 u_ 6 . 3 V _ V _ A 1 5 0 u _6 . 3 V _ V _ A 0. 1 u _ 5 0 V _ Y 5 V _ 0 6
G ND
1
2
3
N .C
RT N
P C1 8 3 Rb 17
N.C
PAD P C 18 1 PC 1 9 6
P C1 7 2 P R 1 88 P C1 7 7
*4 7 p _5 0 V _ N P O_ 0 4
1 u_ 2 5 V _ 0 8
0 . 0 1 u _ 50 V _ X 7 R _ 0 4 2 . 9 4 K _ 1% _ 0 4 0 . 0 1 u _ 50 V _ X 7 R _ 0 4 * 2 20 0 p _ 50 V _ X 7 R _ 0 4
2009/11/17
V I N1 31
SY S1 5 V 31
V D D3 14 , 2 3 , 2 5 , 2 8, 29 , 3 1 , 3 7
V D D5 31
SY S5 V 31 , 3 7
VI N 12 , 3 0 , 3 1 , 3 3, 34 , 3 5 , 3 6 , 37
Power 3.3V/5V B - 33
Schematic Diagrams
Power 1.5V/0.75V/1.8VS
5V 3 .3 V
V D DQ V IN
P R7 5
A
P R 81 P R8 3 1 00 K _ 0 4
P D2
( 1 .5 V= 1 .5 17 V ) 1 . 5 M_ 0 4 1 0_ 0 6 R B 0 5 40 S 2
P U2
C
P R8 2 1 0 _0 6 Z3 80 1 3 7 D D R 1 . 5 V _ P W R GD
V D D QS P GD D D R 1. 5 V _ P W R GD 16
Ra VIN
PC 5 9 P C6 0 P C 51
P R8 4 Z3 80 2 2
0. 1 u _ 5 0V _ Y 5 V _ 0 6
0 . 1u _ 5 0V _Y 5 V _ 0 6
1 0 0 p_ 5 0 V _ N P O _0 4 1K _0 4 1 u _ 25 V _ 0 8 1 u_ 2 5 V _ 08 T ON
P R7 8
Z3 80 3 6 *1 5 m i _l s h ort _ 0 6
FB
8 24 Z3812 Z 38 1 3
RE F BST +P C 1 61
P C 15 6
P C 1 57
P R 73 Z3 80 5 9 PC 4 7
C O MP
5
6
7
8
P R7 6 0 . 1 u _5 0 V _ Y 5 V _ 0 6 PQ 3 8 1 5 u_ 2 5 V _ 6. 3 * 4. 5 _ E L N A
1 0 _0 6 PC 4 4 *1 5 m i _l s h ort _ 0 6
P R 72 Rb 23 Z3814 Z 3 8 15 4 MD S 2 65 9
P R7 7 *0 . 1 u _1 0 V _ X5 R _0 4
DH
1.5V
1
2
3
1 0_ 0 6 10 0 K _ 1 %_ 0 4 Z3 80 6 1 0
1 0 0 0 p_ 5 0 V _X 7R _ 04
V T TS P R 74
Z3808 Z3 80 7 5 21 Z3816 OCP V D DQ
VCC A IL IM PL 6 2 . 5 U H _ 10 * 10 * 5 PJ 5
P C 42
P C3 8
PR 6 7
P C 52 7. 1 5 K _ 1 %_ 0 4
22 Z3817 8A 1 2
P C5 0
Sheet 33 of 40 LX 1 .5 V
1 u_ 2 5 V _ 08 * 0 . 06 8 u _5 0 V _ 0 6 *1 5 m i l_ s h ort _ 0 6 19 Z3818 P Q 36 OP E N _ 8 A
D L
5
6
7
8
5
6
7
8
1 u _2 5 V _ 0 8
5 60 u _ 2 . 5V _6 . 6 *6 . 6 *5 . 9
VTT_MEM
C
VSSA
P C1 5 0
4 MD S 2 6 55 P Q 37 + P C 1 46 P C 15 3 P C 1 55
Power 1.5V/0.75V/ PJ 1 6
1.5A
Z3 80 9 1 4
VSSA
VT T VDD P 1
20 5V
4 4
*M D S 2 6 5 5
PD 1 3 +
* 22 0 u _2 . 5 V _ B _ A 0. 1 u _ 50 V _ Y 5V _ 0 6 0 . 0 1 u_ 5 0 V _ X7 R _0 4
1
2
3
1
2
3
2 1 15 S K 34 S A
V TT _ ME M VT T
* 1 0u _ 6 . 3 V _X 5R _ 06
PC4 0
10 u _ 6. 3 V _ X 5 R _ 0 6
1.8VS
A
O P E N _2 A 12
1 0u _ 6 . 3V _X 5 R _0 6
V DD Q VDD P 2
13 1u _ 2 5 V _0 8
VDD P 2
*1 0 u_ 6 . 3 V _ X 5 R _ 0 6
PC 1 5 8 PR 6 6 25
PC 3 6
P C3 4
P C 35
+ P C3 9 P GN D 2
PC 3 7
1 18
* 2 20 u _ 2. 5 V _ B _ A EN/P S V P GN D 1 16 P R 1 65
* 2 0K _ 1 % _ 04 11 P GN D 1 17 *1 5 m il _ s ho rt _ 0 6
1 u _ 2 5V _ 0 8 V T TE N P GN D 2 V SSA
S C4 8 6
P R7 9 4 7K _ 0 4 1 .5 VE N
5V
3
D
D
P Q9 B PC 4 9
Z 3 81 9 5
P R8 0 1 0 0 K _0 4 G MT D N 7 00 2 Z H S 6R PQ 8
6 S G 0 . 1 u _5 0 V _ Y 5 V _ 0 6
4
1
D * MT N 70 0 2 Z H S 3
DDR3 VDDQ --> 1.5V ( V POWER)
S
PJ 7
G 2
1 6 ,2 8 S US C# S 4 0 m il
1
2
P Q9 A
MT D N 7 0 02 Z H S 6 R
3 0 ,3 1 D D_ O N#
PR 6 9 1 0 0K _ 0 4
330uF*3 , 10uF*6
5V
4 , 16 , 3 4 1 . 1V S _ V TT _ P W R GD PR 7 0 *1 0 0 K _ 04 V TT E N VTT-->0.75V ( VS POWER)
PR1 6 6 10 0 _ 04 6
V T T _M E M
3
D SU SB G
D
2
P Q5 A
2N 7 00 2 K D W
P C 43
0 . 1 u_ 5 0 V _ Y 5 V _ 06
10uF*3, 1uF*4
P Q5 B S
S USB G 5 2 N 7 0 02 K D W 1
31 SUS B
S
4
ON
? ? ? ? PIN6?
5V
3 .3 V
P C1 6 0 1.8VS
2A PU7 1 u_ 2 5 V _ 08
VS 1 .8 1 . 8V S
5 6
9 V IN
V IN
V C N TL 3A PJ 6
3 .3 V PR1 6 7 1 0K _0 4 1 . 8V S _P W R G D 7 4 1 2
P OK V OU T
1 0 u_ 6 . 3 V _ X 5 R _ 0 6
0 . 1 u _1 0 V _ X 7 R _ 0 4
3 O P E N _3 A
10 u _ 6 . 3V _ X 5 R _0 6
EN1 .8 VS V OU T
5V P R6 8 10 K _ 0 4 8 P R1 6 3
E N 1 . 27 K _ 1 % _0 4
1 2
G ND VFB
D
PC 3 3 P C1 5 1
P Q4 7 ,2 0 1. 8 V S
AX6610 1 2, 3 0 , 3 1 , 32 , 3 4 , 3 5, 3 6 , 3 7 VIN
PR 7 1 6 2 K _1 % _ 0 4 G * 1u _ 2 5V _0 8 P C1 5 2 P C 15 9
31 S US B MT N 70 0 2 Z H S 3 8 2p _ 5 0V _ N P O_ 0 4 2 1 , 24 , 2 7 , 3 0, 3 1 , 3 4 5V
3 , 4 , 1 2 , 14 , 1 5 , 1 6, 1 8 , 1 9 , 20 , 2 1 , 2 3, 2 4 , 2 5 , 29 , 3 0 , 3 1, 3 4 , 3 5 3. 3 V
S
1 0 u_ 6 . 3 V _ X 5R _ 0 6
0 . 1 u _ 50 V _ Y 5 V _ 06
P C 41 PR1 6 4 4 , 9 , 1 0, 1 1 , 2 1 , 23 , 2 7 , 2 9, 3 1 , 3 6 1. 5 V
P C 14 8
P C1 4 7
P C 1 49
1 0 , 11 V T T_ M E M
GS7113 1K _1 % _ 04
* 0. 1 u _ 50 V _ Y 5V _ 0 6
6-02-07113-320
AX6610
6-02-06610-320
B - 34 Power 1.5V/0.75V/1.8VS
Schematic Diagrams
Power 1.1VS_VTT
5V
OCP V IN
A
P D8
P R8 6
6 . 4 9 K _ 1 % _ 04
R B 0 5 4 0S 2 1.1VS_VTT=0.75 X (1+PR65 / PR67)
C
P C1 6 3
+
5
6
7
8
5
6
7
8
P Q4 0 P Q3 9 1 5 u _ 2 5V _6 . 3 * 4 . 5 _E LN A
4
MD S 2 6 59
4
*I R F 7 4 1 3Z P B F
VTT_ SEN SE 6
1.1VS_VTT
2
3
1
2
3
1
PC 6 2
ON P U4 25A(15A)
1 .1 V S _ V T T _ E N _ R S C4 1 2 A 0 . 1 u _ 50 V _ Y 5 V _ 0 6
13
15
16
14
PL 7 V T T 1 .1 V S P J1 7 1. 1V S _ V T T
PR 9 0 1 0 K_ 0 4 0 . 5 6U H _1 0 * 10 * 4 . 1
G 1
I LI M
3 .3 V
G0
DH
12 1 1 2
EN LX
11 2 * OP E N -1 2 m m
4 , 16 , 3 3 1 . 1 V S _ V TT _ P W R G D PG D BST
C
5
6
7
8
5
6
7
8
10 3 PQ 4 3 P Q4 4
V O UT VC C
M D S 26 5 5 M D S 2 65 5 P D1 5
FB 9 4 4 4 + P C 15 4 PC 6 9 + P C 16 2
FB DL S K3 4 SA
R TN
GN D
2
3
1
2
3
1
17 2 2 0u _ 4 V _ V _ B 0 . 1 u _ 5 0V _Y 5 V _ 0 6 2 20 u _ 4 V _ V _ B
D 0
D1
PA D
A
Sheet 34 of 40
5
PC 6 1
1 u _ 25 V _ 0 8
Power 1.1VS_VTT
PR 9 2 P R 88 P C6 6
0_04 1 0K _ 1% _ 0 4 *2 0 p _5 0 V _ N P O_ 0 4
P R9 3 *9 0 . 9 K _ 1 % _0 4
5V
PC 6 7
P R 89
0 . 1 u _1 0 V _ X 7 R _ 0 4
2 4K _ 1% _ 0 4
(1.1VS_VTT=1.067V)
P J1 0
2 1
PJ 9
1 00 K _ 0 4
PR 9 4 1 0 K_ 0 4 1 2 1. 1V S _ V T T _E N _ R
5V
4 0 mi l
PR 8 7
3
*1 0 0 K _ 0 4
D
PQ 1 1 B P R9 1
G 5
* 2 N 7 0 0 2K D W
6 S 1 u _ 1 0 V _ X7 R _ 0 4
4
1
D PQ 1 1 A
* 2N 7 0 02 K D W P J8
G 2
1 6 1 .1 V S _ V T T _ E N 4 0 m il
S
2
P C6 8
* 0 . 1 u _1 0 V _ X 5 R _ 0 4
2, 4 , 6 , 7 , 1 4 , 1 5 , 1 6, 19 , 2 0 , 2 1 , 3 5 , 3 6 1. 1V S _ V T T
3 , 4 , 12 , 1 4 , 1 5 , 1 6 , 1 8, 19 , 2 0 , 2 1 , 2 3 , 24 , 2 5 , 2 9 , 3 0 , 3 1, 33 , 3 5 3 . 3 V
2 1 , 2 4 , 2 7 , 3 0, 31 , 3 3 5 V
1 2 , 30 , 3 1 , 3 2 , 3 3 , 3 5, 36 , 3 7 V I N
Power 1.1VS_VTT B - 35
Schematic Diagrams
Power VGFX_CORE
1. 1 V S _V T T
P J2 40 m li
PR 58 1 0K _ 04 2 1
3. 3 V
1 K _0 4
1K _ 0 4
*1 K _0 4
* 1K _ 04
1 K _ 04
*1 K _0 4
1K _ 04
7 D F G T_ V I D _ 0
? ? JUMP? ? 7 D F G T_ V I D _ 1
7 D F G T_ V I D _ 2
7 D F G T_ V I D _ 3
7 D F G T_ V I D _ 4
7 D F G T_ V I D _ 5
7 D F G T_ V I D _ 6
P R 57
P R5 5
P R5 4
P R5 3
P R 52
P R5 1
PR 56
DF G T_ V I D _ 0
DF G T_ V I D _ 1
PJ4 FOR CV? ? ? DF G T_ V I D _ 2
DF G T_ V I D _ 3
PJ 3 40 mi l DF G T_ V I D _ 4
P R5 9 1 K _ 04 2 1 D F G T_ V R _ E N DF G T_ V I D _ 5
3. 3 V S DF G T_ V I D _ 6
* 1K _ 0 4
* 1K _ 04
*1K _ 0 4
*1 K _0 4
1 K _0 4
1 K _0 4
3 .3VS
1K _ 04
7 D F GT _ V R _ EN 5 VS
PR5 0 P R 42
V IN
47 0 _0 4 1 0K _ 1% _ 04
Sheet 35 of 40 P R3 7
P R 49
P R4 7
P R4 6
P R4 5
P R 44
P R4 3
PR 48
1. 1VS_VT T
4. 7 u _2 5 V_ X 5 R _ 08
0. 1 u_ 5 0V _ Y 5V _ 0 6
* 0. 0 1u _ 50 V _X 7 R _ 04
4 . 7u _2 5 V _X 5 R _ 08
*4 . 7u _2 5 V _X 5 R _ 08
1 0_ 06
Power VGFX_Core PR 40
*1 0K _ 1 %_ 04 1 6 V GF X _ VO R E _ P G P C2 3
1 u_ 6 . 3V _ X5 R _ 04
VGFX_CO RE
7 GF X _I M ON 15A(7A)
5
6
7
8
3.3 VS P Q1 9
P R 21 4 MD S2 6 59
32
30
28
26
P C8 5
PC 4
P C5
P C8 8
(0. 7V~1 .77V)
31
29
27
25
P C 96
0_ 04
1
2
3
G N D _ 32 1 1 V GF X_ C O R E
EN
V ID0
V ID1
V ID2
V ID3
V ID4
V ID5
V ID 6
2
P R3 8 24 P R 35 PC1 7 GP U
P C2 5 PR 41 1 V CC 0 _ 06 0. 2 2 u_ 5 0V _ 06 P J 15
P W RG D
* 10 K _1 % _0 4 BST 23 OP E N _8 A
0. 1 u _5 0V _ Y 5 V _0 6 4 .7 K _ 1% _0 4 2
I M ON
1
22 3 2 11 _D R V H PL 3
32 11 _ C LK E N # 3 D RV H 1. 0 U H _ 10 *1 0 *4 . 5
C LK E N # 21 3 2 11 _S W 1 2
SW
4 P U1
F B RT N
* 0. 1 u_ 1 0V _ X 5R _0 4
*0 . 01 u_ 5 0V _ X 7R _0 4
20
P V CC 5 VS
2 20 u _4 V _V _ B
*2 20 u _4 V _V _ B
P C 20 22 0 p_ 5 0V _ N P O_ 04 5 P R 1 54
P C 21 FB AD P 32 1 1 19 3 2 11 _D R V L
DR V L
PC 18 6 PC 13 *2 . 2_ 0 6
C OMP 18
10 0 0p _ 50 V _X 7 R _ 04
C
P C1 9 P G ND
5
6
7
8
5
6
7
8
47 p_ 5 0V _ N P O_ 04 7 2. 2 u_ 1 6V _ X5 R _ 0 6
P R3 3 2 0K _ 1% _0 4 G PU 17 P Q2 5 P Q2 4 P D1 0
A G ND
8 4 4 MD S 26 55
C S C OM P
P R 34 IL IM 33 MD S 2 6 55 S K 34 S A + +
CS RE F
L LI N E
A G ND
1
2
3
1
2
3
R A MP
CS F B
1K _ 1% _ 04 47 0 p_ 50 V _ X7 R _ 04 P C 1 28
I R EF
RP M
P C1 2 9
R T
P C 1 30
*2 20 0 p_ 5 0V _ X 7R _0 4
P C1 3 7
PR 32
P C 1 38
0_ 04 P R2 2
11
13
15
9
10
12
14
16
GN D _3 2 11
GN D _ 32 11 5VS
7. 5 K _1 % _0 4
GPU App. Place RTH1 close to
3 2 11 _C S C OM P
P R3 1 RT 2
3 21 1_ C S C O MP
3 21 1_ C S C O MP
P R8 P R7 P R3 10 0 K_ N T C _ 06 _ B inductor on the same layer
0 CPU *0 _ 04 2 1
8 0. 6 K _ 1% _0 4
2 00 K _ 1% _0 4
3 32 K _1 % _0 6
1 GPU
P R 1 58
1 10 K _1 % _0 6
G N D _ 32 1 1
GN D _3 21 1 P R2 P C8 P C 13 4 P R 1 57
GP U V C C S E N S E 7 GN D _ 32 11
1 50 0 p_ 50 V _ 06 2 2 0p _ 50 V _N P O_0 4 1 80 K _1 % _0 4 P R 1 56
GN D _ 32 11 16 0 K _1 %_ 0 4
4 22 K _ 1% _0 6
P R 39 1 0 0_ 1 %_ 04 G PU
distr ibute evenly between Nside and Sside,
P R 36 1 0 0_ 1 %_ 04 prefer ably on secondar y side.
VIN P R6 1 K _1 % _0 4
GP U V SS S E N SE 7
PC7 P C2 4
10 0 0p _5 0 V _X 7R _0 4 1 00 0 p_ 50 V _ X7 R _ 04
GN D _ 3 21G1 N D _ 32 1 1
2 , 4, 6 , 7 ,1 4 , 15 , 1 6, 1 9, 2 0 , 21 , 34 , 3 6 1 . 1V S _ V TT
3, 4 , 12 , 1 4, 1 5 ,1 6 , 18 , 19 , 2 0, 2 1 ,2 3 , 24 , 2 5, 2 9, 3 0 , 31 , 33 , 3 4 3 . 3V
4 , 9, 1 0 ,1 1 , 21 , 2 3, 2 7, 2 9 , 31 , 33 , 3 6 1 . 5V
7 V GF X _C O R E
1 2 , 30 , 3 1, 3 2, 3 3 , 34 , 36 , 3 7 V I N
2, 1 3 ,1 7 , 20 , 2 1, 2 6, 2 7 , 30 , 31 , 3 6 5 V S
2 , 10 , 11 , 1 2, 1 3, 1 4 , 15 , 16 , 1 7, 1 8 ,1 9 , 20 , 21 , 2 3, 2 4 ,2 5 , 26 , 2 7, 2 8, 2 9 , 30 , 31 , 3 6 3 . 3V S
B - 36 Power VGFX_CORE
Schematic Diagrams
V-Core
V IN
FOR EMI
P C 80
* 1n _ 50 V _ 04
* 15 u_ 2 5V _ 6 . 3* 4. 5 _ E LN A
*1 5 u_ 2 5V _ 6 . 3* 4. 5 _E L N A
1 5u _2 5 V _6 . 3 *4 . 5_ E L N A
S G ND2
*3 3 0u _C A R 3 15 L
0 . 1u _ 50 V _ Y 5V _ 0 6
0 . 1 u_ 5 0V _ Y 5V _ 0 6
0 . 1u _ 50 V _ Y 5V _ 0 6
0 . 1 u_ 5 0V _ Y 5V _ 0 6
0. 1 u _5 0 V _Y 5 V _ 06
0 . 1u _ 50 V _Y 5 V _ 06
0. 1 u_ 5 0V _ Y 5 V _0 6
0. 1 u _5 0 V _Y 5 V _0 6
* 4. 7 u _2 5 V _X 5 R _ 0 8
0 . 1 u_ 5 0V _ Y 5V _ 0 6
0. 1 u _5 0 V _Y 5 V _0 6
0 . 1u _ 50 V _ Y 5V _ 06
P R 1 11
*4 7K _ 0 4 P C8 2
1u _ 25 V _ 08
CS _ P H1 P R 1 13 2 0 0K _ 1% _ 04
CS _ P H2 P R 1 14 2 0 0K _ 1% _ 04
VIN +
P R 1 10 16 2 K_ 1 %_ 0 6
PR1 0 4 1 K _0 4 + +
+
PC 3
RT1 close to PL6 P Q3 0 PQ 35
P C3 1
P C2 2
P C7 6
P C8 4
P C 10 2
P C7 7
P C 26
P C 1 43
1
P C7 8
P C9 1
P C8 3 PC7 9 1 00 0 p_ 5 0V _ X 7R _0 4 I R F H 7 9 23 *I R F H 7 9 23
P C 10 6
PC1 3 2
RT 3 P R 1 06 15 0 0p _ 50 V _ 06
P C 1 07
P C 32
PC8 9
1 00 K _N TC _0 6 _B 73 . 2 K _1 % _0 4
P C 81 S GN D 2 G G
2
4 7 . 5K _ 1 %_ 0 4
4 7 0p _ 50 V _ X7 R _ 04
68 0 K _1 % _0 4
1 62 K _ 1% _ 06
80 . 6 K _1 % _0 4
VCORE
S
C S C OM P
C S C OM P
S GN D 2 HDR 1 V CO RE
CS S UM
CS RE F
3. 3 V S 3. 3 V S P R 10 7
1 . 6 9K _ 1 %_ 04 PL 5
0. 3 6U H _ 12 . 9 *1 4* 3. 8
24A
1 5 P R1 0 5
1 4 P R 10 9
16 P R 1 08
13 P R 1 12
5 6 0u _ 2. 5 V _ 6. 6 *6 . 6 *5. 9
D
C S _P H 1
3 3 0u _ 2. 5 V _V _ A
*3 30 u _2 . 5 V _V _ A
*3 3 0u _ 2. 5 V _ V _A
* 33 0 u_ 2. 5 V _ V _A
P U5 P C 98 P R 16 0
33 0 u_ 2 . 5V _ V _A
D
C
P R 12 3 P R1 2 6 5 VS P Q2 9 5 . 1 _0 6
24
22
21
19
18
ADP3212
23
20
17
0 . 2 2u _5 0 V _0 6
G I R FH 79 3 2 P Q3 4 P D1 2 P R 16 2
3 K _ 1% _ 04 3 K _1 % _0 4 G I R F H 7 9 32
R PM
L L INE
RA M P
C SR E F
SW FB3
OD 3#
IL IM
C S C O MP
S
RT
IREF
P W M3
Sheet 36 of 40
CS S UM
P R 1 27 S K 34 S A 1 0 _0 6
1 00 _ 1% _0 4
S
V R _ ON 1 36 2_ 0 6 BST 1 P C 13 6
EN BST 1
A
4 , 1 6 D E LA Y _ P W R G D 2 35
3 P W RG D DR V H1 34 P R 1 25 2 2 0p _ 50 V _ N P O_ 0 4
6 I MON I MO N SW 1 +
V-Core
4 33 10 0 _0 6 C S _P H 1 VIN + + + + +
2 CL K E N# CL K E N# SW FB1 5 VS
5 32
6 F B RT N P VCC 31 CS RE F
FB DRVL 1
P C 13 9
P C 14 2
PC1 4 1
P C 14 5
1 5 u_ 2 5V _ 6 . 3* 4. 5 _E L N A
P C9 4 7 30 P R 1 20
P C 1 40
P C 1 44
C O MP P GN D
* 4. 7 u _2 5 V _X 5 R _ 0 8
T R D E T#
*4 . 7u _2 5 V _X 5 R _ 0 8
10 0 0p _ 50 V _ X7 R _ 04 P C 97 P C9 0 PC9 2 8 29 10 0 _0 6 P C 93 P Q27 P Q3 2
T RDET # DRVL 2
0 . 1 u_ 5 0V _ Y 5V _ 0 6
15 0 p_ 5 0V _ 0 6 12 p _5 0 V _N P O_ 04 5 VS 9 28 CS _ P H2 I R F H 7 92 3 *I R F H 79 23
D
VA RF R SW FB2
4 . 7 u_ 2 5V _ X 5R _0 8
27
P R6 4
S GN D 2 0. 1 u _5 0 V _Y 5V _ 06 PC9 5 SW 2 26
DR V H2
15 0 p_ 5 0V _ 0 6 10 25 G G P R 16 1
D P RS L P
TT S N S 1 1 VRT T BST 2
S
12 T TS N S + 1 0 _0 6
VID 4
VID 1
VC C
A GN D
PS I#
VID6
VID5
VID3
VID2
VID0
PH1
PH0
C S _P H 2
RS N
RS P
P R 12 4 P R 1 22 P R1 2 1 49
A GN D
PC1 1 1
5 . 49 K _ 1% _ 04 1. 6 K _ 1% _ 04 3 9. 2 K _ 1% _0 4
P C 1 00
P C 1 33
P C 1 12
HD R2
24A
37
39
40
42
43
46
47
38
41
44
45
S GN D 2
5 VS 48 PL 4
0. 3 6 U H _ 1 2. 9 *1 4 *3 . 8
4 H _P R OC H OT #
P C8 7 P R 15 9
D
D
P R 20 P R 1 17 5 . 1 _0 6
C
P Q1 8 S GN D 2 2_ 0 6 0 . 22 u _5 0 V _0 6 P Q2 8
MT N 7 00 2Z H S 3 G 10 _0 6 B ST 2 G I R F H 7 9 32 P Q3 3 P D1 1
G I R F H 7 9 32
S
S
S K 34 S A P C 13 5
S
1 . 1V S _ V TT
A
P C 12 1 . 5V 1 . 5V S 2 2 0p _ 50 V _ N P O_ 0 4
1u _2 5 V _0 8
*6 4 9_ 1 %_ 04
64 9 _1 %_ 0 4
P R 65
* 1K _ 0 4
* 1K _ 0 4
1K _ 0 4
1 K _0 4
1 K _0 4
*1 K _0 4
1 K _0 4
R SP 0 _ 04
S GN D 2 V CC_ S E NS E 6
P C 30
6 P M_ D P R S L P V R P R1 9 0 _0 4 P R 62
* 10 0 0p _ 50 V _ X7 R _ 04 0 _ 04
P R1 8 0 _0 4 R SN
6 PS I# V S S _S E N S E 6
PR2 3
PR2 4
PR2 5
P R 26
PR2 7
PR2 8
P R 29
2 PR1 4 5
P R 1 46
6 H_ V ID0
6 H_ V ID1 PR6 1
P R 30 PJ 1
* R _ 04 6 H_ V ID2 10 0_ 1 %_ 0 4
6 H_ V ID3 4 0m il
6 H_ V ID4
1
6 H_ V ID5
6 H_ V ID6
*1 K _0 4
*1 K _0 4
* 1K _ 04
1 K _ 04
1K _ 0 4
*1 K _ 04
1 K _ 04
5V S P R1 1 5
0 _0 4
5 VS
P R 1 31 10 K _0 4 V R _ ON
3. 3 V S
P R 1 19
P R1 1
P R1 2
P R1 3
P R 14
P R1 5
P R1 6
P R 17
P R 11 6 P R 14 7 P Q2 2B S G ND2
5. 1 K _ 1% _ 04 3
7. 3 2K _ 1 %_ 0 4 10 0K _ 0 4 MT D N 70 0 2Z H S 6 R D
5 PR1 3 0
T TS N S T R D E T# G
P Q 22 A S *1 0 K _0 4
6 4
1
R T1 PC 86
P R 1 18 M TD N 70 0 2Z H S 6R D P J1 4 4, 9 , 10 , 1 1, 2 1 , 23 , 2 7, 2 9 , 31 , 33 1 . 5V
10 0K _ N T C _ 0 6_ B 0. 0 1u _ 50 V _ X7 R _ 0 4
*R _ 0 4 G 2 40 mi l 2 0 , 23 , 31 1 . 5V S
28 V C OR E _ ON 2 , 4 , 6, 7 , 14 , 1 5, 1 6 , 19 , 2 0, 2 1 , 34 , 35 1 . 1V S _ V T T
2
S 6 V CO RE
1
12 , 3 0, 3 1 , 32 , 3 3, 3 4 , 35 , 37 V IN
2 , 13 , 17 , 2 0, 2 1 , 26 , 2 7, 3 0 , 31 , 35 5 VS
2 , 10 , 1 1, 1 2 , 13 , 1 4, 1 5 , 16 , 17 , 1 8, 1 9 , 20 , 2 1, 2 3 , 24 , 25 , 2 6, 2 7 , 28 , 2 9, 3 0 , 31 , 35 3 . 3V S
P C 11 4
* 0. 1 u _1 0 V _X 5R _0 4
V-Core B - 37
Schematic Diagrams
DC-In, Charger
CHARGER VA
# Char ge Cur r en t 3.0A
# Char ge Volt age 12.6V
PQ 2 3
V IN
4
P 2 0 0 3E V G # To tal Pow er 60W
? ? :6-20-B3410-003 1 5
2 6
JA C K 1 3 7
50 9 3 2- 00 3 0 1-0 0 1 PL 1 VA P Q1 7 8
H C B 4 5 3 2K F -80 0 T 60 P 20 0 3 E V G P Q2 6 A
8 P R9 9 A P 69 0 1 GS M PL 2 P R1 3 9 V_ BAT
1 7 3 0. 0 2 _ 1 %_ 3 2 2 4. 7 U H _ 6 . 8* 7 . 3* 3 . 5 0 . 0 2 _ 1% _ 3 2
2
6 2 1 7
G ND 1 P C7 5 PC 1 P C2 P R 10 3 5 1
G ND 2
0_04
0 _ 04
5
6
P R1 1 3 0K _ 1 % _0 4
0 . 1u _ 5 0V _ Y 5 V _ 0 6
0 . 1 u _5 0 V _ Y 5 V _ 06
0 . 1u _ 5 0V _Y 5 V _ 0 6
4 . 7u _ 2 5V _ X 5 R _0 8
4 . 7u _ 2 5V _X 5 R _0 8
0 . 1 u _5 0 V _ Y 5 V _ 06
0 . 1 u _ 50 V _ Y 5 V _ 06
4 . 7u _ 2 5V _ X 5 R _0 8
4 . 7u _ 2 5V _X 5 R _0 8
4 . 7u _ 2 5V _X 5 R _0 8
4 . 7u _ 2 5V _X 5 R _0 8
4 . 7 u_ 2 5 V _X 5 R _0 8
4. 7 u _ 25 V _ X 5 R _ 0 8
4
8
2 0 0K _ 1 % _ 04
0 . 1 u _5 0 V _ Y 5V _0 6
P R1 0 1
1 0 K_ 0 4 P R1 4 8 3
P R 10 2 0_04 P Q 26 B
4
A P 6 9 0 1G S M
P R 15 1
P R 1 50
PC 1 6
P C1 5
1 0 K _1 % _ 04
P C9
P C1 0
P C1 2 4
P C1 2 7
P C1 2 5
P C1 2 6
P C1 2 3
P C1 2 2
P C 12 1
1 0 0K _ 0 4
PC 1 4 0 . 1 u _ 50 V _ Y 5 V _ 0 6
P C 11 3 P R1 3 6
*0 _ 04
P D1
V_ BAT 1 u_ 2 5 V _ 08
C A 0_ 0 4 PIN 25t h
P R 10 0
FOR 2S CONNECT T O GND
Sheet 37 of 40 P C 1 09 P C1 1 0 P C 1 20 R B 0 5 4 0S 2 FOR 3S CONNECT N.C.
FOR 4S CONNECT T O VREF PIN
0 . 1 u _5 0 V _ Y 5 V _ 06 0 . 1u _ 5 0V _ Y 5V _0 6 0 . 1 u_ 5 0 V _ Y 5 V _ 06
P R5
DC-In, Charger VA
PR 4 *0 _ 04
32
31
30
29
28
27
25
26
V IN P U6 VA
C B
LX
OU T -1
O U T -2
P GN D
VB
C E LL S
CT L 2
1 24 P C1 0 3 0 . 1 u _5 0 V _ Y 5 V _ 06
V CC V IN C T L1 V D D3
2 23
P C 1 19 P C1 1 8 P C 1 17 P C1 1 6 3 -I N C 1 C TL 1 22
+I N C 1 G ND
4 21 R1 6 1 0 K _ 04
0 . 1u _ 5 0 V _Y 5 V _0 6 0 . 1u _ 5 0V _ Y 5V _0 6 0 . 1 u _5 0 V _ Y 5 V _ 0 6 0 . 1 u _ 50 V _ Y 5 V _ 0 6 5 A CIN TRERMAL PAD VR EF 20
A CO K RT
6 19 C
7 -I N E 3 C S 18 V OL T _ S E L P R1 4 0 S M C_ B A T AC
0. 1u _ 5 0V _ Y 5 V _ 0 6
O UT C 1
OU T C 2
C O MP 2
C OM P 3
A DJ 1 A DJ 3
+ INC 2
8 17 S GN D 6 A
-I N C 2
AD J 2
0 . 1 u_ 5 0 V _ Y 5V _0 6
-I N E 1
C O MP 1 BATT 33 4 9. 9 K _ 1 % _0 4 D9
3 9 . 2 K _1 % _ 04
S G ND
B A V 9 9 R E C TI F I E R
P R1 5 3 MB 3 9 A 1 3 2 C
10
11
12
13
14
16
9
15
S G ND 6 S M D_ B A T AC
10 K _ 1 % _0 4
V DD 3 10 K _ 1 % _0 4 P C9 9 A
P R 15 5
TOTAL CHARGE
1 0 0 p_ 5 0 V _N P O_ 0 4 P R1 3 4 P R1 4 2 D8
POWER 1 K _ 1 % _0 4 CURRENT B A V 9 9 R E C TI F I E R
ADJ P C1 3 1 1 K _1 % _ 0 4 ADJ C
P R1 4 9 B A T _ DE T AC
PC 6
0. 01 u _ 50 V _ X 7R _ 04 P C1 0 4 * 2 2p _ 5 0V _ N P O_ 0 4 A
P C1 1
P R 1 32
1 0K _0 4 P C1 0 1 D7
1 0 0 0p _ 5 0V _ X 7 R _ 0 4 P R 1 3 7 P R1 4 4 B A V 9 9 R E C TI F I E R
S G ND 6
20 K _ 1 % _0 4
A C _I N # 28
2 2 K _ 1% _ 0 4 S G ND 6 S G ND 6 S G ND 6 2 2K _ 1 % _ 04 C
P R 15 2
C
P C1 0 8 B A T _ V O LT AC
C A B P Q3 1 1 0 0 0p _ 5 0V _ X 7 R _ 0 4 P R 1 4 3 A
VA
S G ND 6 D6
PD 9 P C1 1 5 D T C 11 4 E U A 1 0K _ 1 % _ 04 S GN D 6 B A V 9 9 R E C TI F I E R
U DZ 1 6 B
E
*0 . 1 u _5 0 V _ Y 5 V _ 06
V_ BAT
0. 5V/ 1A T OT A L _ C U R
PIN17t h CONNECT
0. 5V/ 1A CU R_ S E N S E T OBAT CONN.
B T D - 05 T I 1 G
P R 13 3
10
5
1 0 2K _ 1 % _ 04 5 1 S MC _ B A T_ R
P R2 0 0 28 S M C_ B A T 6 2 S MD _ B A T_ R 4
V OL T _ S E L 28 S M D_ B A T B A T _D E T _ R 3
7 3
SYS5 V SY S5 V 28 B A T _ DE T 8 4 B A T _V OL T _R 2
28 B A T_ V O LT 1
PQ 2 1 P R1 2 8
D
A O 3 40 9 3 00 K _ 1 % _0 4 2M _ 1% _ 0 4 J BAT TA1
9
V _B A T S D B A T _ V OL T _ R P R 19 9
P R 1 41 P R1 3 5 G P L C1
V C H G_ S E L 2 8
7 6 . 8K _1 % _ 04 E F 0 8 05 V 0 5 4 00
S
P R1 0 1 0 0 K _0 4 1 00 K _ 0 4 PQ 4 9
G
20 0 K _ 1 %_ 0 4 P Q2 0 A M TN 7 00 2 Z H S 3
P R 1 38 P C 10 5 CT L 1
MT D N 7 00 2 Z H S 6R 6 3
6 0 . 4 K _ 1% _ 0 4 0 . 1 u_ 5 0 V _Y 5 V _ 06 D D
P R9 P Q 20 B
G 2 G 5
28 C H G_ E N MT D N 7 0 02 Z H S 6 R
0 _0 4 S S
1 4
1
PJ 1 3
D
P Q1 OP E N -1 m m P R 12 9 *1 5m i l _s h o rt _ 06 S YS5 V 3 1 , 32
V DD3 1 4, 2 3 , 2 5, 2 8 , 2 9 , 31 , 3 2
S Y S 5V G 2 VA 31
MT N 7 0 0 2Z H S 3 S G ND 6
V IN 1 2, 3 0 , 3 1, 3 2 , 3 3 , 34 , 3 5 , 36
S
B - 38 DC-In, Charger
Schematic Diagrams
Click Board
CLICK BOARD
CC2 CC1
0.1u_10V_X7R_04 0.1u_10V_X7R_04
C5VS C5VS
CGND CGND
CJ_TP1 CJ_TP2
1 CTP_DATA 1 CTP_CLK
2 CTP_CLK 2 CTP_DATA
3 3 CTPBUTTON_L
4 4 CTPBUTTON_R
85201-04051 5
6
Sheet 38 of 40
CGND 85201-06051
CGND
Click Board
CSW1~2
2 4
1 3
LIFT RIGHT
KEY KEY
CSW1 CSW2
TJG-533-S-T/R TJG-533-S-T/R
1 2 1 2
3 4 CTPBUTTON_L 3 4 CTPBUTTON_R
5
6
5
6
CGND CGND
CH3 CH1 CH4 CH2

2 9 2 9 2 9 2 9
3 8 3 8 3 8 3 8
4 1 7 4 1 7 4 1 7 4 1 7
5 6 5 6 5 6 5 6
MTH237D91 MTH237D91 MTH237D91 MTH237D91
CGND CGND CGND CGND CGND CGND CGND CGND
Click Board B - 39
Schematic Diagrams
Audio / USB / RJ11 Board
RJ-11 USB PORT

A _ US B V C C A _U S B V C C
AU 1
A _ 5V 5 6
60 mils
F L G# V O U T 1
60 mil s 2 7
V IN1 V O UT 2 A C9 A C1 0
A C1 3 3 8
V IN2 V O UT 3 0. 1 u _ 16 V _ Y 5 V _ 0 4
1 0 u _1 0 V _ Y 5 V _ 08 4 1 0. 1u _ 16 V _ Y 5 V _ 0 4
E N# G ND
R T 9 7 15 B G S
A G ND A GN D A GN D A G N D A GN D
6-0 2-09715- 920
A_ U S B V CC A L 10 A _U S B V C C 2
H C B 1 6 08 K F -1 2 1 T2 5
60 mil s
A C1 6 AC 1 1
+
10 0 U _ 6 . 3V _B 2 . 1 U _1 0 V _ X7 R _ 0 4
Sheet 39 of 40 MODEM RJ-11

A G ND
A U S B _P N 4 _R
1
A J _ US B 1
V+
J_MODEM1 A J_ MO D E M 1 A J _ RJ 1 2
Audio / USB / RJ11 2 1

2
1
Z 4 0 08
Z 4 0 09
AL 1
AL 2
MH C 1 60 8 S 1 21 P B P Z 4 0 10 1
MH C 1 60 8 S 1 21 P B P Z 4 0 11 2 T IP
RIN G
A R7 * 10 m i l_ s h ort A U S B _P P 4_ R 3
DA T A _ L
DA T A _ H
G ND 4
8 5 2 04 -0 2 00 1 4
GN D 1
GN D 2
GN D 3
Board C 10 1 8 1-1 0 2 05 -L
PIN G ND1 ~ 2 = AG ND
AU SB_ PP4
A U S B _ P N4 4
1 AL 9
3
2 A U S B _P P 4 _ R
A U S B _P N 4 _R
GN D
C 1 07 7 0-1 0 4 A 3
G ND 2
G ND 4
GN D 1
GN D 3
* W C M 2 01 2 F 2 S -16 1 T 03
A R6 * 10 m i l_ s h ort
A G ND A G ND
AUDIO JACK A M IC_ SE NS E 5 A J _ MI C 1

4
A M I C 1 -R AL 4 F C M1 0 05 K F -1 2 1T 0 3 Z 4 10 5 3 R
A M I C 1 -L AL 3 F C M1 0 05 K F -1 2 1T 0 3 Z 4 10 6 2
Z 4 10 7 6 L
1
A C5 A C6 2 S J- S 35 1 -S 3 0
A _5 V
A J _ A U D I O1 1 0 0 P _5 0 V _ 0 4 1 00 P _ 5 0V _ 0 4
MIC IN 3 4 5
A MI C 1 -R 1
A MI C 1 -L 2
3
BLACK
A H E A D P H ON E -R 4
A _ A U DG
A H E A D P H ON E -L 5
A MI C _ S E N S E 6 A H P _S E N S E
A S P K _ HP # 7 2 1 6
A HP _ S ENS E 8 ASPK_ H P# 5 A J _ HP 1
9
A US B _ PN4 4
A US B _ PP 4 10 A H E A D P H ON E -R Z 4 1 12 A L 6 F C M 10 0 5K F -12 1 T 03 Z4108 3 R
11
A R3 6 8_ 1 % _0 4
A S P K OU TR + 12 A H E A D P H ON E -L Z 4 1 13 A L 5 F C M 10 0 5K F -12 1 T 03 Z4109 2
A S P K OU TR - 13
A R2 6 8_ 1 % _0 4 6 L
14 1
8 7 2 13 -1 4 L AR 4 AR 1 A C7 A C8 2 S J- S 35 1 -S 3 0
* 1K _0 4 * 1K _ 0 4 1 0 0 P _5 0 V _ 0 4 1 00 P _ 5 0V _ 0 4
A _ A U DG A G ND HEADP HONE
BLACK
A _ A U DG
A S P K OU T R + AL 8 1 2 F C M 10 0 5 K F -12 1 T 03
AL 7 A C1 2 A J _ S P K R1
F C M1 0 0 5K F -1 2 1 T0 3 10 0 0 p_ 5 0V _X 7 R _ 0 4 A S P KO UT R+ _ R J_SPK1
A S P K O UT R- A S P K O U T R -_ R 1 2 1
1 2
2
A C1 5 A C1 4 8 5 2 04 -0 2 00 1
P C B F oo t p ri nt = 8 5 2 04 -0 2 R
AH 2 AH3 AH1 1 8 0p _ 50 V _ N P O_ 04 1 8 0p _ 5 0V _ N P O_ 0 4
C 52 D 52 2 9 2 9 A C3 0. 1 u _1 6 V _ Y 5 V _ 0 4
3 8 3 8 A _ A U DG AR 5 *1 0 m li _ sh o rt
4 1 7 4 1 7 A C1 0. 1 u _1 6 V _ Y 5 V _ 0 4
5 6 5 6
A C4 0. 1 u _1 6 V _ Y 5 V _ 0 4
MT H 27 6 D 1 1 1 MT H 27 6 D 1 1 1
A C2 0. 1 u _1 6 V _ Y 5 V _ 0 4
A G ND A G ND A G ND A GN D
A G ND A _ A UD G
B - 40 Audio / USB / RJ11 Board

Schematic Diagrams
Power Switch & LID Board
POWER SW & LED & HOT KEY
S _3 . 3 V
LID SWITCH IC SD 2
C
S _ 3 . 3V S *B A V 99 R E C T I F I E R
S _ 3. 3V
POWER
SWITCH SR 1 1 0 0K _ 0 4 AC
S _ 3. 3 V S S _ 3 .3 V
S R2
LED SU 1
S _ 3 . 3V S S _3 . 3 V 1 2 S LI D _ S W #
VC C OU T
SJ _ SW 1 22 0 _ 04
20 mi l
G ND
A
1 SJ _ SW 2 SC2 S C1
2 0m il 2 0m il
2
3
S M _B T N #
1
Z4301 M H -2 4 8
Sheet 40 of 40
3
SW EB_ W W W # 0 . 1 u_ 1 0 V _ X7 R _ 0 4 1 0 0 p_ 5 0 V _N P O_ 0 4
4 2
S W E B _ E M A IL # S M _ B TN # SC 6 S M GN D
5 S L ID_ S W # 3 S W E B _W W W #
6 4
Power Switch & LID
A
S W E B _E MA I L # *0 . 1 u _1 0 V _ X5 R _0 4 S M GN D S MGN D
7 SAP_ O N S M GN D 5 S L I D _S W #
8 6
SD 1 S M GN D
9 S M GN D 7 S MG N D
Board
S A P _O N L TS T -C 15 0 T B K T S MG N D
10 S _ V IN 8
SU1, SU2
3
C
* 50 5 00 -0 1 04 1 -0 01 L 8 8 2 96 -0 8 00
1 2
1 0 pin & 8 pi n co -la y
S M GN D
S _V I N
HOT KEY
POWER BUTTON WEB_WWW# WEB_EMAIL# AP_KEY#
S R3
SPW R_ SW 1 SW W W _ SW 1 S MA I L _ S W 1 *1 00 K _ 0 4 SAP_ SW 1
TJ G -53 3 -S -T / R T JG -5 33 -S -T / R TJ G -53 3 -S -T / R T JG -5 33 -S -T / R
1 2 S M_ B T N # 1 2 S W E B _W W W # 1 2 S W E B _ E MA I L # 1 2 SAP_ O N
3 4 3 4 3 4 3 4
SC 4 S C3 SC 5 S R5
5
6
5
6
5
6
5
6
PSW1~8 SR 4 * 47 K _ 0 4
0 . 1 u_ 1 0 V _X 7 R _ 0 4 0 . 1u _ 1 0V _ X 7 R _ 04 0_04 0 . 1 u_ 1 0 V _X 7 R _ 0 4
3 1
4 2
S MG N D S M GN D S M GN D S MG N D S MG N D S M GN D S M GN D
S MGN D
S M GN D
S MH 1 S MH 3 S M H4
2 9 2 9 2 9
3 8 3 8 3 8
4 1 7 4 1 7 4 1 7
5 6 5 6 5 6
MT H 2 3 7D 8 7 MT H 2 3 7 D 8 7 M TH 23 7 D 1 1 8
S M GN D S M GN D S MG N D S MG N D
Power Switch & LID Board B - 41

Schematic Diagrams
B - 42

CLEVO E412x - 6-7P-E4124-002 PDF

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CLEVO E412x - 6-7P-E4124-002 PDF

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Preface

E4120 / E4121-C / E4125-C / E4121D-C

About this Manual

The following information is included:

Appendix A, Part Lists

IMPORTANT SAFETY INSTRUCTIONS

TO REDUCE THE RISK OF FIRE, USE ONLY NO. 26 AWG OR LARGER,

This Computers Optical Device is a Laser Class 1 Product

Instructions for Care and Operation

Use only approved brands of Unplug the power cord before

The computer has specific power requirements:

IBEXPEAK - M 5/9 ..................................................................... B-19

Power 3.3V/5V ............................................................................. B-33

56K Fax/Modem Security (Kensington Type) Lock Slot

Dimensions & Weight

Full Range AC/DC Adapter

1 - 4 External Locator - Top View with LCD Panel Open

External Locator - Front & Right side Views Figure 2

External Locator - Front & Right side Views 1 - 5

External Locator - Left Side & Rear View

1 - 6 External Locator - Left Side & Rear View

External Locator - Bottom View

To prevent your com-

External Locator - Bottom View 1 - 7

Figure 7 Mainboard Overview - Top (Key Parts)

1 - 8 Mainboard Overview - Top (Key Parts)

Mainboard Overview - Bottom (Key Parts) Figure 8

1. CPU Socket (no

Mainboard Overview - Bottom (Key Parts) 1 - 9

Figure 9 Mainboard Overview - Top (Connectors)

1 - 10 Mainboard Overview - Top (Connectors)

Mainboard Overview - Bottom (Connectors) Figure 10

Mainboard Overview - Bottom (Connectors) 1 - 11

An example of these types of boxes are shown in the sidebar.

To remove the Battery: To remove the Modem:

To remove the WLAN Module:

Removing the Battery

Removing the Battery 2 - 5

Removing the Hard Disk Drive

a. Locate the HDD bay Hard Disk Upgrade Process

New HDDs are blank. Before you begin make sure:

2 - 6 Removing the Hard Disk Drive

3. Remove the hard disk bay cover 63 .

Removing the Hard Disk Drive 2 - 7

Figure 4 Removing the Optical (CD/DVD) Device

2 - 8 Removing the Optical (CD/DVD) Device

Removing the System Memory (RAM) Figure 5

Be careful not to touch

Removing the System Memory (RAM) 2 - 9

2 - 10 Removing the System Memory (RAM)

Removing and Installing the Processor

Removing and Installing the Processor 2 - 11

The heat sink, and CPU area in

2 - 12 Removing and Installing the Processor

Processor Installation Procedure Figure 9

Removing and Installing the Processor 2 - 13

Figure 10 Removing the Wireless LAN Module

2 - 14 Removing the Wireless LAN Module

Removing the 3.75G Module Figure 11

Removing the 3.75G Module 2 - 15

Figure 12 Removing the Modem

2 - 16 Removing the Modem

Removing the Bluetooth Module Figure 13