EE141-Fall 2009 Complex Gate Delay

Digital Integrated Use RC model to estimate delay:

Circuits
Rp Rp
A B

Rn CL
B
Lecture 7
Gate Delay and Rn
Cint
Logical Effort A

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Announcements Complex Gate Delay (2)

Lab#3 this Fri., next Mon. and Tues. What is the delay in this case?
Homework #3 due today Rp Rp
Homework #4 due next Thursday A B

Rn CL
B

Rn
Cint
A

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Class Material Elmore Delay

Last lecture
Inverter delay optimization
Todays lecture
Gate delay and logical effort Elmore delay: approximation for delay of
arbitrary (complex) RC circuits
Reading (Chapter 6) To find Elmore time constant:
For each capacitor, draw path of current from
cap to input
Multiply C by sum of Rs on current path that
are common with path from Vin to Vout
Add up RC products from all capacitors
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 Elmore Delay (Formal Method) Another Example Gate

Apply current I across C, measure Vout

Calculate Reff = Vout/I

Time constant due to that C is Reff*C

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Simplified Model: Elmore Delay Gate Sizing

Rp Rp Rp
2 A B 2 4 B

Rn Rp Cint
CL 4
2 A
B
Elmore = R1C1 + ( R1 + R2 ) C2 + ( R1 + R2 + R3 ) C3
Rn Rn Rn CL
2 Cint
1
A A B 1

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Another Elmore Delay Example Sizing Example

B
A
C

D
OUT = D + A (B + C)
Elmore = A
D
B C

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 Buffer Chain Review
In Out
C1 C2 CN
1 2 N CL = CN+1
Logical
N
Effort Delay = tinv ( + fi )
i =1

fi = Ci+1/Ci
For given N: Ci+1/Ci = Ci/Ci-1
To find N: Ci+1/Ci ~ 4

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Delay Of NAND Gate

Question #1
Cdnand = 6CD 2 2
All of these are decoders Cgnand = 4CG = (4/3) Cginv
Which one is best? CD/CG= 2

tpNAND = kRW(Cint + CL)

= k(Rsq,n*L/W)(WCdnand + CL)
= k(Rsq,n*L*Cgnand)(Cdnand /Cgnand +CL/(WCgnand))
= k(Rsq,n*L*4*Cg)(3/2* +CL/(4WCg))
= tinv (2 + (4/3)f)
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Delay Of NOR Gate

Question #2 4
Cdnor = 6CD
Is it better to drive a big capacitive load Cgnor = 5CG = (5/3) Cginv
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directly with the NAND gate, or after some CD/CG=
buffering?
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tpNAND = kR(Cint + CL)

CL CL = k(Rsq,n*L/W)(WCdnor + CL)
= k(Rsq,n*L*Cgnor)(Cdnor /Cgnor +CL/(WCgnor))
= k(Rsq,n*L*5*Cg)(6/5* +CL/(5WCg))
Method to answer both of these questions:
Logical effort = tinv (2 + (5/3)f)
Extension of buffer sizing problem
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 Logical Effort Delay in a Logic Gate
tpgate = tinv (p + LEf) Gate delay:

Delay = EF + p (measured in units of tinv)

Measure everything in units of tinv (divide by tinv):
effective fanout intrinsic delay
p intrinsic delay (kg) - gate parameter f(W)
LE logical effort (k) gate parameter f(W) Effective fanout:
f electrical effort (effective fanout) EF = LE f
Normalize everything to an inverter:
logical effort electrical fanout = Cout/Cin
LEinv =1, pinv =

Logical effort is a function of topology, independent of sizing

Effective fanout is a function of load/gate size
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Logical Effort Logical Effort

C
Delay = k tinv g + L Inverter has the smallest logical effort and
Cin intrinsic delay of all static CMOS gates
= tinv ( p + LE f )
Measure everything in units of tinv (divide by tinv): Logical effort LE is defined as:
(Req,gateCin,gate)/(Req,invCin,inv)
p intrinsic delay (kg) - gate parameter f(W) Easiest way to calculate (usually):
LE logical effort (k) gate parameter f(W)
Size gate to deliver same current as an inverter, take
f electrical effort (effective fanout) ratio of gate input capacitance to inverter capacitance
Normalize everything to an inverter:
LEinv =1, pinv = LE increases with gate complexity

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Graphical View Logical Effort

Calculating LE by sizing for same drive strength:

t pNAND VDD VDD VDD

Normalized delay (d)

t pINV

A 2 A 2 B 2 B 4

F
F
A 4
A 2
A 1 F

A 1 B 1
1 2 3 4 5 6 7 B 2
Fan-out (f)

Inverter 2-input NAND 2-input NOR

LE = 1 LE = LE =
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 Logical Effort of Gates Multistage Networks
N

t pNAND Delay = ( pi + LEi fi )

Normalized delay (d)

LE=4/3 t pINV i =1
p=2
d=(4/3)f+2 Effective fanout: EFi = LEifi
LE=1
p=
d=f+
Path electrical fanout: F = Cout/Cin

p = Fan-in
Path logical effort: LE = LE1LE2LEN
(for top input)
Branching effort: B = b1b2bN
1 2 3 4 5 6 7
Fan-out (f) Path effort: PE = LE F

Path delay D = di = pi + EFi

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Gate Sizing Convention Optimum Effort per Stage

Need to set a convention:
What does a gate of size 2 mean? When each stage bears the same effort:
For an inverter it is clear: EF N = PE
Cinv = 2, Rinv =
EF = N PE
For a gate, two possibilities: Effective fanouts: LE1f1 = LE2f2 = = LENfN
Cgate = 2Cinv
Rgate = Rinv/2 Minimum path delay
In my notes, size Cgate/Cinv
D = i =1 ( LEi fi + pi ) = N PE1/ N + i =1 pi
N N

Size 2 gate has twice the input capacitance of a unit

inverter
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Adding Branching Optimal Number of Stages

For a given load,
Branching effort: and given input capacitance of the first gate
Find optimal number of stages and optimal sizing
CL ,on path + CL ,off path
b=
D = N PE1/ N + pi
CL ,on path

Remember: we can always add inverters to the end of the chain

CL,on_path

The best effective fanout EF = PE1/ N is still around 4
CL,off_path (3.6 with =1)

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 Example: Optimize Path Next Lecture
1 b c
a Applying logical effort to a decoder
5
LE = 1 LE = 5/3 LE = 5/3 LE = 1
f=a f = b/a f = c/b f = 5/c

Electrical fanout, F =
LE =
PE =
EF/stage =
a=
b=
c=
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Example: Optimize Path

1 b c
a
5
LE = 1 LE = 5/3 LE = 5/3 LE = 1
f=a f = b/a f = c/b f = 5/c

Electrical fanout, F = 5 5/c = 1.93

LE = 1(5/3)(5/3)1 = (25/9) (5/3)c/b = 1.93
PE = ( LE)F = (125/9) (5/3)b/a = 1.93
EF/stage = (125/9)^(1/4) = 1.93
a = 1.93
b = 2.23
c = 2.59
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Method of Logical Effort

Compute the path effort: PE = (LE)BF
Find the best number of stages N ~ log4PE
Compute the effective fanout/stage EF = PE1/N
Sketch the path with this number of stages
Work either from either end, find sizes:
Cin = Cout*LE/EF

Reference: Sutherland, Sproull, Harris, Logical Effort, Morgan-Kaufmann 1999.

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