Baker Ch.

12 Static Logic Gates Introduction to VLSI

 Chapter 12
– Static Logic Gates
• DC NAND, NOR
• Layout
• AC, Switching
• Complex CMOS Gates

Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor 1
 Baker Ch. 12 Static Logic Gates Introduction to VLSI

 DC NAND, NOR  DESCRIPTION

– TRANSCONDUCTANCE RATIO
• MODEL W/INPUTS TIED TOGETHER
• ASSUME 2-INPUT
• WN, 2LN; 2WP, LP
• NAND =W/2L (nmos)  2W/2L (pmos)
• NOR =W/L (nmos)  4W/L (pmos)

Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor 2
 Baker Ch. 12 Static Logic Gates Introduction to VLSI

 LAYOUT NAND, NOR  DESCRIPTION

– WHAT IS NON-MINIMUM?
• POLY-TO-POLY SPACING

– WHAT IS THE IMPACT?

• EXTRA SERIES DIFF RESISTANCE
• EXTRA DIFF CAP

– HOW MUCH?
• DEPENDS ON SIMS
• WHAT IS THE SPEC TARGET?

Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor 3
 Baker Ch. 12 Static Logic Gates Introduction to VLSI

 AC, SWITCHING  PARALLEL CONNECTIONS

– PMOS
• tPLH ~0.7 RP/N (N COXP + CLOAD)
– NMOS
• tPHL ~0.7 RN/N (N COXN + CLOAD)
 SERIES CONNECTIONS
– tDELAY ~ 0.35 R C N2 (CHPT. 2)
– PMOS
• tPLH ~0.35 RP COXP N2 + 0.7 N RP CLOAD
– NMOS
• tPHL ~0.35 RN COXN N2 + 0.7 N RN CLOAD

Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor 4
 Baker Ch. 12 Static Logic Gates Introduction to VLSI

 MUTLI-INPUT GATES  DESCRIPTION

– PSEUDO-NMOS
– USES PMOS AS A LOAD
– MUTLI-INPUT W/O AREA PENALTY

– TRADEOFF IS SLOW RISE TIME

Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor 5
 Baker Ch. 12 Static Logic Gates Introduction to VLSI

 COMPLEX CMOS GATES  DESCRIPTION

– AND-OR-INVERT (AOI)
• INSTEAD LOGIC GATE IMPL
• NEED INV SIGNALS AS INPUTS
– EXAMPLE, Z=A’ + BC
– Z’ = [ A’ + BC ]’ = A(B’ + C’)
– Z = [ A(B’ + C’) ] ’ = A’ + BC
– OUTPUT CAP, SWITCH NMOS ||
3 PMOS, 2 IN SERIES
3 NMOS, 2 IN SERIES

4 PMOS, 2 IN SERIES
4 NMOS, 2 IN SERIES

Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor 6
 Baker Ch. 12 Static Logic Gates Introduction to VLSI

 CMOS GATES– XOR  DESCRIPTION

– Z = (A+B) (A’ + B’)
– Z’ = [ (A+B) (A’ + B’) ]’ = A’B’ + AB
– Z = [ A’B’ + AB ]’

Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor 7
 Baker Ch. 12 Static Logic Gates Introduction to VLSI

 CMOS GATES– ADDER  DESCRIPTION

– SUM:
• Sn = An XOR Bn XOR Cn
• Sn =
A’n B’n Cn +
A’n Bn C’n +
An B’n C’n +
An Bn Cn

– CARRY:
• Cn+1 = An Bn + Cn (An + Bn)
• C’n+1 = (A’n + B’n) [ C’n + (A’n B’n) ]

– COMBINING SUM AND CARRY:

• Sn = (An + Bn + Cn) Cn+1 + An Bn Cn

Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor 8