The Power to Amaze.

POWER CONVERTER TOPOLOGY

TRENDS

Name: Steve Mappus

Systems Engineer

Date: October 02, 2014

www.psma.com, power@psma.com
 Agenda

 Topology Overview
 Non Isolated Topologies
 Isolated DC-DC Derivatives
 Single Ended Topologies
 Transformer Reset Techniques
 Flyback Converter
 Forward Converter
 Double Ended Topologies
 Push Pull
 Half Bridge
 Full Bridge
 Summary

2
 Isolated Power Topology Derivatives

VO 1 VO D VO
BOOST = BUCK-BOOST =− BUCK =D
Vi 1 − D Vi 1− D Vi
NON-ISOLATED

ISOLATED

SINGLE-ENDED SINGLE-ENDED DOUBLE-ENDED

LOW POWER (< 100 W)

MID-POWER (100 W - 500 W) FLYBACK FORWARD PUSH-PULL

HIGH-POWER (> 500 W) 2-SWITCH 2-SWITCH HALF BRIDGE

Power levels numbers for general

discussion only. Exceptions aplenty. ACTIVE CLAMP ACTIVE CLAMP LLC

FULL BRIDGE

 8 “Mainstream” Converter Topologies ZVT/PHASE SHIFT

 Non-Isolated  Isolated
HARD SWITCHED
1. Boost 4. Flyback
2. Buck-Boost 5. Forward
3. Buck 6. Push-Pull
7. Half Bridge
8. Full Bridge

3
 Other Topologies?

 Numerous Variations Exist  Different Ways to Operate Them

 Sepic  Voltage Mode Control
 Cuk  Current Mode Control
 Current Fed Buck  Digital Control
 Tapped Inductors  Variable Frequency
 Multiple Outputs  CCM, DCM, BCM
 Interleaving  ZVS
 More?  ZCS
 Synchronous Rectification

 Some Practical Converter Topology Advice

 Most power conversion requirements can be met using one or more of the 8
mainstream topologies
 Save more difficult topologies for unique application requirements
 Beware of publications proclaiming the “best” topology

4
 Multi-Stage Topology
Typical Distributed Power System
AC Line 48 V to 12 V IBC (Intermediate Bus Converter)
85 V < VAC < 265 V

VDC = 400 V 400 V to 48 V Bus Converter

Telecom Rectifier
VPOL_1 < 5 V

PFC Boost High Power DC-DC

 Scalable, efficient, complex protection functions, VPOL_N < 5 V

sequencing, redundancy, digital control, etc

 Efficiency example
POL DC-DC
η SYS = η PFC ×η DC ×η DC ×η POL
η SYS = 98% × 95% × 95% × 96% = 84.9%
5
 Single-Stage Topology
PFC Flyback

AC-DC

AC

EMI

PFC
FL7733A

 Difficult to meet: Low cost, high PF, low THD, high efficiency, wide VIN with single-stage

η = 84.9%

6
Non-Isolated Converter Topologies

7
 Boost Converter (Step Up)
VIN(t) L VOUT VGS(Q)
VOUT
VL D
CBYP COUT
VDS(Q)
VAC
Q IL BCM
IL

IDS(Q)
VIN(t) L VOUT

VL D ID
COUT tON tOFF
CBYP TS
VAC
Q IL
Boost CCM transfer function:
𝑉𝑉𝑂𝑂𝑂𝑂𝑂𝑂 𝑇𝑇𝑆𝑆 1
= =
𝑉𝑉𝐼𝐼𝐼𝐼(𝑡𝑡) 𝑡𝑡𝑂𝑂𝑂𝑂𝑂𝑂 1 − 𝐷𝐷

Inductor volt-second balance:  VIN < VOUT

〈𝑉𝑉𝐿𝐿 〉 𝑇𝑇𝑆𝑆 = 𝑉𝑉𝐼𝐼𝐼𝐼(𝑡𝑡) × 𝑡𝑡𝑂𝑂𝑁𝑁 + ��𝑉𝑉𝐼𝐼𝐼𝐼(𝑡𝑡) − 𝑉𝑉𝑂𝑂𝑂𝑂𝑂𝑂 � × 𝑡𝑡𝑂𝑂𝐹𝐹𝐹𝐹 � = 0  Most efficient at lower D
 Continuous input current
𝑉𝑉𝐼𝐼𝐼𝐼(𝑡𝑡) × (𝑡𝑡𝑂𝑂𝑂𝑂 + 𝑡𝑡𝑂𝑂𝑂𝑂𝑂𝑂 ) = 𝑉𝑉𝑂𝑂𝑂𝑂𝑂𝑂 × 𝑡𝑡𝑂𝑂𝑂𝑂𝑂𝑂
 CCM, BCM, DCM modes
𝑉𝑉𝐼𝐼𝐼𝐼(𝑡𝑡) × 𝑇𝑇𝑆𝑆 = 𝑉𝑉𝑂𝑂𝑂𝑂𝑂𝑂 × 𝑡𝑡𝑂𝑂𝑂𝑂𝑂𝑂
8
 VIN(t) L VOUT

Operating Mode CBYP

IL D
COUT
VAC
CCM, BCM or DCM Q VDS
VGS

IL(PK) IL(PK)
IL(PK)
∆IL ∆IL
IL(MIN)
IL IL ∆IL

0A 0A
0A
VOUT VOUT

VDS VDS VDS

VIN

2x(VIN – VOUT)
0V 0V 0V
VGS VGS VGS

0V 0V 0V
tON tOFF t tON tOFF tRES t tON tOFF tD t

TS TS TS

CCM BCM DCM

(Fixed Freq) (Variable Freq) (Fixed Freq)

9
 Buck Converter (Step Down)
L VOUT
VGS(Q)
VIN+VF
VL
Q COUT
CIN VDS(Q)
VIN D VIN
IL
VD
VIN-VOUT VF
VL
-VOUT
L VOUT

VL IL
Q COUT
CIN
VIN D IDS(Q)

ID
tON tOFF
TS

Inductor volt-second balance: Buck CCM transfer function:

〈𝑉𝑉𝐿𝐿 〉 𝑇𝑇𝑆𝑆 = [(𝑉𝑉𝐼𝐼𝐼𝐼 − 𝑉𝑉𝑂𝑂𝑂𝑂𝑂𝑂 ) × 𝑡𝑡𝑂𝑂𝑂𝑂 ] − 𝑉𝑉𝑂𝑂𝑂𝑂𝑂𝑂 × 𝑡𝑡𝑂𝑂𝑂𝑂𝑂𝑂 = 0 𝑉𝑉𝑂𝑂𝑂𝑂𝑂𝑂 𝑡𝑡𝑂𝑂𝑂𝑂
= = 𝐷𝐷
𝑉𝑉𝐼𝐼𝐼𝐼 𝑇𝑇𝑆𝑆
𝑉𝑉𝐼𝐼𝐼𝐼 × 𝑡𝑡𝑂𝑂𝑂𝑂 = 𝑉𝑉𝑂𝑂𝑂𝑂𝑂𝑂 × (𝑡𝑡𝑂𝑂𝑂𝑂 + 𝑡𝑡𝑂𝑂𝑂𝑂𝑂𝑂 )  VIN > VOUT
𝑉𝑉𝐼𝐼𝐼𝐼 × 𝑡𝑡𝑂𝑂𝑂𝑂 = 𝑉𝑉𝑂𝑂𝑂𝑂𝑂𝑂 × 𝑇𝑇𝑆𝑆  Most efficient at higher D
10
 Buck-Boost Converter (Inverting)
D -VOUT
VGS(Q)
VIN
VIN+|-VOUT| -VOUT
Q COUT
CIN VDS(Q)
VIN L VL
VIN
IL
VL
VOUT-VF

IL
D -VOUT

IDS(Q)
Q COUT
CIN
VIN L VL
ID
tON tOFF
IL TS

Inductor volt-second balance: Buck-Boost CCM transfer function:

〈𝑉𝑉𝐿𝐿 〉 𝑇𝑇𝑆𝑆 = 𝑉𝑉𝐼𝐼𝐼𝐼 × 𝑡𝑡𝑂𝑂𝑂𝑂 + 𝑉𝑉𝑂𝑂𝑂𝑂𝑂𝑂 × 𝑡𝑡𝑂𝑂𝑂𝑂𝑂𝑂 = 0 𝑉𝑉𝑂𝑂𝑂𝑂𝑂𝑂 𝐷𝐷
= −� �
𝑉𝑉𝐼𝐼𝐼𝐼 × 𝑡𝑡𝑂𝑂𝑂𝑂 = −(𝑉𝑉𝑂𝑂𝑂𝑂𝑂𝑂 × 𝑡𝑡𝑂𝑂𝑂𝑂𝑂𝑂 ) 𝑉𝑉𝐼𝐼𝐼𝐼 1 − 𝐷𝐷
𝑉𝑉𝑂𝑂𝑂𝑂𝑂𝑂 𝑡𝑡𝑂𝑂𝑂𝑂 /𝑇𝑇𝑆𝑆 𝑡𝑡𝑂𝑂𝑂𝑂 /𝑇𝑇𝑆𝑆  VIN < VOUT or VIN > VOUT
= −� � = −� �
𝑉𝑉𝐼𝐼𝐼𝐼 𝑡𝑡𝑂𝑂𝑂𝑂𝑂𝑂 /𝑇𝑇𝑆𝑆 (𝑇𝑇𝑆𝑆 − 𝑡𝑡𝑂𝑂𝑂𝑂 )/𝑇𝑇𝑆𝑆  Used for negative VOUT
11
Single Ended Converter Topologies

12
 Benefits of a Transformer
1. Provides primary to secondary safety isolation – subject to regulatory standards

AC DC
AC Output Load
(or DC)

2. Voltage conversion resolution

L D1 L

VO VO N
VIN Q1 VO =D NP NS
D2 CO VO = S D
D1 VIN VIN N P
CIN CO VIN CIN

Q1

Ex: For FSW=300kHz (TSW=3.33µs), NP:NS=4:1, 36V<VIN<75 and VO=5V

Buck Converter Isolated Buck (Forward) Converter

6% < D < 14% 27% < D < 55%

200 ns < tON < 467 ns 900 ns < tON < 1.8 µs

3. Potential ground differences between primary and secondary

4. Multiple outputs can be regulated/quasi-regulated

13
 Transformer Characteristics
NP NS CP-S(MUTUAL)

LP(LEAK) LS(LEAK)
VIN VOUT RP RS
NP NS

RCORE LMAG
CP(W) CS(W)
 Ideal transformer
 Perfect coupling between Np:Ns
Parasitic Transformer Model
 No energy storage

NP NS VGS

VIN VOUT
Overshoot/ringing due to
Leakage Inductance

 Flyback “transformer”
 Really a coupled inductor
VDS
 Primary energy stored during tON
 Power transferred during tOFF
CCM Flyback (VDS = 32 V, VLK = 12 V)

14
 Single Ended Topologies Defined
Single Ended – Transformer operation limited to first quadrant
B ∝ Vt B ∝ Vt
+BSAT +BSAT
B2 B2
∆B ∆B
B1 B1

H ∝ NI H ∝ NI

UNGAPPED

GAPPED
-BSAT -BSAT

(a) Forward Converter Transformer Hysteresis (c) Gapped Flyback “Transformer”

D1 L D

Reset NP NS NP NS
Circuit D2 CO CO VO
CIN VIN CIN

Q1 RESET CIRCUIT: Q1
1. Third winding
2. RCD reset
3. Resonant reset
(b) Forward Converter 4. Active clamp reset (b) Flyback Converter

15
 Flyback Converter Derivation
D -VOUT D VOUT

n:1
Q COUT COUT
CIN CIN
VIN L VIN LM

(a) (d)
D -VOUT VOUT

1:1 n:1
Q COUT COUT
CIN CIN
VIN L VIN LM

Q D

(b) (e)
D -VOUT
a) Non-isolated buck-boost
1:1
CIN
Q COUT b) Coupled inductor buck-boost
VIN LM c) Isolated buck-boost
d) Isolated flyback converter
e) D can be in return path
(c)
16
 Flyback Converter
CCM Operation
VOUT
PWM
NP n:1 NS COUT
CIN 0
VIN LM VIN+(NP/NS)VOUT

Q VDS
D

0
(a) Flyback Converter VOUT
VS
0
 CCM Transfer Function
-(NS/NP)VIN
VO N S D
= × IQ1
VIN N P 1 − D 0
 Limitations ID1
0
 Q1 switching loss (hard switched)
IL
 D2 conduction loss 0
 Q1(VDS) > VIN
(b) CCM Waveforms
 50% duty cycle limit
 Right half plane zero in CCM
 Output rectifier reverse recovery

17
 Quasi-Resonant Flyback
Conventional Valley Switching

Wide frequency variation depends on output load condition

iD

T1
t
Output load decreases
vDS

t Operating frequency
increases
iD T2
fS [Hz]

t
PSwitching Loss ∝ COSSV DS2 f S
vDS

t
Output Power [W]

18
 Quasi-Resonant Flyback
Window Valley Switching
Tsmax=10.8us
Light Load tW=3.0us
tB=7.8us
 Frequency variation depends
on output load conditions
(a)
fs_A=110kHz
 Operating frequency is within
narrow variation (127.5 kHz
~ 92.6 kHz)
(b) fs_B=122kHz

vDS (100V/div)

(c) fs_C=127.5kHz

iD (100mA/div) Time scale 2usec/div

(d) fs_D=92.6kHz

Heavy Load
19
 Two-Switch, Quasi-Resonant Flyback
VIN
(FROM PFC) D5 D4

FAN7382 Q1
VHS D3
PBIAS 1 VCC VB 8
C2
2 HIN HO 7 D1 VLED C1

C3
3 LIN VS 6
D2 VA
Q2
4 COM LO 5

R3 R1

R2 CC
FB CV

FAN6300H R4
1 DET HV 8 ACIN

2 FB NC 7

3 CS VDD 6 PBIAS

4 GND GATE 5 RDY

(FROM PFC)

20
 Two-Switch Quasi-Resonant Flyback
Switching Waveforms
VIN+VHS
VGS(HS)
VIN
 Quasi-resonant, variable frequency
PBIAS
VGS(LS)  HS and LS MOSFETs switch synchronously
0V

IDET(SOURCE)>30µA
 Switching period, TS = tOFF + tf + tON
tDELAY=200ns
 Inductor current switches from 0 A (ZCS)
0V
VA VA
every switching cycle
5µs
 VDS
VO
OVP
 ZVS → VOUT > 2×VIN
2.5V

VDET 0.7V
 Valley switch → otherwise
0V  Window valley switching
IDS

0A

ID

0A

VIN VRO
2 2

VDS VRO
VIN 2
2
0V
tOFF tf tON

TS

21
 Two-Switch Quasi-Resonant Flyback
Measured Waveforms

 VDS Valley Switching on First Valley  Extended Window Valley Switching

 VOUT < ½ VIN  VOUT < ½ VIN
 D = 42%  D = 11%
 FS = 63 kHz  FS = 68 kHz
 POUT = 85 W  POUT = 24 W

22
 Forward Converter Basics
D1 L

PWM
NR NP NS D2 CO VO 0
CIN
VIN VR+VIN
D3 Q1 VIN VDS(Q1)
0
VIN
(a) Forward Converter with Reset Winding
0 VP
N
VR = −VIN × P
NR
IMAG
 Really a Transformer Coupled Buck 0

 CCM Transfer Function 0 IQ1

0 IL
VO N
= S ×D
V IN N P 0 ID1

 Limitations 0 ID2

 Q1 switching loss (hard switched)

(b) DCM Waveforms (D<0.5)
 D2 conduction loss
 Q1(VDS) > 2 VIN
 50% duty cycle limit (NP:NR = 1:1)

23
 Problems with Duty Cycle > 50%
Equal Vxt Area
VP VIN  Common practice is to use 1:1 bifilar
transformer winding for NP:NR
0
t

− VIN ×
NP  D = 40%
NR
IMAG  Converter operates in DCM
 Transformer is completely reset on every
switching cycle
DTS D2TS D 3T S
t
TS

Unequal Vxt Area

VP VIN
 D = 67%
 Converter wants to operate in CCM
D=40% t  Transformer can NOT reset on every
NP
switching cycle
− VIN ×
D=67% NR
 IMAG increases due to volt second product
imbalance
IMAG  Transformer saturation will result
 Operation beyond D = 50% requires
additional reset voltage
DTS D2TS
t
TS 2TS 3TS

24
 Duty Cycle Greater Than 50%
NP NR NS
VDS vs Vin  For NP:NR = 1:2
Third Winding Reset
 VDS=3VIN
216
204
192
180 Q1 VDS
168
VDS (V)

156
144 Equal Vxt Area
132 VP VIN
120
108
96
84
72 } NP:NR=1:1 t

36 42 48 54
Vin (V)
60 66 72
D=67%
NP
} NP:NR=1:2
− VIN ×
NR
Np:NR=1:1 Np:NR=1:2

IMAG

DTS D2TS
t
TS 2TS 3TS

Conclusion: Reset winding technique, D > 50% not practical for high VIN applications
due to additional MOSFET VDS stress
25
 Active Clamp Forward Converter
D1 L

CCL
 Advantages
NP NS
D2 CO
 Reduced MOSFET VDS voltage stress
Q2
CIN  Higher efficiency through ZVS
Q1
 Use of parasitic elements
 Higher frequency operation
 Suitable for off-line (HS clamp) or DC-DC (LS
PWM
0
clamp)
Q2 VGS
 Disadvantages
0  Conditional ZVS only
VIN+VCL
Q1 VDS
 Dual primary side gate drive with accurate dead-
0 time control and max duty cycle clamp required
IMAG
 Poor transient response due to CCL
ICL
 Transfer Function
IQ1
0
VO N
IP
= S ×D
0 V IN N P
VIN
0 VP
VRESET

26
 Active Clamp Forward Converter
Two Versions
D1 L D1 L

CCL
NP NS CO NP NS
D2 D2 CO
Q2 CCL
CIN CIN
Q2
Q1 Q1
(a) High-Side Active Clamp (b) Low-Side Active Clamp
(Flyback Clamp) (Boost Clamp)

PARAMETER HIGH-SIDE ACTIVE CLAMP (off-line) LOW-SIDE ACTIVE CLAMP (telecom)

VDS  1   1 
  × V IN   × V IN
1− D  1− D 
VRESET  D   D 
  × V IN   × V IN
1− D  1− D 
 D   1 
VCL   × V IN   × V IN
1− D  1− D 

CCL Lower voltage by VIN volts Higher voltage by VIN volts

(applied voltage) Highest VCL occurs at DMAX Not practical for off-line
CCL Same value as low-side for given ripple Same value as high-side for given ripple
(cap value) voltage voltage
Clamp MOSFET N-Channel P-Channel
(Q2) Can be used for > 500 V Can be used up to 500 V
Gate Drive Gate drive transformer required Level shifting gate drive required

27
 Active Clamp Forward Converter
Zero Voltage Switching (ZVS)

 ZVS occurs when the voltage across the MOSFET, VDS, is positioned to “zero
volts” prior to the start of the next switching cycle.
 Benefits of ZVS
 Reduced switching losses
 Higher operating frequency possible (smaller passive component size)
 Higher converter efficiency
 Increased reliability
 Reduced radiated emissions (EMI)

VDS

ID

PSW=VDS x ID x FSW

(a) Hard Switching (b) “Ideal” ZVS

28
 Active Clamp Forward Converter
Zero Voltage Switching (ZVS)

 Parasitic elements can be used to benefit ZVS

CD1
CP-S(MUTUAL)

LP(LEAK) LS(LEAK) RS D1 L
RP
NP NS
CCL
CDS RCORE LMAG
D2
CP(W) CS(W) CO
Q2 D2 CD2

CDS
Q1 D1 VDS

 Active Clamp Forward converter uses fixed frequency resonant transitions

to achieve ZVS when specific operating conditions are met

29
 Single Ended (<500W)
2 Switch Forward Converter
Q2
 Advantages
D1 L
 Ruggedness
D4 D3
CIN NP NS
D2 CO  MOSFET voltage stress limited to VIN
 Magnetizing energy recycled by D3,
Q1
D4
 Universal input, 150 W < P < 500 W
PWM
0
(Q1, Q2)  Disadvantages
VIN  Limited to less than 50% duty cycle
VDS
VIN/2 (Q1, Q2)  High side gate drive required for Q2
0
VIN/NP  Hard switching
0 VS
-VIN/NP  Transfer Function
0 IMAG
0 ID3, ID4 VO N
= S ×D
V IN N P
0 IQ1, IQ2
IO IL

ID1
0

ID2
0

30
 Single Ended (>1kW)
Interleaved 2 Switch Forward Converter

 Advantages Q2
D1 L

 Can operate multiple power stages out of D4 D3 NP NS

CIN D2 CO
phase
 Ripple current cancellation at output Q1
capacitor
 Reduced RMS current at input capacitor Q4
D5 L
 Multiple stages can add up to kW of power D8 D7 NP NS
 Smaller output inductors can improve D6

transient response Q3

 Disadvantages
Qn
 Design complexity Dn L

 PCB layout can be challenging Dn Dn NP NS

Dn

Qn

31
Double Ended Converter Topologies

32
 Double Ended Topologies Defined

Double Ended – Transformer operation occurs in first and third quadrants

B ∝ Vt B ∝ Vt
+BSAT +BSAT
B2
(RCD Reset) ∆ B
B2 B2
B1
∆ B (Active Clamp)
H ∝ NI
∆B H ∝ NI
B1
B1

-BSAT -BSAT

Half-Bridge, Full-Bridge Active Clamp Forward

 Symmetrical operation between first  “Single ended” but operates slightly into
and third quadrants the third quadrant
 No transformer reset circuitry required

Normal
Flux Imbalance

Saturation
Primary Current
33
 Double Ended (<500 W)
Half Bridge Converter (Symmetrical)
Q2
D1 L
 Advantages
NP
C1
NS CO  Better transformer utilization
CIN VP
 MOSFET voltage stress limited to VIN
NS
C2
Q1
 Best for high VIN off line applications up to
D2 500W
 Single winding primary
PWM, Q1
 Transformer balanced by C1 and C2
PWM, Q2  Asymmetric and resonant versions can ZVS
VIN/2
VP  Disadvantages
-VIN/2
VIN  Totem pole primary gate drive
VDS(Q1, Q3)
VIN  High primary current
VDS(Q2, Q4)
 Possible cross conduction between Q1 and
IP Q2
 Hard switching
ID1  Transfer Function
VO N
ID2 = 2× S × D
IO IL
VIN NP

34
 Asymmetrical Half Bridge Converter
Vd
0
Symmetric square waveform + + +
Vd Vp Vp

Vd - - -
0
Asymmetric square waveform 1:1

What if an asymmetric square wave is introduced to the transformer?

 Transformer will be saturated
What if an asymmetric square wave is introduced to the transformer in series
with a DC blocking capacitor?
 Not saturated due to the voltage of the blocking capacitor, CB
+ VCB -

Same area
+ + +
Vd CB Vp Vp
0
0 - - -
1:1 VCB

35
 Asymmetrical Half Bridge Converter
D=0.46 D=0.23 D1 L
Q2
Q2 (D) NP
NS CO
Q1 (D)
CIN VP
VIN/2
VIN/2 NS
VP CB VO N
= 2 × S × D × (1 − D )
Q1
-VIN/2
-VIN/2 D2 V IN NP
IP

 Asymmetrical Gate Drive

(a) Symmetrical HB waveforms  Q2 modulated by D
 Q1 driven by 1-D
D=0.46 D=0.23

Q2 (D)
 Fixed dead time between Q1 and Q2
Q1 (1-D)
 Dead time optimized for ZVS and anti cross
VIN-VCB
Equal conduction
Area
VIN-VCB
 Fixed frequency ZVS PWM operation
VP
VCB VCB  Near D=0.5, operation is same as symmetrical HB
IP
 BUT, excessive voltage stress is applied to
(b) Asymmetrical HB waveforms secondary rectifier at VIN(MAX)
36
 Asymmetrical Half Bridge Converter
 Secondary rectifier voltage stress: Asymmetrical Half Bridge
VD vs D, VO=50 V

VD1 = D × VO VD 2 = VO × (1 − D ) 40
35

Diode Voltage Stress (V)

30
 Reverse recovery and parasitic 25
ringing 20

 Wide ∆D range requires use of high 15

10
voltage rectifiers 5
 Converter operates best near D = 0.5 0
0.20 0.23 0.26 0.29 0.32 0.35 0.38 0.41 0.44 0.47 0.50
Duty Cycle
 Advantages
VD1 VD2
 Fixed frequency ZVS
 Constant power transfer (D and 1-D) reduces output ripple
 Power stage can be controlled using any active clamp PWM controller
 Disadvantages
 High voltage stress on secondary rectifier
 Poor transient response due to blocking capacitor, CB

37
 LLC Resonant Half Bridge Converter
 Square wave generator: produces a square wave voltage, Vd by driving
switches, Q1 and Q2 with alternating 50% duty cycle for each switch.
 Resonant network: consists of Llkp, Llks, Lm and Cr. The current lags the voltage
(inductive) applied to the resonant network which allows the MOSFET’s to be
turned on with zero voltage.
 Rectifier network: produces DC voltage by rectifying AC current
Ip

Im

Square wave generator

Ids2

Q1 resonant network Rectifier network

Ip Io ID
Vin n:1 ID
Vd +
Llkp Llks Ro
Vin
Q2 VO Vd
Im (Vds2)
Lm -
Ids2 Cr
Vgs1

Vgs2

38
 LLC Converter Characteristics
1 1
 Two resonant frequencies fP = fO =
2π (LM + Lr )Cr 2π Lr Cr
(fo and fp) exist LLC Resonant Converter
 The gain is fixed at resonant fp fo
1.8
frequency (fo) regardless of the load Lr / Cr
variation Q=0.2 Q=
1.6 Rac

M @ f = fo = 1 1.4
Q= 1
Q= 0.8
Q= 0.6
 Peak gain frequency exists between 1.2 Q= 0.4
fo and fp

Gain
Q= 0.2

 As Q decreases (load current 1.0

decreases), the peak gain frequency

moves to fp and higher peak gain is 0.8
Q=1
obtained
 As Q increases (load current =M 1=
when f s f o 2nVO
0.6
M=
increases), peak gain frequency Vin
moves to fo and the peak gain drops 0.4
40 50 60 70 80 90 100 110 120 130 140
Freq (kHz)

39
 LLC Topology Variations

Primary Side Variation Secondary Side Variation

Lr Q1
Q1 ½ Cr
Ro + Ro +
Lm Lr

Cr VO VO
Lm
VIN - -
VIN Q2 Q2

½ Cr Full bridge rectifier with 2 Rectifier diode with center

single winding tab winding
Transformer across the Split resonant capacitor
high side MOSFET

Ro + Ro +
Q1 Q1
½ Cr
Lr VO VO

- -
Lr Lm
VIN
Q2 VIN
Lm Q2 Voltage doubler rectifier Synchronous rectifier with
Cr with single winding center tab winding
½ Cr

Transformer across the low Split resonant capacitor with

side MOSFET clamping diode

40
 LLC Resonant Half Bridge Converter

 Advantages of the LLC resonant converter

 Narrow frequency variation range over wide load range
 Zero voltage switching even at no load condition
 Reduced switching loss through ZVS  Improved efficiency and EMI
 When the two magnetic components are implemented with a single core (use
the leakage inductance as the resonant inductor), one component can be
saved

 Disadvantages of the LLC resonant converter

 Can optimize performance at one operating point, but not with wide range of
input voltage and load variations (too wide frequency range)
 Difficult to regulate the output at no load condition
 Significant current may circulate through the resonant network, even at the no
load condition
 Quasi-sinusoidal waveforms exhibit higher peak values than equivalent
rectangular waveforms
 High output current ripple

41
 Double Ended (<500W)
Push Pull Converter
D1 L
 Advantages
NP NS CO  Lower primary current compared to HB
NP NS
 Best for lower VIN, such as telecom DC-
CIN DC of US Line Voltage
Q2 Q1
D2
 Simple low-side gate drive
 Low output current ripple
 Disadvantages
PWM, Q1
 High voltage (2xVIN) on primary
PWM, Q2
MOSFETs
IQ1
 Transformer flux walking (VMC only)
IQ2  Center tapped transformer structure
2VIN
 Hard switching
VDS(Q1)
2VIN  Transfer Function
VDS(Q2)
VO N
= 2× S × D
ID1 V IN NP

ID2

IO IL

42
 Double Ended (>500W)
Full Bridge Converter (PWM)
D1 L
Q1 Q3  Advantages
NS CO  MOSFET voltage stress limited to VIN
NP
CIN
 Twice the power compared to half
NS
bridge
Q2 Q4
D2  Single winding primary
Gate, Q1  Disadvantages
Gate, Q2  Dual, totem pole primary gate drive
Gate, Q3
 Hard switching (Non-ZVT)
 Parasitics degrade circuit performance
Gate, Q4
VIN  Circuit complexity
-VIN VP
VIN
 Transfer Function
VDS(Q1, Q4)
VO N
VIN VDS(Q2, Q3) = 2× S × D
VIN NP
IP

ID1

ID2
IO IL

43
 Double Ended (>500W)
Phase Shifted Full Bridge Converter
Q1 Q3
D1 L
 Advantages
NS CO  High Efficiency ZVS
CIN NP
 Highest single stage processing power
NS
Q2 Q4
 MOSFET voltage stress limited to VIN
D2  Twice the power compared to half bridge
Gate, Q1  Full wave rectified secondary
Gate, Q2  Single winding primary
Gate, Q3  Excellent choice for EU line voltage (PFC pre-
Gate, Q4
VIN
regulator) with output power >1kW
-VIN
VP
 Disadvantages
VIN VDS(Q1, Q4)  Dual, high side primary gate drive
VIN VDS(Q2, Q3)
 Circuit complexity
IP  High circulating primary current for ZVS
ID1  Loss of ZVS at light load current
ID2  Transfer Function
IO IL VO N
= 2× S × D
Freewheel

Freewheel
Power

Power

VIN NP

44
 Phase Shifted Full Bridge Converter
ZVS Waveforms
Q1 Q3

Q2 Q4

Q2 (P→A)
VDS, VGS

Q1 Q3

Q2 Q4

Q4 (A→P)
VDS, VGS

(a) IO = 100% (b) IO = 35% (c) IO = 0%

A=“Active” or power phase
P=“Passive” or freewheel phase
45
 Current Doubler Rectifier

What is it? - A full wave alternative rectification technique compatible with all
double ended converter topologies
Derivation of Current Doubler
D1 L D1 D1 D1

NS CO VO NS CO VO V CO VO I CO VO
L
NP NP I V
NS NS V I

D2 D2 D2 D2
(a) (b) (c) (d)

D1
L1 Current Doubler L1

L1 CO VO Q1 CO VO
D1 CO VO
NP NS NP NS
NP NS
D2 Q2
L2
OR L2
L2 (f) (g)

D2
(e)

46
 Phase Shifted Full Bridge with Current Doubler
L1 Gate, Q1
Q1 Q3
Gate, Q2
D1 CO
CIN Gate, Q3
D2

Q2 Q4
Gate, Q4
L2 t0 t1
VP
L1
Q1 Q3
IP
D1 CO
CIN
D2
VL1
Q2 Q4 IL1
L2 t1 t2
VL2

Q1 Q3
L1 IL2
IO=IL1+IL2
D1 CO
CIN
D2
t0 t1 t2 t3 t4
Q2 Q4 Current Doubler Timing Diagram (PSFB Application)
L2 t2 t3

 Better thermal distribution for higher current outputs

L1
Q1 Q3
 Each inductor carries half the load current at half
CIN
D1 CO
the switching frequency
D2
 Ripple currents cancel as a function of D
Q2 Q4
L2 t3 t4  Single winding secondary
47
 High Power Topology Summary
Topology Transformer Primary VDS “Ideal” Application
Switches

CCM Boost Inductor 1 VOUT High power PFC > 300 W

(non-isolated) Interleaved PFC > Several kW

BCM Boost Inductor 1 VOUT PFC < 300 W

(non-isolated) Interleaved PFC < 1 kW

Forward Single-end 1 2xVIN < 200 W, universal off-line or telecom

Active Clamp Single-end 2 < 500 W, universal off-line or telecom,

1
VIN × highest efficiency required
1− D

2-Switch Forward Single-end 2 VIN < 500 W, universal off-line, PFC pre-
regulator

Half Bridge Double-end 2 VIN < 500 W, EU off-line, Intermediate Bus

Converters

Push Pull Double-end 2 2xVIN < 500 W, telecom or low VIN (< 200 V)

Full Bridge Double-end 4 VIN > 500 W, universal off-line

Phase Shifted FB Double-end 4 VIN > 1 kW, universal off-line or telecom,

highest efficiency required

Current Doubler Double-end NA NA Any double-ended topology, low VOUT,

high IOUT most benefit

48
 Summary

 Power Converter Topology Trends:

 Advanced control algorithms breathing new life into classic topologies…
 Buck → multiphase buck
 Boost → BCM boost
 Flyback → QR flyback
 Forward → active clamp forward
 Half bridge → LLC resonant
 Full bridge → PSFB

 The innovation trends are in new control methods that are pushing the limits of
power processing, converter size, and operating frequencies.
 Better uses of zero-voltage switching and zero-current switching for lower
stresses
 Better use of parasitic elements
 Digital techniques including non-linear and multi-variant control
 Better synchronous rectification timing control

49